White Paper Designing with FinFETs: The Opportunities and the Challenges Author Jamil Kawa R&D Group Director, Synopsys, Inc Introduction With the help of double-patterning and other advanced lithography techniques, CMOS technology continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs are replacing planar FETs (also called “planar CMOS”) as the device technology of choice at these advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage and dynamic power, intra-die variability, and retention voltage for SRAMs. FinFET devices have a significantly more complex topology than planar FET devices. In addition, their design features and characteristics are quite different, creating many questions for designers. For example, ` How much of the cumulative experience in planar FET design is applicable and transferrable to FinFET design? Can design flows and methodologies painstakingly developed over tens of years be reused? Or are we dealing with a radical change in design methodology? ` Are EDA tools ready for this transition? To what extent can they be ready, given the industry’s limited experience with FinFET as a device? ` Given the complex device models of the FinFET and of its associated parasitics, can designers (and analog designers in particular) rely on such device models as good predictors for designing robust circuits? The list of questions goes on and all represent relevant issues that have to be addressed by foundries and EDA companies to minimize or avoid design pitfalls and costly iterations. A superficial view of the custom design flow, especially as far as the design implementation steps are concerned, could lead one to conclude that the transition from planar FET to FinFET will be seamless and transparent to the designer. But the impact the FinFET device has on the design flow can be quite significant. What does that mean for the designer? Most likely, a longer and steeper learning curve than what is typical in a transition from one planer technology node to the next, as shown in Figure 1. In fact, the learning curve has already been expanding with each new planar node as a result of new lithography artifacts such as restricted design rules (RDR) and double patterning. The jump in complexity with FinFET is even more pronounced. September 2012
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White Paper
Designing with FinFETs: The Opportunities and the Challenges
Author
Jamil Kawa
R&D Group Director,
Synopsys, Inc
IntroductionWith the help of double-patterning and other advanced lithography techniques, CMOS technology
continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs
are replacing planar FETs (also called “planar CMOS”) as the device technology of choice at these
advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage
and dynamic power, intra-die variability, and retention voltage for SRAMs.
FinFET devices have a significantly more complex topology than planar FET devices. In addition, their
design features and characteristics are quite different, creating many questions for designers. For
example,
`` How much of the cumulative experience in planar FET design is applicable and transferrable to
FinFET design? Can design flows and methodologies painstakingly developed over tens of years
be reused? Or are we dealing with a radical change in design methodology?
`` Are EDA tools ready for this transition? To what extent can they be ready, given the industry’s
limited experience with FinFET as a device?
`` Given the complex device models of the FinFET and of its associated parasitics, can designers
(and analog designers in particular) rely on such device models as good predictors for designing
robust circuits?
The list of questions goes on and all represent relevant issues that have to be addressed by foundries and
EDA companies to minimize or avoid design pitfalls and costly iterations.
A superficial view of the custom design flow, especially as far as the design implementation steps are
concerned, could lead one to conclude that the transition from planar FET to FinFET will be seamless
and transparent to the designer. But the impact the FinFET device has on the design flow can be quite
significant.
What does that mean for the designer? Most likely, a longer and steeper learning curve than what is
typical in a transition from one planer technology node to the next, as shown in Figure 1. In fact, the
learning curve has already been expanding with each new planar node as a result of new lithography
artifacts such as restricted design rules (RDR) and double patterning. The jump in complexity with FinFET
is even more pronounced.
September 2012
Designing with FinFETs: The Opportunities and the Challenges 2
FinFET: The DeviceFigures 2 and 3 are simplified depictions of a planar FET and a FinFET, respectively. In the planar FET, a single
gate controls the source–drain channel. Such a gate does not have good electrostatic field control away from
the surface of the channel next to the gate, and as a result leakage currents between source and drain happen
even when the gate is “off”.
By contrast, in the FinFET, the transistor channel is a thin vertical fin with the gate fully “wrapped” around the
channel formed between the source and the drain. The gate of the FinFET can be thought of as a “multiple
gate” surrounding the thin channel. Such a gate can fully deplete the channels of carriers. This results in much
better electrostatic control of the channel and thus better electrical characteristics. The thin body of the fin
is a requirement to ensure that the wrapped gate has complete control of the channel. Figures 2 and 3 show
“bulk” planar and FinFET transistors. It is worth noting that fins can be formed on silicon-on-insulator (SOI)
structures as well.
The most important geometric parameters of a FinFET are its height (HFIN), its width or body thickness (Tsi), and
its channel length (Lg). Figure 4 demonstrates those parameters. The effective electrical width of a FinFET is the
planar width/body thickness Tsi plus twice the fin height HFIN.
28nm and below
More resources required
Res
ou
rces
Time
Longerdevelopment
time
FinFETDouble patterning
Planar FET
Gate
Drain
Source
Oxide
Siliconsubstrate
Gate
Drain
Source
Oxide
Siliconsubstrate
FinFET
Figure 1: Learning curve progression as a function of technology node
Figure 2: Planar FET Figure 3: FinFET
Designing with FinFETs: The Opportunities and the Challenges 3
A simplified representation of the key stages in the process of manufacturing FinFET structures is shown in
Figures 5, 6, and 7.
The definition of the active device areas is shown as the blue mandrels, or temporary supporting structures.
The fins (red) are formed by etching the mandrels (Figure 5). Then a cut mask is used to remove the unwanted
parts of the structure (Figure 6) leaving the final pattern (Figure 7).
Given that FinFET technology will be implemented at 20-nm or smaller geometries, double patterning
techniques will be needed for all critical layers. A “spacer double patterning” is usually the preferred technique
for patterning the fins.
At any one technology node, the FinFET has several advantages over its planar counterpart including (but not
limited to):
`` Very good electrostatic control of the channel. The channel can be “choked off” more easily. FinFETs
boast a near-ideal sub-threshold behavior (associated to leakage), something that’s not easy to
achieve in planar technology without considerable design effort.
`` Greatly reduced short channel effects (an effect that takes place when the channel length is the same
order of magnitude as the depletion-layer widths of the source and drain junction, making the specific
transistor behave differently from standard longer channel transistors). The short channel effects in
planar technology are complex and give rise to a large impact on gate length variations and therefore
on electrical performance.
`` High integration density, or 3D. Thanks to the vertical channel orientation of FinFETs, they deliver
more performance per linear “W” than planar even after the isolation dead-area between the fins is
taken into account.
`` Smaller variability, especially variability resulting from random dopant fluctuation primarily due
to doping-free channels. Also, variability associated with line-edge roughness (LER), the random
deviation of gate line edges from the intended ideal shape, which results in non-uniform channel
lengths, is lower in FinFETs
y Undoped or lightly doped channel: much lower dopant concentrations are necessary in the channel
region.
y Gate definition: the gate is defined from the top of the fin. The dominant part of the gate is defined
by etching processes, which have very low LER
“FinFET”(90ο rotation)
Source
Gate
Drain
Gate
Fin width = TSi
Source
Drain Gate Lg
Fin heightHFIN = W/2
Figure 4: FinFET geometric parameters. Dimensions are not to scale