MHz 1000 10,000 100,000 10GHz 1486 TM Pentium- Pro Processor Designing for Electro-Magnetic Compatibility K Salazar, University of Delaware ABSTRACT Recent regulations have demanded that electronics manufacturing companies control emissions from their products and the susceptibility of their products to emissions from other products. In addition, unexpected product failure and the ever-present demands of technology are also forcing the electronics industry to face the need to maintain electrical integrity. Our investigations into high-speed design techniques have shown three major causes of failure: emissions from interconnecting conductors; poor PCB layout and lack of technical knowledge in electromagnetic compatibility (EMC). Catching these kinds of electrical integrity problems early in the design phase allows designers to take timely action without jeopardising project time scales. The work reported here presents design for manufacturing guidelines and rules to maintain electrical integrity in printed circuit boards (PCBs). Currently, a common method for handling EMC is through compliance testing of the final product. Similarly, noise budget is measured on finished prototypes. Since product life cycles are reducing, dealing with EMC late in the design cycle is undesirable. The cost of fixing may also be higher at a final stage because only a few options are available to correct the problem. A ‘find and fix’ approach is no longer acceptable anymore. More and more companies are facing or will soon be facing EMC and electrical integrity issues. The majority of analysis tools available today are targeted toward simulation engineers. Such tools are not easy to use and are dependent on the availability and accuracy of complex simulation models. Moreover, they also tend to be ineffective on how to correct potential EMC problems. KEYWORDS: Design for Manufacture, EMC, PCB Design 1 INTRODUCTION The electronics industry is ever-changing, a good indication of these changes is to consider microprocessor performance over the last few years. The graph shown in Figure 1 illustrates the past, present and future trends in microprocessor clock frequency thus necessitating the need for signal integrity issues so as to prevent or minimise the effects of electro-magnetic interference. Interconnecting traces exhibit “parasitics” such as self inductance, self capacitance, mutual inductance and capacitance with their surroundings. These parasitics are very small factors with signals running at low frequencies, but cannot be ignored at high speed. Presently, the continual increase of clock frequencies and faster rise and fall times, cause interconnects to start act active as active elements of the design and interconnect delays start to become even greater then component delays. In other words, at higher frequencies, a signal trace becomes an interconnect component. A PCB trace alone can be represented as a transmission line consisting of series inductance and shunt capacitance elements distributed along the line. At high speed, a signal propagating down the line has to charge up each inductor and capacitor element before it is passed to the next element. It is intuitively easy to understand that this charging process has the effect of reducing the propagation time and increase the impedance of the trace.
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MHz
1000
10,000
100,000
10GHz
1486 TM
Pentium- Pro Processor
Designing for Electro-Magnetic Compatibility
K Salazar, University of Delaware
ABSTRACT
Recent regulations have demanded that electronics manufacturing companies control
emissions from their products and the susceptibility of their products to emissions from other
products. In addition, unexpected product failure and the ever-present demands of technology
are also forcing the electronics industry to face the need to maintain electrical integrity.
Our investigations into high-speed design techniques have shown three major causes of
failure: emissions from interconnecting conductors; poor PCB layout and lack of technical
knowledge in electromagnetic compatibility (EMC). Catching these kinds of electrical integrity
problems early in the design phase allows designers to take timely action without jeopardising
project time scales. The work reported here presents design for manufacturing guidelines and
rules to maintain electrical integrity in printed circuit boards (PCBs). Currently, a common
method for handling EMC is through compliance testing of the final product. Similarly, noise
budget is measured on finished prototypes. Since product life cycles are reducing, dealing with
EMC late in the design cycle is undesirable. The cost of fixing may also be higher at a final
stage because only a few options are available to correct the problem. A ‘find and fix’ approach
is no longer acceptable anymore.
More and more companies are facing or will soon be facing EMC and electrical integrity
issues. The majority of analysis tools available today are targeted toward simulation engineers.
Such tools are not easy to use and are dependent on the availability and accuracy of complex
simulation models. Moreover, they also tend to be ineffective on how to correct potential EMC
problems.
KEYWORDS: Design for Manufacture, EMC, PCB Design
1 INTRODUCTION
The electronics industry is ever-changing, a good indication of these changes is to consider
microprocessor performance over the last few years. The graph shown in Figure 1 illustrates the
past, present and future trends in microprocessor clock frequency thus necessitating the need for
signal integrity issues so as to prevent or minimise the effects of electro-magnetic interference.
Interconnecting traces exhibit “parasitics” such as self inductance, self capacitance, mutual
inductance and capacitance with their surroundings. These parasitics are very small factors with
signals running at low frequencies, but cannot be ignored at high speed. Presently, the continual
increase of clock frequencies and faster rise and fall times, cause interconnects to start act active
as active elements of the design and interconnect delays start to become even greater then
component delays. In other words, at higher frequencies, a signal trace becomes an interconnect
component. A PCB trace alone can be represented as a transmission line consisting of series
inductance and shunt capacitance elements distributed along the line.
At high speed, a signal propagating down the line has to charge up each inductor and
capacitor element before it is passed to the next element. It is intuitively easy to understand that
this charging process has the effect of reducing the propagation time and increase the impedance
of the trace.
Figure 1:Moore’s Law, Frequency with respect to time
Impedance is expressed as: Z = CL ---------- (1)
The characteristic impedance (electromagnetic wave resistance) of a PCB trace is
determined primarily by its width, the PCB material and the thickness between signal layer and
power plane. The physical construction of the PCB may be considered as a wave-guide made
up of trace geometry, dielectric insulator and planes. A typical PCB layer cross-section can be
can be divided in five different configurations: microstrip; embedded microstrip; dual microstrip;
stripline and dual stripline. Each configuration has its own characteristic impedance and
propagation delay.
2 CROSS-SECTIONS OF VARIOUS TRANSMISSION LINE CONFIGURATIONS
Microstrip : A track routed over a solid ground plane.
Embedded Microstrip: Same as microstrip but trace is buried in the insulator.
Dual microstrip: Two surface traces buried in the insulator.
Stripline: Case of a wire sandwiched between two planes.
Dual stripline: Two traces centred between two planes.
With reference to figure 2, a signal runs faster on microstrip configuration than on
stripline. So for a given delay, longer tracks are permitted with a microstrip configuration. It is
important to note that, a wire routed in microstrip is not shielded from emissions by the power
and ground planes as it would be the case of a wire routed in stripline.
L being the per unit length inductance and C the per unit length capacitance.
Microstrip Stripline
Figure 2: Cross-sections of various transmission line configurations
Shielding in case of stripline gives typically a reduction of emissions by up to 10bB. For
high speed boards, place power and ground planes directly adjacent. This will maximise the
capacitive coupling and thus reduce supply noise. Also use extra ground planes (and not pwer
planes) to isolate routing layers. For example, for an 8 layer PCB (4 routing), the best
assignment for EMC performance is S1, G, S2, G, P, S3, G, S4 where S = signal routing layer, G
= ground plane and P = power plane.
3 PROPAGATION DELAY
Propagation Delay is a complex function of many parameters including incluing inpedance
and loading. Intended functionality requires that timing constraints have to be defined. Here are
two examples. Delay control, see figure 3, if Tpd is too long, then the pulse will arrive too late
for the intended function.
Figure 3: Delay control
Skew management, see figure 4, the path delay of A+C OR B+C must be equal to D within
device tolerance. Important factors for skew management are gate propagation delays and
copper trace delays. Effective skew management is ideally performed in the time domain not in
the geometrical domain.
Figure 4: Skew management
4 ATTENUATION
At high frequencies, current density no longer becomes evenly distributed in the cross-
section of the trace. The current density becomes higher near the surface of the trace and the
resistor of the conductor increases. This skin effect has a consequence on the high harmonic
frequencies and is responsible for signal degradation and attenuation. Because of the skin effect,
a square pulse shape will become slightly rounded. Also, while the resistance increases with the
frequency, the intrinsic trace inductance reduces and it is then the loop inductance that becomes
the dominant paramater in thecharacteristic impedance. This inductance is a function of the
geometry of the signal and its ground return path. In order to minimise these effects with high
speed signals, short and wide tracks are highly recommended.
Figure 5: Effects Attenuation on an original pulse
Original pulse
Effects of attenuation
5 REFLECTIONS
A signal propagating down a lossless line of constant characteristic impedance will
travel along the line without distortion. However, when the signal arrives at the end of the line
(after Td time), reflection will occur if the load impedance does not match the impedance of the
conductor, see figure 6. The reflected wave travels back down the line and after Td time, it hits
the source and is reflected back again but now from the source.
Figure 6: Chronlogy of a reflection
The signal is partially reflected, the amount of reflection is dependent on the magnitude of
the impedance mismatch. The reflection coefficient, expressed as a percentage can be calculated
as:
)0(
)0(100
ZZs
ZZsKref
------------- (2)
When the rise time of the signal is greater than the propagation delay down the trace, the
reflections are masked by the slow rise of the signal. If the two-way propagation delay (source-
end-source) is longer than the rise or fall times, then the reflection from the far end arrived after
the initial transition is finished. The length beyond which the line should be terminated is given
by:
Td
TrL
2 ------------- (3)
Where: L = length of trace, Tr = edge rate, Td = loaded propagation delay.
Long nets may be subject to high amounts of reflection. For example, rise times of 2 nano-
seconds require special consideration when the trace length is greater then 14 cm (for the
stripline topology, FR-4 material). This length threshold is often called the critical length, it is
the maximum permissible unterminated trace length. Different logic families with characteristic
rise times will demand critical length of traces in order to reduce the impedance. Ensuring that
traces are kept under their critical length is often unpractical. In such cases a termination scheme
may be the best solution.
6 TERMINATION STRATEGIES
As mentioned earlier, in order to reduce reflections, the input impedance of the receiver
must appear to match the impedance of the inductor. The reflection coefficient, expressed in
percentage is calculated from equation (2). An input impedance of the receiver, larger than the
conductor’s impedance will cause over/undershoot, while the opposite will cause a drop in the
pulse. The side affects of termination area: additional of extra delay to the signal; extra power
consumption due to current requirement; and extra cost of component. Typically, such
termination methods are recommended by the semiconductor vendor. Methods of termination
comprise the following: series resistor; parallel resistor; Thevenin (split resistor); RC termination
and diode clamp. With the exception of the diode clamp strategy, all other termination methods
involve the output resistance of the driver that is non-linear and varies for most semiconductor
processes over a wide range.
7 TOPOLOGY
Timing constraints are taken into account when selecting the appropriate net topology to
control the arrival time of the signals at their respective receivers. Various topologies are used to
achieve different objectives, figure 7 illustrates commonly used net topologies.
Figure 7: Various net topologies
The star topology is characterised by multiple branches from a central driving point that
requires a strong driver. In this topology, series termination can be used, on each leg. However,
if branch length matching is not possible, then RC termination close to central point can be used.
In the case of the daisychain topology where loads are distributed down the line, together with a
strong driver there will be skew between loads. As such, parallel, Thevenin or RC termination
can be used. In point-to-point, connection between two points, when termination is required, a
series resistor at the source is recommended, with a resistor value optimised for a rising or failing
edge. This is dependent on how balanced the high/low impedance of the driver. In the case of
TEE (Far end cluster), essentially a variation of star topology, where loads are close together and
skew must be minimised. In this topology it is possible to use either series termination close to
the driver, or RC termination at the branching point to the loads. Finally, the H tree topology is
easier to drive than a star topology. With this method, each line from a tap to a load has the
same impedance, so the same termination resistor value can be used at each load. The other
advantage of the H-tree structure is that the wire length between the driver and each load is
identical, preventing such signal skew problems.
8 GROUND BOUNCE
Outputs are inductively coupled between power and ground, as the component switches
state. The sudden high current requirement will lead to a reverse voltage drop called ground
bounce or switching noise. To minimise the effect, decoupling capacitors should be used (with
low lead self inductance) and placed close to the component to be decoupled. The capacitor
maintains a constant voltage across the component and delivers a more stable current outside of
the general power planes. Since ground is more sensitive than VCC, the decoupling capacitor
should be located as close as possible to the ground pin. Extra capacitance is provided by the use
of multilayer PCB power and ground planes. In fact, ground bounce was the main contributing
effect to the change from double sided to multilayer PCB with power and ground planes. Care
should be taken when planes are getting heavily perforated, because this will cause the plane
inductance to increase. Currents in an imperfect ground plane flow from ground pins to the
power connector and can affect the voltage of other components with ground pins. High ground
currents in the plane are more likely to occur with bus and high current drivers, they should
therefore be located close to the power connector. It is important to ensure that self-resonant
frequency of decoupling capacitors is above the frequency of the signal to be decoupled.
9 CROSSTALK
A high speed trace behaves like a transmitting antenna. A sudden change of current on one
trace can cause capacitive and inductive coupling into adjacent traces. When this crosstalk level
is sufficient, a false signal transition can occur. The amount of coupling between traces is
proportional to the length of the two traces running in parallel and inversely proportional to their
spacing. Strategies for the reduction of crosstalk include: minimising the length of parallelism;
maximising trace spreading; lowering the thickness of the dielectric; minimising impedance;
minimising the edge rate and selecting the most appropriate termination strategy.
10 CONCLUSIONS EMI REDUCTION TECHNIQUES
In order to reduce electromagnetic interference, there are a number of approaches
including: minimising rise and fall times on clock and signal edges (see figure 8); utilising
slowest logic consistent with the circuit operation (see figure 9); and board partitioning to
minimise ground bounce effects (see figure 10).
Figure 8: Minimising rise and small times on signal and clock edges
Minimised rise and fall times on signal and clock edges. Sharper edges cause high
harmonic contents in the high frequency spectrum.
Figure 9: Using Slowest logic consistent with the circuit operation
Selection of the most appropriate logic family plays a key role in the overall EMC
performance. Logic families that are designed to operate at high frequency will exhibit sharp
edge rates. This will result in larger harmonic spectral contents. Figure 9 is ordered by the
noisiest at the top to the less noisy at the bottom. The ECL family is relatively less noisy, this is
simply because it has the small voltage swing. CMOS is slow and also has reduced drive
capability, this is why it is the best from an EMC standpoint.
Figure 10: Board partitioning
To minimise ground bounce effect, it is desirable to place high speed components close to
the power source with slower components placed further away. To minimise cross coupling and
thus system noise it is also advisable to create separate partitions for analogue and digital
sections. Furthermore, to prevent noise conducted through input/output IO cables, segregate IO
connectors, IO drivers/receivers and non-IO components. Provide extra spacing between highly
radiating nets and IO nets.
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Informatics and Control, 22(2), pp.195-204, ISSN: 1220-1766.
Page, T (2013) Use of Mobile Device Apps in Product Design, International Journal of Green
Computing, 4(1), pp.18-34, ISSN: 1948-5018. DOI: 10.4018/jgc.2013010102.
Page, T (2013) Smartphone Technology, Consumer Attachment and Mass Customisation,
International Journal of Green Computing, 4(2), pp.38-57, ISSN: 1948-5018. DOI:
10.4018/jgc.2013070104.
Page, T (2014) Application Based Mobile Devices in Design Education, International Journal of
Mobile Learning and Organisation, 8(2), pp.96-111, DOI: 10.1504/IJMLO.2014.062347.
Page, T (2014) Skeuomorphism or Flat Design: Future Directions in Mobile Device User
Interface (UI) Design Education, International Journal of Mobile Learning and Organisation,
8(2), pp.130-142, DOI: 10.1504/IJMLO.2014.062350.
Page, T (2014) Touchscreen Mobile Devices and Older Adults: A Usability Study, International
Journal of Human Factors and Ergonomics, 3(1), pp.65-85, DOI: 10.1504/IJHFE.2014.062550.
Karthikeyan, S, Asokan, P, Nickolas, S, Page, T (2014) A hybrid discrete firefly algorithm for
solving multi-objective flexible job shop scheduling problems, International Journal of Bio-
Inspired Computation, 6(4), pp.1-18.lboro tom page
Page, T (2014) Notions of Innovation in Healthcare Services and Products, International Journal
of Innovation and Sustainable Development, 8(3), pp.217-231, ISSN: 1740-8822.
Page, T (2014) Product attachment and replacement: implications for sustainable design,
International Journal of Sustainable Design, 2(3), pp.256-282.
Page, T (2014) Skeuomorphism or Flat Design: Future Directions in Mobile Device User
Interface (UI) Design Education, International Journal of Mobile Learning and Organisation,
8(2), pp.130-142, DOI: 10.1504/IJMLO.2014.062350.
Page, T. (2009) “Disruptive Innovation – A Strategy for New Product Development?”, Lambert
Academic Publishing, ISBN: 978-3-8383-3135-5.
Page, T. (2010) “Prospects for Microgeneration: Energy use, the environment and the wider
community”, Lambert Academic Publishing, ISBN: 978-3-8383-0517-2.
Page, T. (2010) “A Methodology for Decision-Support in Electronic Product Design” Lambert
Academic Publishing, ISBN: 978-3-8383-8246-3.
Page, T. (2010) “Carbon Emission in Domestic Energy Use” Lambert Academic Publishing,
ISBN: 978-3-8433-5863-7.
Page, T., Ichimura, M. and Arunachalam, S., (2011) “A Novel Workforce Training Model for
Lean Manufacturing: Training to be Lean” Lambert Academic Publishing, ISBN: 978-3-8433-
7886-4.
Page, T. (2011) “Can High Tech Swimwear Help You Swim Faster?” Lambert Academic
Publishing, ISBN: 978-3-8433-9128-3.
Page, T. (2011) “A Growth Model in the Use of LEDs in Commercial Lighting Design”
Lambert Academic Publishing, ISBN: 978-3-8443-0783-2.
Page, T. (2011) “Emotive Design Methods in Product Branding: Brand and Emotion and their
Relationship with Product Design” Lambert Academic Publishing, ISBN: 978-3-8443-1067-2.
Arunachalam, S. and Page T. (2011) “An Application of Data Mining Techniques in Data
Warehousing: A Case-Based Approach”, Lambert Academic Publishing, ISBN: 978-3-8433-
8037-9.
Arunachalam, S. and Page T. (2011) “Development of a Compressor Circuit for an Automatic
Sound Desk”, Lambert Academic Publishing, ISBN: 978- 3-8433-8567-1.
Page, T. (2011) “Influence of Social Networking in Electronic Product Design” Lambert
Academic Publishing, ISBN: 978-3-8465-1590-7.
Page, T. (2011) “Brand Identity in Consumer-driven Electronic Product markets” Lambert
Academic Publishing, ISBN: 978-3-8465-2238-7.
Page, T. (2011) “Design for Additive Manufacturing” Lambert Academic Publishing”, Lambert
Academic Publishing, ISBN: 978-3-8473-2294-8.
Page, T. (2011) “Radio Frequency Identification in Electronic Product Design”, Lambert
Academic Publishing, ISBN: 978-3-8465-9331-8.
Page, T. (2011) “Sustainable Product Development or Marketing Hype?”, Lambert Academic
Publishing, ISBN: 978-3-8433-6637-3.
Page, T. (2011) “Brand Innovation in FMCG”, Lambert Academic Publishing, ISBN: 978-3-
8443-1611-7.
Page, T. (2011) “Electronic Product Design of Home Entertainment Systems: A Study of
Consumer issues in Electronic Product Design”, Lambert Academic Publishing, ISBN: 978-3-
8465-3789-3.
Page, T. (2011) “Social Networking Technologies and Their Implications for Commerce”,
Lambert Academic Publishing, ISBN: 978-3-8465-4573-7.
Page, T. (2012) “Sci Fi and Electronic Product Design: Futurism in Design”, Lambert Academic
Publishing, ISBN: 978-3-8465-9656-2.
Page, T. (2012) “The Challenges of Sustainable Product Design: Studies in Electronic
Products”, Lambert Academic Publishing, ISBN: 978-3-8473-7122-9.
Page, T. (2012) “Electronic Product Design of Sports Equipment: Proliferation of Technology in
Sport”, Lambert Academic Publishing, ISBN: 978-3-8465-8524-5.
Page, T. (2012) “Light Emitting Diode (LED) Technology in Industrial Lighting Design: A
Study of Lighting Design”, Lambert Academic Publishing, ISBN: 978-3-8433-6073-9.
Page, T. (2012) “The Influence of Mobile Devices and Apps on Product Design: Design Tools
on the Move”, Lambert Academic Publishing, ISBN: 978-3-659-11120-4.
Page, T. (2012) “Sustainability in the Design of Electronic Consumer-Based Products: Models
and materials”, Lambert Academic Publishing, ISBN: 978-3-8484-0280-9.
Page, T. (2012) “Mobile Apps as Design Practice Tools in Education and Practice: Electronic
Product Design”, Lambert Academic Publishing, ISBN: 978-3-659-11733-6.
Page, T. (2012) “Healthcare Innovations: Service and Product Design”, Lambert Academic
Publishing, ISBN: 978-3-659-12465-5.
Page, T. (2012) “Technology of Car Crime Prevention: Evaluation of Anti-Theft Devices”,
Lambert Academic Publishing, ISBN: 978-3-8465-5344-2.
Page, T. (2012) “Intellectual Property and Business Competitiveness”, Lambert Academic
Publishing, ISBN: 978-3-659-15569-7.
Page, T. (2012) “Developing Technologies in Mobile Applications”, Lambert Academic
Publishing, ISBN: 978-3-659-15757-8.
Page, T. (2012) “Battery Technology in the Development of Power Tools”, Lambert Academic
Publishing, ISBN: 978-3-659-16369-2.
Page, T. (2012) “A Study of Smartphone Text Input Methods”, Lambert Academic Publishing,
ISBN: 978-3-659-16826-0.
Page, T. (2012) “Scientific and Technological Diffusion in Engineering Design: Technology
Transfer and New Futures”, Lambert Academic Publishing, ISBN: 978-3-659-17429-2.
Page, T. (2012) “A Usability Study of Automotive Control Screen Displays”, Lambert
Academic Publishing, ISBN: 978-3-8465-9722-4.
Page, T., ''Transmission End Beep Tone'', Radio Communication, 72(1), 1996, pp 42-43, ISSN
0033-7803.
Page, T., ''Automatic Tape Switch'', Radio Communication, 72(7), 1996, pp 35-36, ISSN 0033-
7803.
Page, T. and Milburn, R., ''Causes of Misregistration in Multilayer PCBs during Prepreg
Bonding'', Electronics Manufacturing Engineering: Society of Manufacturing Engineers,
Dearborn, MI, USA, 181, 2004, pp 12-18.
Ganesh, K., Nagarajan, S., Malairajan, R.A., and Page, T. “Special Issue on Heuristics and
Meta-Heuristics for Integrated Supply Chain Optimization Problems”. International Journal of
Information Systems and Supply Chain Management, 6(2), pp.iv-viii, April-June 2013.
Page, T. and Gilliatt, J., ''An Approach to the Assessment of Engineering Design Activity as
Practiced in the UK'', Advances in Manufacturing Technology, Proceedings of the 7th National
Conference on Production Research, Hatfield, UK, 1991, pp 162-166, ISBN 0-900458-46-1.
Page, T. and Parkinson, B., ''Functional Design'', Advances in Manufacturing Technology VII,
Proceedings of the 9th National Conference on Manufacturing Research, University of Bath,
UK, 1993, pp 1-5, ISBN 1-85790-005-7.
Page, T., ''Concurrent Engineering: Implications for a New Material Supplier/Customer
Relationship'', Advances in Manufacturing Technology VII, Proceedings of the 9th National
Conference on Manufacturing Research, University of Bath, UK, 1993, pp 1-5, ISBN 1-85790-
005-7.
Page, T., ''Concurrent Engineering: Simultaneous Design and Manufacture'', Advances in
Manufacturing Technology VII, Proceedings of the 9th National Conference on Manufacturing
Research, University of Bath, UK, 1993, pp 1-5, ISBN 1-85790-005-7.
Page, T. and Parkinson, B., ''Concurrent Engineering: An Educational Perspective'', Proceedings
of the 2nd International Conference on Concurrent Engineering & Electronic Design
Automation, Poole, UK, 1994, pp 208-212, ISBN 1-56555-074-9.
Page, T. and Beamish, J.C., ''A Knowledge-Based Tool for Conducting Design for Manufacture
in a Surface Mount Technology Environment'', Advances in Manufacturing Technology IX,
Proceedings of the 11th National Conference on Manufacturing Research, De Montfort
University, UK, 1995, pp 125-129, ISBN 0-7484-0400-7.
Page, T., Loke, S. and Arunachalam, S., ''The Integration of a Knowledge-Based System and a
Gantt Chart Scheduling Application for Solving the Machine Shop Scheduling Problem'',
Advances in Manufacturing Technology XII, Proceedings of the 14th National Conference on
Manufacturing Research, University of Derby, UK, 1998, pp 727-732, ISBN 1-86058-172-2.
Page, T., ''Implementation of Sample Design Rules in a Commercially Used PCB Design
Application'', Advances in Manufacturing Technology XIV, Proceedings of the 16th National
Conference on Manufacturing Research, University of East London, UK, 2000, pp 125-129,
ISBN 1-86058-267-2.
Page, T., ''A Knowledge-Based Methodology for Guidelines and Rules in the Design for
Assembly of Printed Circuit Boards (PCBs)'', Advances in Manufacturing Technology XIV,
Proceedings of the 16th National Conference on Manufacturing Research, University of East
London, UK, 2000, pp 131-135, ISBN 1-86058-267-2.
Page, T., ''A Declarative Representation of Component Selection Guidelines and the Rules in the
Design for Assembly of Printed Circuit Boards'', Advances in Manufacturing Technology XIV,
Proceedings of the 16th National Conference on Manufacturing Research, University of East
London, UK, 2000, pp 137-141, ISBN 1-86058-267-2.
Page, T., ''A Review of Information Requirements for Conducting Design for Assembly in
Surface Mount Technology'', Advances in Manufacturing Technology XiV, Proceedings of the
16th National Conference on Manufacturing Research, University of East London, UK, 2000, pp
215-219, ISBN 1-86058-267-2.
Page, T. and Milburn, R., ''Causes of Misregistration in Multi-layer Printed Circuit boards
during Prepreg bonding'', Knowledge driven manufacturing, CIT Press, Cork Ireland, The 20th
International Manufacturing Conference IMC20, Cork Institute of Technology, 2003, pp 274-
279, ISBN 0 9545736 0 9.
Page, T., ''Knowledge-Based Computer-Aided Process Planning Approaches in Electronics
Manufacturing'', Knowledge Driven Manufacturing, CIT Press, Cork Ireland, The 20th
International Manufacturing Conference IMC20, Cork Institute of Technology, 2003, pp 296-
301, ISBN 0 9545736 0 9.
Page, T., Koliza, V., Pearce, D. and Khoudian, P., ''Soft Systems Methodology applied in the
New Product Introduction (NPI) Process'', Knowledge Driven Manufacturing, CIT Press, Cork,
Ireland, The 20th International Manufacturing Conference, IMC20, Cork Institute of
Technology, 2003, pp 575-581, ISBN 0 9545736 0 9.
Page, T., Koliza, V., Pearce, D. and Khoudian, P., ''Formulation of a calculation for identifying
actual and potential costs incurred by delays in the New Product Introduction Process'',
Proceedings of the 19th National Conference on Manufacturing Research, Professional
Engineering Publishing, 19th National Conference on Manufacturing Research, Strathclyde
University, 2003, pp 229-234, ISBN 1 86058 412 8.
Page, T., ''Embodiment of fine-pitch design for manufacturing guidelines and rules in printed
circuit board (PCB) design software'', Proceedings of the 19th National Conference on
Manufacturing Research, Professional Engineering Publishing, 19th National Conference on
Manufacturing Research, Strathclyde University, 2003, pp 259-264, ISBN 1 86058 412 8.
Page, T., ''A case study in the use of internet-based tutorials and a managed learning
environment in support of the teaching and learning of CAD/CAM'', Proceedings of the 19th
National Conference on Manufacturing Research, Professional Engineering Publishing, 19th
National Conference on Manufacturing Research, Strathclyde University, 2003, pp 303-308,
ISBN 1 86058412 8.
Page, T., ''Embodiment of fine-pitch design for manufacturing guidelines and rules in printed
circuit board (PCB) design software'', Advances in Manufacturing Technology XVII,
Professional Engineering Publishing, First International Conference on Manufacturing Research,
Strathclyde University, 2003, pp 259-264, ISBN 1 86058 412 8.
Page, T., ''A case study in the use of internet-based tutorials and a managed learning
environment in support of the teaching and learning of CAD/CAM'', Advances in Manufacturing
Technology XVII, Professional Engineering Publishing, First International Conference on
Manufacturing Research, Strathclyde University, 2003, pp 303-308, ISBN 1 86058 412 8.
Page, T., Koliza, V., Pearce, D. and Khoudian, P., ''Formulation of a calculation for identifying
actual and potential costs caused by delays in the new product introduction process'', Advances
in Manufacturing Technology XVII, Professional Engineering Publishing, First International
Conference on Manufacturing Research, Strathcylde University, 2003, pp 229-234, ISBN 1
86058 412 8.
Baguley, P., Bramall, D., Marpoulos, P. and Page, T., ''The automation of sustainability via re-
use, modularization and fuzzy logic'', Design and manufacture for sustainable development
2004, Bhamra, T. and Hon, B. (eds), Professional Engineering Publishing Ltd, UK,
Loughborough University, 2004, pp 65-74, ISBN 1 86058 470 5.
Page, T. and Lehtonen, M., ''Internet-based Tutorials and a Managed Learning Environment in
Teaching Microcontroller Interfacing'', Proceedings of the TEKA/FATE Symposium on
Technology Education 2004, Kananoja, T. (ed), TEKA/FATE Symposium, Turku, Finland,
2004, pp 201-207, ISBN 951-634-884-8.
Page, T. and Lehtonen, M., ''Internet-based Tutorials and a Managed Learning Environment in
Teaching Microcontroller Interfacing'', Technology Education and Educational Technology and
Training Practices 2004, Kananojo, T. (ed), TEKA/FATE Symposium, Turku, Finland, 2004, pp
313-319, ISSN 1459-6830.
Clegg, B. and Page, T., ''The Commercial-Financial Perspective of the Extended Enterprise
Matrix'', 10th International Conference on Concurrent Enterprising, Escuela Superior de
Ingenieros, Seville, Spain, 2004, Poster Presentation.
Koliza, V., Pearce, D., Khoudian, P., O'Sullivan, J. and Page, T., ''Performance Measurement of
the New Product Introduction'', Proceedings of the 20th National Conference on Manufacturing
Research, Sheffield Hallam University, 2004, pp 294-298.
Koliza, V., Pearce, D., Khoudian, P., O'Sullivan, J. and Page, T., ''Performance Measurement of
the New Product Introduction Process'', Advances in Manufacturing Technology, Proceedings of
the 2nd International Conference on Manufacturing Research, Sheffield Hallam University,
2004, pp 294-298, ISBN 1 84387 088 6.
Baguley, P., Page, T., Koliza, V. and Maropoulos, P., ''Time to Market Prediction Using Type-2
Fuzzy Sets'', Proceedings of the 20th National Conference on Manufacturing Research, Sheffield
Hallam University, 2004, pp 299-304.
Baguley, P., Page, T., Koliza, V. and Maropoulos, P., ''Time to Market Prediction Using Type-2
Fuzzy Sets'', Advances in Manufacturing Technology. Proceedings of the 2nd International
Conference on Manufacturing Research, Sheffield Hallam University, 2004, pp 299-304, ISBN
1 84387 088 6.
Baguley, P., Page, T. and Maropoulos, P., ''Sophisticated Cost Modelling'', Proceedings of the
20th National Conference on Manufacturing Research, Sheffield Hallam University, 2004, pp
305-309.
Baguley, P., Page, T. and Maropoulos, P., ''Sophisticated Cost Modelling'', Advances in
Manufacturing Technology, Proceedings of the 2nd International Conference on Manufacturing
Research, Sheffield Hallam University, 2004, pp 305-309, ISBN 1 84387 088 6.
Page, T., ''An Application of Internet-Based Tutorials and a Managed Learning Environment in
Support of Microcontroller Interfacing'', Proceedings of the 20th National Conference on
Manufacturing Research, Sheffield Hallam University, 2004, pp 459-464.
Page, T., ''An Application of Internet-Based Tutorials and a Managed Learning Environment in
Support of Teaching and Learning in Microcontroller Interfacing'', Advances in Manufacturing
Technology, Proceedings of the 2nd International Conference on Manufacturing Research,
Sheffield Hallam University, 2004, pp 459-464, ISBN 1 84387 088 6.
Page, T., ''An Analysis of Registration Errors in High Density Interconnects Caused During
Bonding of Multi-Layer Printed Circuit Boards (PCBs)'', Proceedings of the 20th National
Conference on Manufacturing Research, Sheffield Hallam University, 2004, pp 67-72.
Page, T., ''An Analysis of Registration Errors in High Density Interconnects Caused during
Bonding of Multi-layer Printed Circuit Boards (PCBs)'', Advances in Manufacturing
Technology, Proceedings of the 2nd International Conference on Manufacturing Research,
Sheffield Hallam University, 2004, pp 67-72, ISBN 1 84387 088 6.
Koliza, V., Pearce, D., Khoudian, P., O'Sullivan, J. and Page, T., ''Qualitative Analysis of the
New Product Introduction (NPI) related Issues'', Proceedings of the 21st International
Manufacturing Conference IMC21, University of Limerick, 2004, pp 27-32, ISBN 1 8746537 7
1.
Page, T. and Baguley, P., ''Prevention of Electromagnetic Interference (EMI) through Design for
Assembly of Printed Circuit Boards'', Proceedings of the 21st International Manufacturing
Conference IMC21, University of Limerick, 2004, pp 321-328, ISBN 1 8746537 7 1.
Page, T., ''Embodiment of Fine-Pitch Design Rules in a PCB Design Application'', Proceedings
of the 21st International Manufacturing Conference IMC21, University of Limerick, 2004, pp
553-558, ISBN 1 8746537 7 1.
Baguley, P., Page, T., Maropoulos, P.G. and Koliza, V., ''Type 2 Fuzzy Sets used in Evaluating
a New Product Introduction Process'', Proceedings of the 21st International Manufacturing
Conference IMC21, University of Limerick, 2004, pp 635-642, ISBN 1 8746537 7 1.
Page, T., Baguley, P. and Schaefer, D., ''Maintaining Electromagnetic Compatibility through
Design for Fabrication & Assembly of Printed Circuit Boards (PCBs)'', ECAD/ECAE 2004,
Proceedings of the lst International Conference on Electrical/Electromechanical Computer
Aided Design & Engineering, Maropoulos, P.G. & Schaefer, D. (eds), ECAD/ECAE 2004,
University of Durham, November 2004, pp 101-105, ISBN 0-953555-3-6.
Page, T., Baguley, P. and Schaefer, D., ''Ensuring Electromagnetic Compliance in Printed
Circuit Boards Through Design for Assembly Guidelines'', ECAD/ECAE 2004, Proceedings of
the lst International Conference on Electrical/Electromechanical Computer-Aided Design &
Engineering, Maropoulos, P.G. & Schaefer, D. (eds), ECAD/ECAE 2004, University of
Durham, November 2004, pp 106-110, ISBN 0-953555-3-6.
Baguley, P., Schaefer, D. and Page, T., ''Costing Issues Regarding Product Variant Design'',
ECAD/ECAE 2004, Proceedings of the lst International Conference on
Electrical/Electromechanical Computer-Aided Design & Engineering, Maropoulos, P.G. &
Schaefer. D. (eds), ECAD/ECAE 2004, University of Durham, November 2004, pp 41-45, ISBN
0-9535558-3-6.
Iskanius, P., Page, T. and Haapasalo, H., ''Moving Toward an Agile Supply Chain - A Case
Study from a Traditional Industry Sector'', ICAM 2005 International Conference on Agile
Manufacturing 2005 Proceedings, International Society of Agile Manufacturing (ISAM), ICAM
2005, Helsinki University of Technology, 2005, pp 179-188.
Iskanius, P. and Page, T., ''Development Road Map towards e-business - A Case Study'',
Proceedings of the 22nd International Manufacturing Conference IMC22, Vickery, J. (ed), 22nd
International Manufacturing Conference, Institute of Technology Tallaght, Ireland, 2005, pp
493-500, ISBN 0-9551218.
Koliza, V., Khoudion, P., Pearce, O., O'Sullivan, J. and Page, T., ''A Sensitivity Analysis on
Organisations with Different Characteristics of New Product Introduction and Time To Market
Variations'', Proceedings of the 22nd International Manufacturing Conference - IMC 22,
Vickery, John (ed), 22nd International Manufacturing Conference IMC22, Tallaght, Ireland,
2005, pp 613-618, ISBN 0-9551218-0-9.
Page, T., ''A Learner Centred Evaluation of Hypermedia-based Learning Resources in Blended
Learning in Microcontroller Product Design'', Proceedings of DATA International Research
Conference 2005, Norman, E.W.L., Spendlove, D. and Grover, P. (eds), Design and Technology
Association, Inspire and Educate, DATA International Research Conference 2005, Sheffield
Hallam University, July 2005, pp 147-151, ISBN 1-898788-75-8.
Page, T., ''A Hypermedia-based Learning Environment in Support of Blended Learning in
Electronic Product Design'', Proceedings of the third International Conference on Engineering
and Product Design Education EPD05, Engineering and Product Design Education 2005, Napier
University, Edinburgh, September 2005, pp 497-502.
Valiusaityte, I., Rajabally, E., and Page, T., ‘Mathematical Means for Assessing Military
Aircraft Performance as Applied to Training Effectiveness’, Proceedings of Simulations
Interoperability Standards Organisation (SISO): Simulation Interoperability Workshop Fall
2008, Paper ref: 08F-SIW-013, (TRAIN Forum), Orlando, Florida, USA, September 2008, pp.
771-781.
Page, T., ''Development of a Database for the Analysis of Non-Linear Materials within a Finite
Element Modelling Package'', Non-Linear Applications in Finite Element Analysis, Institute of
Mechanical Engineers, London, 2001, pp1-5.
Page, T. and Baguley, P., ''Preservation of Electromagnetic Compatibility Through Effective
Design for Manufacturing of Printed Circuit Boards (PCBs)'', October 2004, pp 1-10, Society of
Manufacturing Engineer, Dearborn, MI, USA, Technical Paper: TP04PUB292.
Maropoulos, P.G., Baguley, P., Page, T. and Koliza, V., ''Evaluation and Performance
Measurement of the New Product Development Process'', October 2004, pp 1-10, Society of
Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP04PUB300.
Page, T. and Baguley, P., ''Sustainable Design and Manufacturing Implications Through Re-Use,
Modularization and Fuzzy Logic'', October 2004, pp 1-12, Society of Manufacturing Engineers,
Dearborn, MI, USA, Technical Paper: TP04PUB299.
Page, T., ''Design for Assembly Constraints in Surface Mount Technology'', October 2004, pp 1-
7, Society of Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP04PUB295.
Page, T., ''Knowledge-Based Support for the Provision of Design for Assembly Guidelines and
Rules in Electronics Manufacturing'', October 2004, pp 1-7, Society of Manufacturing
Engineers, Dearborn, MI, USA, Technical Paper: TP04PUB296.
Page, T., ''Development and Integration of a Non-Linear Materials Database for Finite Element
Analysis (FEA)'', October 2004, pp 1-7, Society of Manufacturing Engineers, Dearborn, MI,
USA, Technical Paper: TP04PUB297.
Page, T., ''Representation of Component Selection Rules for Design for Assembly of Printed
Circuit Boards'', October 2004, pp 1-7, Society of Manufacturing Engineers, Dearborn, MI,
USA, Technical Paper: TP04PUB298.
Baguley, P., Maropoulos, P., Page, T. and Koliza, V., ''The Reduction of Product Development
Lead-Time Using Type-2 Fuzzy Sets'', October 2004, pp 1-8, Society of Manufacturing
Engineers, Dearborn, MI, USA, Technical Paper: TP04PPUB304.
Page, T., ''A Review of Knowledge-Based Computer-Aided Process Planning Approaches in
Electronics Manufacturing'', October 2004, pp 1-8, Society of Manufacturing Engineers,
Dearborn, MI, USA, Technical Paper: TP04PUB293.
Baguley, P., Maropoulos, P. and Page, T., ''Cost Engineering for New Product Design and
Innovation'', October 2004, pp 1-8, Society of Manufacturing Engineers, Dearborn, MI, USA,
Technical Paper: TP04PUB302.
Koliza, V., Page, T. and Pearce, D., ''Classification of Actual & Potential Cost Formulae Caused
by Delays in the New Product Development (NPD) Process'', October 2004, pp 1-8, Society of
Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP04PUB303.
Page, T., ''Thick Film Microelectronic Packaging Technology'', October 2004, pp 1-8, Society of
Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP04PUB341.
Page, T., ''A Demonstration of the Implementation of Fine Pitch Design Rules in a PCB Design
Application'', October 2004, pp 1-8, Society of Manufacturing Engineers, Dearborn, MI,USA,
Technical Paper: TP04PUB294.
Pearce, D., Khoudian, P., Page, T. and Koliza, V., ''Application of the Soft Systems
Methodology in the New Product Development (NPD) Process'', October 2004, pp 1-9, Society
of Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP04PUB301.
Haapasalo, H., Iskanius, P. and Page, T., ''Order Delivery Process in Manufacturing Network
Deploying Manufacturing Philosophies in the Steel Product Industry'', November 2004, pp 1-10,
Society of Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP04PUB319.
Haapasalo, H., Iskanius, P. and Page, T., ''The Development of a Design and Manufacturing
Collaboration Agreement'', November 2004, pp 1-12, Society of Manufacturing Engineers,
Dearborn, MI, USA, Technical Paper: TP04PUB322.
Alaruikka, A.M., Iskanius, P. and Page, T., ''Data Translations in Information Flow in a Finnish
Steel Product Industry Network'', November 2004, pp 1-15, Society of Manufacturing
Engineers, Dearborn, MI, USA, Technical Paper: TP04PUB318.
Iskanius, P., Page, T. and Pikka, V., ''The Influence that the Focal Company has over its Supply
Network - A Case Study in Steel Product Design & Manufacture'', November 2004, pp 1-16,
Society of Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP04PUB321.
Iskanius, P., Uusipaavalniemi, S. and Page, T., ''Steel Product Design & Manufacturing - A Case
Study in Agility'', November 2004, pp 1-18, Society of Manufacturing Engineers, Dearborn, MI,
USA, Technical Paper: TP04PUB316.
Iskanius, P., Uusipaavalniemi, S. and Page, T., ''The Development of a Collaborative Venture in
an Agile Supply Chain - A Case Study in Steel Product Design'', November 2004, pp 1-20,
Society of Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP04 PUB317.
Budan, A,, Arunachalam, S. and Page, T., ''The Use of a Simulated Annealing Algorithm for
Design Optimization of Steel and Composite Leaf Springs'', November 2004, pp 1-28, Society
of Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP04PUB313.
Clegg, B. and Page, T., ''The Use of the Extended Enterprise Matrix to Derive Costs in Product
Development'', November 2004, pp 1-6, Society of Manufacturing Engineers, Dearborn, MI,
USA, Technical Paper: TP04PUB339.
Arunachalam, S., Sankaranarayanaswamy, K., Page, T. and Dhanalakshmi, V., ''Optimal Part
Family Formation Using a Realistic Fuzzy Set Theoretic Approach in Cellular Manufacturing'',
November 2004, pp 1-7, Society of Manufacturing Engineers, Dearborn, MI, USA, Technical
Paper: TP03PUB314.
Sankaranarayanaswamy, K., Arunachalam, S., Page, T. and Dhanalakshmi, V., ''Automatic
Evaluation of alternate Tool Access Directions (TADs) using STEP for Minimal Set-up
Changes'', November 2004, pp 1-8, Society of Manufacturing Engineers, Dearborn, MI, USA,
Technical Paper: TP04PUB315.
Koliza, V., Khoudian, P., Pearce, D., Page, T. and O'Sullivan, J., ''Monitoring of Performance in
the New Product Development (NPD) Process: Qualitative Analysis of Benchmarks'', November
2004, pp 1-8, Society of Manufacturing Engineers, Dearborn, MI, USA, Technical Paper:
TP04PUB320.
Page, T., ''Supply Chain Management - A Review of Integrated Design & Manufacture'',
November 2004, pp 1-9, Society of Manufacturing Engineers, Dearborn, MI, USA, Technical
Paper: TP04PUB324.
Page, T., ''A Case Study in the Implementation of an Enterprise Resource Planning (ERP)
System'', November 2004, pp 1-9, Society of Manufacturing Engineers, Dearborn, MI, USA,
Technical Paper: TP04PUB325.
Page, T., ''A Discussion of Quality Management Systems Implementation - A European
Context'', November 2004, pp 1-9, Society of Manufacturing Engineers, Dearborn, MI, USA,
Technical Paper: TP04PUB326.
Page, T., ''Modern Photoplotting Formats'', November 2004, pp 1-9, Society of Manufacturing
Engineers, Dearborn, MI, USA, Technical Paper: TP04PUB340.
Page, T., ''A Specification for Design for Assembly Support in Surface Mount Technology
Utilizing a Knowledge-Based System'', December 2004, pp 1-25, Society of Manufacturing
Engineers, Dearborn, MI, USA, Technical Paper: TP04PUB359.
Page, T., ''The Design of a Manifold Tract Component Through the Analysis of Solid-Fluid
Interaction Using F.E.A.'', December 2004, pp 1-29, Society of Manufacturing Engineers,
Dearborn, MI, USA, Technical Paper: TP04PUB360.
Page, T., ''A Description of the Design, Fabrication and Assembly of Printed Circuit Boards
(PCBs) Using Surface Mount Technology (SMT) & Plated Through Hole (PTH) Technology'',
December 2004, pp 1-45, Society of Manufacturing Engineers, Dearborn, MI, USA, Technical
Paper: TP04PUB357.
Page, T., ''Design Guidelines and Rules for Effective Yield in Manufacturing & Assembly of
Printed Circuit Boards Utilizing Surface Mount Technology'', December 2004, pp 1-45, Society
of Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP04PUB358.
Page, T., ''An Appraisal of Database Technologies in Support of Manufacturing Operation
Decision Making'', 2005, pp 1-10, Society of Manufacturing Engineers, Dearborn, MI, USA,
Technical Paper TP05PUB155.
Mohanasumdaram, K., Arunachalam, S. and Page, T., ''An Application of Performance
Measurement in an Assembly Job Shop Environment - A Case Study'', 2005, pp 1-12, Society of
Manufacturing Engineers (SME), Dearborn, MI, USA, Technical Paper TP05PUB33.
Arunachalam, S. and Page, T., ''Criteria for Successful Implementation of Decision Support
Systems'', February 2005, pp 1-10, Socieity of Manufacturing Engineers, Dearborn, MI, USA,
Technical Paper: TP05PUB19.
Page, T., ''Implementation Issues in Data Warehousing'', February 2005, pp 1-12, Society of
Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP05PUB14.
Page, T., ''A Classification of Data Mining Techniques'', February 2005, pp 1-12, Society of
Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP05PUB16.
Arunachalam, S. and Page, T., ''Engineering Optimization Using Genetic Algorithms'', February
2005, pp 1-12, Society of Manufacturing Engineers, Dearborn, MI, USA, Technical Paper:
TP05PUB18.
Page, T., ''The Use of Topological Optimization Within a Finite Element Package for the Design
of a Structural Component'', February 2005, pp 1-13, Society of Manufacturing Engineers,
Dearborn, MI, USA, Technical Paper: TP05PUB9.
Page, T., ''Design of a Bracket Fixture for Vibrational Analysis of a Fluid-Filled Manifold Tract
Utilizing Modal Analysis in FEA'', February 2005, pp 1-14, Society of Manufacturing
Engineers, Dearborn, MI, USA, Technical Paper: TP05PUB8.
Senthil, P., Arunachalam, S. and Page, T., ''A Novel Algorithm for Parallel Machine
Scheduling'', February 2005, pp 1-17, Society of Manufacturing Engineers, Dearborn, MI, USA,
Technical Paper: TP05PUB12.
Page, T., ''Engineering Design Methods - A Review and Classification of Sources'', February
2005, pp 1-24, Society of Manufacturing Engineers, Dearborn, MI, USA, Technical Paper:
TP05PUB13.
Page, T., ''A Demonstration of the Decision Support System Utilized in Support in the Design
for Assembly of Printed Circuit Boards'', February 2005, pp 1-27, Society of Manufacturing
Engineers, Dearborn, MI, USA, Technical Paper: TP05PUB6.
Sundararaj, G., Arunachalam, S. and Page, T., ''A Review of Experimental Techniques Applied
in Cryogenic Treatment of Cutting Tols and Metals'', February 2005, pp 1-35, Society of
Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP05PUB11.
Page, T., ''A Representation of Design Guidelines and Rules in Electronic Design for
Manufacturing Utilizing Knowledge Representation Schema'', February 2005, pp 1-57, Society
of Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP05PUB5.
Arunachalam, S., Loke, S. and Page, T., ''Solving the Machine Shop Scheduling Problem
Through the Integration of a Knowledge-based System and a Gantt Chart Scheduling
Application'', February 2005, pp 1-6, Society of Manufacturing Engineers, Dearborn, MI, USA,
Technical Paper: TP05PUB10.
Page, T., ''An Introduction to Multi-Agent Systems'', February 2005, pp 1-8, Society of
Manufacturing Engineers, Dearborn, MI, USA, Technical Paper: TP05PUB17.
Miller, J. and Page, T., ''Optimization Formulae for Multi-Station Assembly Systems'', February
2005, pp 1-9, Society of Manufacturing Engineers, Dearborn, MI, USA, Technical Paper:
TP05PUB15.
Brown, C.C., MacNair Smith, H., Miller, J. and Page, T., ''The Design and Development of a
Robotic Assembly System for Consumer Products Assisted by Voice Control'', March 2005, pp
1-8, Society of Manufacturing Engineers (SME), Dearborn, MI, USA, Technical Paper
TP05PUB32.
Page, T., ''Conversion of Analogue Signals to Digital Signals for Input to Microcontroller
Devices'', June 2005, pp 1-10, Socieity of Manufacturing Engineers, Dearborn, MI, USA,
Technical Paper TP05PUB91.
Sankaranarayanasamy, K., Arunachalam, S., Page, T. and Dhanalakshmi, V., ''A Novel
Approach to Part Family Formation in Cellular Manufacturing Using Fuzzy Analysis in
CAD/CAM'', June 2005, pp 1-12, Society of Manufacturing Engineers, Dearborn, MI, USA,
Technical Paper TP05PUB67.
Page, T., ''Approaches to the Design of Digital Systems Using Very Large Scale Integration
(VLSI) CAD'', June 2005, pp 1-16, Society of Manufacturing Engineers, Dearborn, MI, USA,
Technical Paper TP05PUB90.
Page, T., ''Activity-Based Costing (ABC) - A Guide to Implementation and Use for
Manufacturing Engineering Operations'', June 2005, pp 1-7, Society of Manufacturing
Engineers, Dearborn, MI, USA, Technical Paper TP05PUB68.
Page, T., ''The Modeling of Three-Dimensional Assemblies in CAD'', June 2005, pp 1-7, Society
of Manufacturing Engineers, Dearborn, MI, USA, Technical Paper TP05PUB70.
Page, T., ''Decision Making for Capacity Planning'', June 2005, pp 1-8, Society of
Manufacturing Engineers, Dearborn, MI, USA, Technical Paper TP05PUB92.
Page, T., ''A Methodology for the Rationalization of Investment in Advanced Manufacturing
Technology'', June 2005, pp 1-9, Society of Manufacturing Engineers, Dearborn, MI, USA,
Technical Paper TP05PUB66.
Page, T., ''The Formulation of a Product Design Specification (PDS) with Emphasis on Design
for Assembly'', August 2005, pp 1-10, Society of Manufacturing Engineers, Dearborn, MI. USA,
Technical Paper TP05PUB173.
Page, T., ''Enabling Technologies for Effective Management of Product Development in the 21st
Century'', August 2005, pp 1-19, Society of Manufacturing Engineers, Dearborn, MI, USA,
Technical Paper TP05PUB132.
Page, T., ''Material Removal Through Drilling & Hole Making Processes'', August 2005, pp 1-8,
Society of Manufacturing Engineers, (SME), Dearborn, MI, USA, Technical Paper
TP05PUB193.
Page, T., ''The Modelling of Curve Entities in 3D CAD'', August 2005, pp 1-8, Society of
Manufacturing Engineers, Dearborn, MI, USA, Technical Paper TP05PUB154.
Page, T., ''Graphical Aides and Tools for the Implementation of Continuous Improvement'',
August 2005, pp 1-8, Society of Manufacturing Engineers, Dearborn, MI, USA, Technical Paper
TP05PUB156.
Page, T., ''Design and Analysis Software Applications for Engineering Design and
Manufacture'', August 2005, pp 1-9, Society of Manufacturing Engineers (SME), Dearborn, MI,
USA, Technical Paper TP05PUB194.
Page, T., ''The Use of Manufacturing Information Systems in Support of E-Commerce
Activities'', October 2005, pp 1-10, Society of Manufacturing Engineers (SME), Dearborn, MI,
USA.
Page, T., ''An Account of the Use of DFA/DFM Tools in Modern Manufacturing Enterprises'',
October 2005, pp 1-10, Society of Manufacturing Engineers (SME), Dearborn, MI, USA,
Technical Paper (TP05PUB214).
Page, T., ''Where is the Future for Networking and Data Communication Technologies'', October
2005, pp 1-17, Society of Manufacturing Engineers (SME), Dearborn, MI, USA, Technical
Paper (TP05PUB220).
Page, T., ''A Strategy for Globalized Manufacturing Operations'', October 2005, pp 1-6, Society
of Manufacturing Engineers (SME), Dearborn, MI, USA, Technical Paper (TP05PUB215).
Page, T., ''Strategies for the Location of Multi-Plant Networks'', October 2005, pp 1-6, Society
of Manufacturing Engineers (SME), Dearborn, MI, USA, Technical Paper (TP05PUB217).
Page, T., ''To provide for Process Variability Through the Specification of Tolerances in Modern
3D CAD'', October 2005, pp 1-7, Society of Manufacturing Engineers (SME), Dearborn, MI,
USA, Technical Paper (TP05PUB212).
Page, T., ''A Consideration of Manufacturing Issues in the Strategic Management of
Operations'', October 2005, pp 1-8, Society of Manufacturing Engineers (SME), Dearborn, MI,
USA.
Page, T., ''Technologies for Automation in Manufacturing'', October 2005, pp 1-8, Society of
Manufacturing Engineers (SME), Dearborn, MI, USA, Technical Paper (TP05PUB218).
Page, T., ''Embedded Microprocessor Product Design'', October 2005, pp 1-9, Society of
Manufacturing Engineers (SME), Dearborn, MI, USA, Technical Paper (TP05PUB219).
Page, T., ''Combinational Circuit Design Using Discrete Bistable Devices'', December 2005, pp
1-6, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper:
TP05PUB254.
Pearce, D., O'Sullivan, J,, Khoudian, P., Page, T. and Koliza, V., ''An Application of Sensitivity
Analysis on New Product Development Projects with Time to Market Variations'', December
2005, pp 1-7, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper:
TP05PUB248.
Pearce, D., O'Sullivan, J., Khoudian, P., Page, T. and Koliza, V., ''New Product Introduction and
Time to Market with Emphasis on Business Profitability - A Survey'', December 2005, pp 1-7,
Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper:
TP05PUB249.
Page, T., ''Implementation Issues in Quality Systems'', 2006, pp1-7, Society of Manufacturing
Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP06PUB120).
Page, T., ''The Abstraction of Manufacturing Features from Surface Models in CAD'', March
2006, pp 1-11, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical
Paper TP06PUB6.
Page, T., ''Geometric Modelling and Representation of Curve and Surface Operations in 3D
CAD'', March 2006, pp 1-12, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA,
Technical Paper TP06PUB13.
Page, T., ''A Collaborative Design Methodology for the Design of Embedded Control Systems'',
March 2006, pp 1-12, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA,
Technical Paper TP06PUB14.
Page, T., ''A Direct Translation Technique for Transferring Data Between Electronic and
Mechanical CAD Systems'', March 2006, pp 1-12, Society of Manufacturing Engineers (SME),
Dearborn, Mi, USA, Technical Paper TP06PUB5.
Page, T., ''Algorithms for Collision Avoidance in Machine Tool Path Verification'', March 2006,
pp 1-13, Society of Manufacturing Engineers SME, Dearborn, Mi, USA, Technical Paper
TP06PUB9.
Page, T., ''Traditional Industry Competition - Development of an Agile Supply Chain'', March
2006, pp 1-14, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical
Paper TP06PUB7.
Page, T., ''The Application of Geometric Tree Structures in Constructing and Modifying 3-D
Models in CAD'', March 2006, pp 1-15, Society of Manufacturing Engineers (SME), Dearborn,
Mi, USA, Technical Paper TP06PUB4.
Page, T., ''Representation Schemes Used in Geometric Modelling of Solids and Surfaces in
CAD'', March 2006, pp 1-20, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA,
Technical Paper TP06PUB17.
Page, T., ''Pragmatic Considerations in Design for Production'', March 2006, pp 1-7, Society of
Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper TP06PUB12.
Page, T., ''A Group Technology Approach to Computer-Aided Process Planning Systems'',
March 2006, pp 1-7, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA,
Technical Paper TP06PUB8.
Page, T., ''Approaches to Focussed Manufacturing'', March 2006, pp 1-8, Society of
Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper TP06PUB10.
Page, T., ''Enabling Technologies for Effective Computer-Aided Manufacturing'', March 2006,
pp 1-8, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper
TP06PUB11.
Page, T., ''An Overview of Production Control Systems for Kanban Operation'', March 2006, pp
1-9, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper
TP06PUB15.
Page, T., ''Key Features of Lean Production'', March 2006, pp 1-9, Society of Manufacturing
Engineers (SME), Dearborn, Mi, USA, Technical Paper TP06PUB16.
Page, T., ''Mechatronic Systems Used in Control'', June 2006, pp 1-10, Society of Manufacturing
Engineers (SME), Dearborn, Mi, USA, Technical Paper TP06PUB94.
Page, T., ''Introduction to Bezier and NURBS Representation Schemes in Surface Modelling'',
October 2006, pp1-27, Society of Manufacturing Engineers (SME) Dearborn,Mi, USA.,
Technical Paper (TP06PUB134).
Baloglu, A., Arunachalam, S. and Page, T., ''Re-Engineering the Supply Chain in Internet Age:
A Case Study ABB Turkey'', October 2006, pp1-27, Society of Manufacturing Engineers
(SME), Dearborn, Mi, USA., Technical Paper (TP06PUB119).
Page, T., ''Algorithms Used for Routing and Placement in VLSI'', November 2006, pp 1-10,
Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper
(TP06PUB153).
Page, T., ''Linear Programming Techniques for Floorplanning in VLSI'', November 2006, pp 1-
12, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper
(TP06PUB155).
Page, T., ''Programmable Techniques for Transmission Line Optimization in VLSI'', November
2006, pp 1-5, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper
(TP06PUB154).
Page, T., ''Non-Slicing Floorplan Representation Used in Linear Programming in VLSI'',
November 2006, pp 1-6, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA,
Technical Paper (TP06PUB156).
Page, T., ''A Justification for Relevance in Performance Measurement Criteria'', November
2006, pp 1-7, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper
(TP06PUB152).
Ichimura, M., Arunachalam, S. and Page, T., ''Critical Training Requirements for Lean
Manufacturing'', March 2007, pp 1-16, Society of Manufacturing Engineers (SME), Dearborn,
Mi, USA, Technical Paper (TP07PUB15).
Kannan, A.R., Pandey, K., Narayanasamy, R., Arunachalam, S., Shanmugan, S. and Page, T.,
''The Performance of Deformation of Fe-0.8%C-1.0%Si-0.8%Cu Sintered Powder Metallurgy
Specimens Throughout Preform Forging '', March 2007, pp 1-21, Society of Manufacturing
Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB16).
Iskanius, P. and Page, T., ''A Case Study in E-Business and Supply Chain Integration'', July
2007, pp 1-9, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper
(TP07PUB74).
Page, T., ''Computer Graphics in CAD/CAM'', July 2007, pp 1-7, Society of Manufacturing
Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB77).
Page, T., ''Design Process: A Case Study in Product Improvement'', July 2007, pp 1-10, Society
of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB78).
Page, T., ''Effective Computer-Aided Manufacturing'', July 2007, pp 1-7, Society of
Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB81).
Page, T., ''Production Levelling and Scheduling'', July 2007, pp 1-8, Society of Manufacturing
Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB88).
Page, T. ''Assembly modelling in Computer-Aided Engineering'', July 2007, pp 1-6, Society of
Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB96).
Page, T. ''Activity-Based Costing (ABC) in Operations management'', July 2007, pp 1-6, Society
of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB97).
Page, T. ''Components of Lean Production'', July 2007, pp 1-8, Society of Manufacturing
Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB98).
Page, T. ''Analogue to Digital Conversion in Embedded Devices'', July 2007, pp 1-9, Society of
Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB99).
Arreymbi, J., Arunachalam, S. and Page, T., ''Evaluating the Effects of Radio Frequency
identification (RFID) Applications in Manufacturing and Business'', July 2007, pp 1-12, Society
of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB100).
Page, T. ''Concurrent Engineering in the Era of Mass Customization'', July 2007, pp 1-18,
Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper
(TP07PUB103).
Page, T. ''VLSI Digital Design Techniques'', July 2007, pp 1-15, Society of Manufacturing
Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB104).
Page, T., ''Strategic Level Decision-Making in Capacity Planning'', July 2007, pp 1-7, Society of
Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB107).
Page, T., ''The Role of Manufacturing in E-Commerce'', December 2007, pp 1-10, Society of
Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB205).
Page, T., ''Applications of Design and Analysis'', December 2007, pp 1-9, Society of
Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB206).
Muhos, M., Iskanius, P. and Page, T., ''Agility in the Finnish Metal Industry'', December 2007,
pp 1-11, Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper
(TP07PUB208).
Helaakoski, H., Peltomaa, I., Iskanius, P. and Page, T., ''A Roadmap towards E-Commerce in
the Steel Product Industry'', December 2007, pp 1-10, Society of Manufacturing Engineers
(SME), Dearborn, Mi, USA, Technical Paper (TP07PUB209).
Helaakoski, H., Iskanius, P. and Page, T., ''A Computer-Supported Collaborative Tool for
Continuous Improvement'', December 2007, pp 1-14, Society of Manufacturing Engineers
(SME), Dearborn, Mi, USA, Technical Paper (TP07PUB210).
Page, T., ''Performance Measurement in the Product Design Process'', December 2007, pp 1-11,
Society of Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper
(TP07PUB211).
Page, T., ''Tolerance Assignment in 3D-CAD'', December 2007, pp 1-7, Society of
Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB212).
Page, T., ''Quality Measures in Product Design'', December 2007, pp 1-11, Society of
Manufacturing Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB213).
Helaakoski, H., Peltomaa, I., Kipina, J., Iskanius, P. and Page, T., ''A Business Model in Support
of Agility in the Steel Industry Sector'', December 2007, pp 1-8, Society of Manufacturing
Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB214).
Page, T., ''Detailed Routing Design Rules'', December 2007, pp 1-13, Society of Manufacturing
Engineers (SME), Dearborn, Mi, USA, Technical Paper (TP07PUB220).
Page, T (2015) Privacy Issues Surrounding Wearable Technology, Vol.4, No. 3, pp.1-15,
imanager's Journal on Information Technology.
Page, T (2015) An Approach to the Management of the Sustainable Issues in Mobile Phone
Design and Manufacturing, pp.12-23, i-manager's Journal on Management Vol. 10, No. 2.
Page, T (2015) Barriers to the Adoption of Wearable Technology, i-manager’s Journal on
Information Technology, Vol. 4, No. 3, June – August 2015.
Page, T (2015) Technological Diffusion of Near Field Communication, i-manager’s Journal on
Mobile Applications & Technologies, Vol. 1, No. 3, pp.1-14, i-manager publications.
Page, T (2015) Smartphone Applications–A Comparative Study Between Older and Younger
Users, i-manager’s Journal on Mobile Applications & Technologies, Vol. 1, No. 4, November
2014 - January 2015, i-manager publications.
Page, T (2015) A Forecast of the Adoption of Wearable Technology, International Journal of
Technology Diffusion (IJTD), 6(2), pp.12-29, ISSN: 1947-9301. DOI:
10.4018/IJTD.2015040102.
Page, T (Accepted for publication) A Study into the Use of Tolerance Analysis in the
Mechanical Design of Medical Devices, International Journal of Design Engineering.
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