Designing Bipolar Transistor Radio Frequency Integrated Circuits (Artech House Microwave Library)

Designing Bipolar Transistor RadioFrequency Integrated Circuits

For a listing of recent titles in the Artech HouseMicrowave Library, turn to the back of this book.

Designing Bipolar Transistor RadioFrequency Integrated Circuits

Allen A. Sweet

a r te c h h ouse . co m

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British Library Cataloguing in Publication DataA catalogue record of this book is available from the British Library.

ISBN 13: 978-1-59693-128-2ISBN 10: 1-59693-128-0

Cover design by Igor Valdman

© 2008 ARTECH HOUSE, INC.685 Canton StreetNorwood, MA 02062

All rights reserved. Printed and bound in the United States of America. No part of this bookmay be reproduced or utilized in any form or by any means, electronic or mechanical, includ-ing photocopying, recording, or by any information storage and retrieval system, withoutpermission in writing from the publisher.

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10 9 8 7 6 5 4 3 2 1

FUNDAMENTAL PHYSICAL CONSTANTS

1. Speed of light in a vacuum: c=3x1010 cm/s2. Permittivity of a vacuum: ε0=8.89x10–14 F/cm3. Permeability of a vacuum: µ0=1260 nH/meter4. Planck’s constant: h=6.63x10–34 J-seconds5. Boltzmann’s constant: k=1.38x10–23 J/degrees Kelvin6. Charge of an electron: q=1.6x10–19 C7. Rest mass of an electron: me=9.11x10–31 Kg8. Thermal voltage: VT=kT/q=0.0259 volts at T=300 degrees Kelvin9. Bandgap energy of Silicon= 1.12 eV10. Bandgap energy of GaAs = 1.42 eV11. Dielectric constant of Silicon: 11.712. Dielectric constant of GaAs: 12.5

IMPORTANT UNIT CONVERSIONS

1. Angstrom (Å): 1Å=1x10–8 cm2. Nanometer (nm): 1 nm =1x10–7 cm3. Micron (µm): 1 µm=1x10–4 cm4. Electron-Volt (eV): 1 eV=1.6x10–19 J

Contents

Acknowledgments ix

CHAPTER 1Introduction 1

References 11

CHAPTER 2Applications 13

2.1 Cellular/PCS Handsets 132.2 Cellular/PCS Infrastructure 152.3 WLANs 162.4 Bluetooth 172.5 UWB 182.6 WiMax 192.7 Digital TV and Set-Top Boxes 202.8 Cognitive Radio 202.9 Spectrum Allocation in the United States (All Frequencies2.9 in Megahertz) 212.10 Physical Layer Standards 22

References 24

CHAPTER 3RFIC Architectures 25

3.1 I/Q Receivers 253.2 I/Q Modulators 303.3 Nonzero IF Receivers 323.4 Zero IF Receivers 373.5 Differential versus Single-Ended Topologies 41

References 41

CHAPTER 4InGaP/GaAs HBT Fabrication Technology 43

4.1 Transistor Structures 434.2 Device Models 454.3 Passive Structures, Their Electrical Models, and Layout Design Rules 48

4.3.1 Microstrip Lines 534.3.2 TFR Resistors 55

vii

4.3.3 M1-to-M2 Vias 574.3.4 MIM Capacitors 574.3.5 Substrate Vias 584.3.6 Bonding Pads 604.3.7 Crossover Capacitances 614.3.8 Spiral Inductors 624.3.9 Transistor Dummy Cells 644.3.10 Significant Layout Parasitic Elements 654.3.11 Simple Layout Example 65

4.4 Maximum Electrical Ratings 674.5 CAD Layout Tools 70

References 70

CHAPTER 5SiGe HBT Fabrication Technology 71

5.1 SiGe HBT Transistor Structures 715.2 Transistor Device Models 795.3 Passive Device Structures and Models 815.4 Design Rules 865.5 CAD Layout 86

References 87

CHAPTER 6Passive Circuit Design 89

6.1 Low-Pass Filters 896.2 High-Pass Filters 936.3 Band-Pass Filters 936.4 Differential Filters 956.5 Technology and Substrates 996.6 Splitters/Dividers 996.7 Phase Shifters and Baluns 102

References 104

CHAPTER 7Amplifier Design Basics 105

7.1 Matching Techniques 1057.2 Gain Compensation 1067.3 Fano’s Limit 1067.4 Stability 1077.5 Noise Match 1097.6 Differential Amplifiers 1097.7 Cascode Amplifiers 111

References 113

CHAPTER 8Low-Noise Amplifier Design 115

8.1 Noise Figure Concepts 115

viii Contents

8.2 Noise Temperature 1168.3 Front-end Attenuation and LNAs 1178.4 Multistage Noise Figure Contributions 1178.5 Circuit Topologies for Low Noise 1188.6 Design Example 1: Single-Ended PCS LNA 1268.7 Design Example 2: Three-Transistor Hybrid Darlington8.7 Differential LNA Using SiGe Technology 127

References 132

CHAPTER 9Power Amplifier Design 133

9.1 Loadline Concepts 1349.2 Maximum Power and Efficiency 1369.3 Class AB Power Amplifiers 1399.4 Definitions of Nonlinear Performance Metrics 1419.5 Adjacent Channel Power Ratio 1459.6 Error Vector Magnitude 1469.7 Circuit Topologies for PAs 1479.8 Matching Circuit Options 1499.9 Stability 1509.10 Bias Circuits 1509.11 Design Example 3: Wideband Gain Block Darlington Amplifier 1549.12 Design Example 4: Feedback Power Amplifier Design 164

References 171

CHAPTER 10Designing Multistage Amplifiers 173

10.1 Multistage LNAs 17310.2 Multistage Power Amplifiers 17510.3 Gain and Power Allocations 17710.4 Active Device Sizing 17710.5 Design Example 5: A Differential PCS PA 181

References 194

CHAPTER 11Mixer/Modulator Design 195

11.1 Mixer Basics 19511.2 Diode Mixers 19711.3 Single-Balanced Active Multiplying Mixers 20011.4 Fully Balanced Active Multiplying Mixers (Gilbert cell) 20511.5 I/Q Mixers 21711.6 I/Q Modulators 21911.7 Design Example 6: Cellular/PCS Downconverting Mixer RFIC 221

References 230

CHAPTER 12Frequency Multiplier Design 231

Contents ix

12.1 Frequency Doublers 23112.2 Frequency Triplers 23312.3 Frequency Translators 235

References 239

CHAPTER 13Voltage-Controlled Oscillator Design 241

13.1 Varactor Diode Basics 24213.2 Negative-Resistance Concepts 24813.3 Types of Resonators 25213.4 Feedback Circuit Topologies for Producing Negative Resistance 252

13.4.1 Negative-Resistance Oscillator Circuits 25213.4.2 The Colpitts Oscillator Circuit 258

13.5 Frequency-Temperature Stability 26113.6 Phase Noise 26313.7 Quadrature Phase-Shifting Networks 26613.8 Ring Oscillators 26713.9 Design Example 7: 802.11a (Wi-Fi A) Differential VCO 27213.10 Figure of Merit 27813.11 Electronic Tuning and a Differential VCO Topology 279

References 281

CHAPTER 14Layout Design Strategies 283

14.1 Minimum Area 28314.2 “On-Chip” versus “Off-Chip” Component Decisions 28314.3 Minimizing Parasitics 28414.4 Testability 28514.5 Types of CAD Systems 28614.6 Foundry Comparison 28714.7 Reticle Assembly 289

CHAPTER 15RFIC Economics 293

15.1 Levels of Integration 29315.2 Single-Ended versus Differential Topologies 29415.3 Process Technology Choices 29515.4 Area versus Performance Trade-offs 29615.5 Electrical Yield 29715.6 Prototype Costs 29815.7 Production Costs 298

Acronyms 301

About the Author 305

Index 307

x Contents

Acknowledgments

I wish to acknowledge all of my ELEN 351, ELEN 354, and ELEM359 graduatestudents at Santa Clara University. Your probing questions, your well-executedclass projects, and your sense of excitement about the material has helped megreatly to clarify many of the design concepts that are discussed in this book. In thisregard, my special thanks go to Amer Droubi and Calvin Chien for contributingexcellent design material, based on their class projects, to this book. I wish all of youmuch success in your design careers. I would also like to thank my faithful teachingassistant Yiching Chen, who has added so much to these classes.

I am deeply indebted to Professor Shoba Krishnan and Professor SamihaMourad of the Electrical Engineering Department of Santa Clara University, formaking possible the creation of a sequence of RFIC graduate design classes at SantaClara University. It is out of these classes that this book has grown.

To Barbara Lovenvirth of Artech House Publishing, goes my heart felt thanksfor your constant encouragement and support (especially when I needed it the most)during the creation process of this book.

My special thanks to Agilent Corporation for making their ADS simulation toolset available to the students and facility of Santa Clara University.

I wish to give my special thanks to Ron Parrott and his staff at Vida ProductsInc., for supplying design material for this book, and making time available for ourmany interesting discussion about the operation of Vida Product’s YIG tuned ringoscillators.

Many thanks to Taka Shinomiya with whom I have enjoyed many lively discus-sions on power amplifer design.

Finally, I want most especially to thank my wife Fran Sweet, whose patienceand support during our many discussions about the book’s preparation; for herword processing talents and editing skills, and for her “advanced word smithing”magic acts. Everything that you have done on behalf of the book has helped in somany ways to bring us to this successful conclusion of our 18-month book-writingproject. With all my love I thanks you Fran for being my faithful and constant part-ner and companion in this endeavor.

Lastly, I wish to thank my father, Norman A Sweet, for giving me a crystal radiokit as a present on my 10th Christmas. It was this crystal radio that started me on alife long odyssey of discovery into the joys and wonder of radio electronics; whichlives in this book and continues on.

xi

C H A P T E R 1

Introduction

Over the past three decades, radio frequency (RF) and microwave circuits havecome through a period of rapid evolution and growth. Until the early 1960s, mostRF and microwave circuits made use of vacuum tubes such as “lighthouse” tubes,klystrons, magnetrons, backward wave oscillators (BWOs), and traveling-wavetubes (TWTs) [1]. By the mid-1960s, all this was beginning to change as even moredramatic changes were rapidly approaching on the horizon in the form of newsolid-state devices capable of working at RF and microwave frequency ranges. Thefirst of these new technologies to present itself was the silicon (Si) bipolar transistor,which had been scaled to operate up to a frequency of about 1 GHz. And that wasonly the beginning of a wave of development during which time such uniquesolid-state devices as Gunn diodes, Impatt diodes, PIN diodes, and varactor diodesbecame available [2]. These two-terminal solid-state devices had the ability to pushthe upper frequency limit of solid-state electronics from under 1 GHz to well over10 GHz. The rush was on. All eyes were watching to see whose efforts would deliverthe next highest operating frequency, the highest power output, the lowest noise,and the best temperature stability. As the Vietnam War came to an end, this processaccelerated even more because of the availability of federal research money.Because much of the basic RF and microwave research was funded by the federalgovernment, a sharp focus was placed on military applications. RF and microwavetechnology had become a very important element in the cold war strategy of thetime.

Since then, the RF and microwave field has evolved over four distinct periods.Figure 1.1 provides a map of the way these developing technologies emerged overtime. The first period, from the mid-1960s to the mid-1970s, is characterized by theuse of diode-active devices and waveguide transmission lines and resonators. Thegreat technology push during this period provided a replacement for vacuum tubesin both military and commercial communications systems. Reliability was a majormotivating factor. Vacuum tube systems were famous for failing at the worst possi-ble time, and it was widely felt in the 1960s that a switch to solid state, even withreduced performance, would significantly improve system reliability [3]. The ques-tion of the day became, what vacuum tubes can realistically be replaced bysolid-state devices? Since solid-state devices could not generate the RF power of themagnitude that vacuum tubes were capable of, the first targets were applicationsnot requiring high RF power levels. Examples of these include receiver local oscilla-tors and low power transmitters. Most mixers in this period were already usingsolid-state designs employing point contact diodes, or Schottky diodes, as the activedevices. It was therefore very natural to include a solid-state local oscillator as an

1

integral part of these mixers, forming a nearly complete solid-state receiver. Thisneed was filled by replacing klystron vacuum tubes with Gunn diode oscillators. Theexception to the trend toward solid state within receiver systems was the low-noiseamplifier, which remained a TWT until gallium arsenide (GaAs)metal-semiconductor field-effect transistors (MESFETs) became more widely avail-able. Low- and medium-power transmitters evolved into solid-state designs; Impattdiode oscillators were used as replacements for klystron, TWT, and magnetron vac-uum tubes in these applications. Along with reliability, the new solid-state hardwareoffered the systems designer further advantages of lower power dissipation (no vac-uum tube filaments needing heater power) and lower operating voltages, eliminat-ing complex high-voltage power supplies. The RF/microwave industry very rapidlybecame sold on the virtues of solid-state hardware. We were ready for the nextimportant period of development.

The second major period is characterized by the availability of GaAs MESFETdevices [4]. With the arrival of GaAs MESFET devices, three terminal devices wereat long last available to the RF/microwave circuit designer. Microstrip transmissionlines were introduced during this period [5]. Microstrip transmission lines are usu-ally patterned on thin film ceramic substrates. Using photolithographic techniques[4], the circuit designer can fabricate an entire network of microstrip transmissionlines on a single thin film ceramic substrate, and using so-called hybrid assemblytechniques, circuits may be assembled by connecting active devices such as GaAsMESFETs and diodes to the patterned ceramic substrates using wire-bonding tech-niques. The field was revolutionized with the development of these RF/microwavethin film hybrid circuits. It was now possible to construct an entire subsystem withina single small mechanical housing. When compared to the old technologies usingvacuum tube equipment or even the diode/waveguide solid-state equipment fromthe recent past, the savings in terms of size, weight, and power consumption weredramatic.

During the cold war military buildup following the end of the Vietnam War,considerable research and development funding for this type of work became avail-

2 Introduction

Figure 1.1 A timeline showing how the RF and microwave electronics field has evolved throughfour distinct phases during the last forty years.

able from the U.S. government. For this reason, many of the applications addressedby the emerging solid-state RF/microwave technology were military in nature. Infact, RF/microwave technology development coincided with a major cold war armsbuildup in both the United States and the Soviet Union. The compact hardware,made possible by the use of ceramic microstrip circuits and GaAs transistors anddiodes, found ready application in newly designed radar, electronic warfare, andmissile systems. This period extended from the mid-1970s to the mid-1990s. It wasa very intense and exciting two decades of design progress. The domain ofsolid-state circuits was growing by leaps and bounds. With the advent of GaAsMESFET devices, both low-noise and medium-power TWTs were at last replacedby solid-state transistor amplifiers [7]. These ceramic microstrip hybrid circuitswere capable of extremely wide bandwidth operation. This was a great advance forelectronic warfare systems, which depend on the ability to acquire random signalsover a wide range of possible input frequencies. TWT amplifiers were no longerneeded in such systems. The elimination of TWTs created an opportunity fortremendous savings in terms of cost, power, and weight in many airborne systems.All of these technological advances worked in combination with advances in otherareas, such as engine design, new materials, and life support, to make possible thehigh-performance military aircraft that became available toward the end of the coldwar period.

The third significant period of RF/microwave technological development grewout of the desire to reduce the cost, size, and weight of RF/microwave solid-state cir-cuits. The path to cost and size reduction followed the same route as that followedby both digital and low-frequency analog circuits: the implementation of integratedcircuit (IC) techniques. Since GaAs MESFET devices had very quickly become themost important solid-state active device at these frequencies, an integrated circuittechnology was needed that would build on GaAs MESFETs. Fabrication technol-ogy for GaAs integrated circuits became available in the mid-1980s [8].

At first, these so-called microwave monolithic integrated circuits (MMICs)were limited to perhaps two transistors and some matching elements, but over timeMMICs grew to include enough components to make up entire amplifiers and evensimple subsystems. MMICs made use of a particular property of undoped GaAssubstrates: their high natural resistance. In fact, undoped GaAs, unlike undoped sili-con, is an excellent insulator. This means that the undoped GaAs substrates used inMMIC circuits are excellent media for microstrip lines. Furthermore, since thedielectric constant of GaAs is 12.5, such transmission lines are physically short,reducing size, weight, and total cost. As cost depends heavily on total die area, thisunique new MMIC technology held the promise of replacing much of the then exist-ing ceramic microstrip hybrid hardware with low-cost, fully monolithic,MMIC-integrated circuits.

This promise has been only partially fulfilled because of two factors: First, thereis the issue of tuning (or tweaking). Hybrid ceramic circuits had always required amoderate amount of expensive hand alignment. This alignment, known in theindustry as “tweaking,” accounted for much of the hardware’s cost. However, inthe case of MMIC circuits, it was no longer possible to tweak the circuit because it isan integrated circuit and too small for any hands-on alignment (even if the insulat-ing passivation layer were to be left off in processing) to be practical. This means

Introduction 3

that either MMICs work or they don’t. However, it’s not quite that simple. Varia-tions in the fabrication process occur from wafer to wafer, which can significantlyaffect the performance of an MMIC circuit. Wafer-to-wafer variations reduce theoverall yield of MMIC devices, and depending on the degree of difficulty of the elec-trical specifications, the yield may be quite low, which tends to cancel out the costadvantages of using an MMIC approach in the first place.

Two possible solutions to these problems were attempted. The first was moreexact modeling, and the second was improved process uniformity. The first solutionmade use of models that allowed the simulation of a wide range of electrical parame-ters, not just the small-signal S-parameters, which were customarily used in hybridceramic circuit simulations. The new models created for MMIC applications had tobe able to function over a large range of signal levels, including dc behavior. Thesemodels, generically called large-signal models, were far more complex than thesmall-signal S-parameter models that preceded them. Considerable effort andexpense went into the development of these large-signal models, with the hope thatif the new MMIC circuits could be modeled accurately and completely, their yieldswould increase. The effort was only partially successful because of a second majorissue: wafer-to-wafer variations during fabrication. All the modeling precision in theworld won’t increase yield if the model parameters keep changing in unpredictableways. To improve this situation, the foundries (fabrication facilities) attempted touse more repeatable processes. The most significant change was a switch from wetetch processing (involving placing the wafers into chemical baths) to a dry etch pro-cess (which makes use of a plasma that impinges very uniformly onto the wafer in aspecially designed vacuum chamber). However, not all etching processes could beswitched to dry etch. In particular, the gate recess etch step in fabricating theMESFET device’s gates could not be done by dry etch and had to remain a wet etchprocess step. A lot of device variation is experienced in this one step, and it is a chal-lenge to model developers and circuit designers alike to deal with this variation. Thissituation has never been totally resolved. MESFET circuits today still experience sig-nificant process variations that affect yield, sometimes profoundly. By necessity,designers have developed ways of optimizing their circuits for process variations sothat yield number can be increased. However, to date no universal solution to thisproblem has been identified.

History intervened at this point to create a shift in emphasis and application. In1991, the Soviet Union ceased to exist, and the cold war ended. As a result, the ongo-ing demand for improved military hardware came to an abrupt end, and govern-ment-sponsored research and development funding sharply declined. This globalpolitical change created temporary hard times for companies and individuals work-ing in RF and microwaves throughout the 1990s. However, just as the RF/micro-wave electronics field descended into decline with the end of the cold war, thetechnology quickly came back to life with the arrival of the wireless revolution,which began gaining energy in the second part of the 1990s.

The emergence of wireless technology signaled the beginning of a fourth periodof technology development, and work in wireless research and development contin-ues today. This period signaled the emergence of radio frequency integrated circuits(RFICs) as a major driver of progress in RF and microwaves. The timeline presentedin Figure 1.2 focuses on the applications in each time period. Wireless applications

4 Introduction

are the latest period. In many ways, wireless applications feel like “back to thefuture.” The focus is changing to narrowband applications at relatively low fre-quencies (1 to 4 GHz). This is a dramatic shift from ceramic/hybrid and MMICtechnologies, where the focus was on very broadband applications at high frequen-cies (up to 25 GHz). However, the concept of RFIC was born out of the need toserve these applications.

New high-frequency fabrication technologies began to appear. All during thepurely microwave–millimeter-wave period (late 1960s to mid-1990s), the dominanthigh-frequency fabrication technology was GaAs MESFET. However, by the late1990s, GaAs MESFET was joined by the GaAs heterojunction bipolar transistor(HBT) [9] whose advantages relative to GaAs MESFET are discussed throughoutthe present book. MMIC designers were quick to perceive the advantages of GaAsHBT, and many designers changed technologies, especially for cellular infrastruc-ture applications. Within a short period, designers began designing PAs for mobilehandsets using GaAs HBT. During this largely III–V compound semiconductordesign period of the late 1980s, MMIC designers gave considerable attention to cel-lular applications. Due to the low-frequency (0.80 to 1.9 GHz) operations associ-ated with cellular applications, these new integrated circuits came to be calledRFICs, rather than MMICs. RFICs have operating frequencies more in keepingwith traditional RF frequencies than with the higher microwave frequencies associ-ated with MMICs.

Then, the world changed again, in many ways, all at once. First, new sili-con-based fabrication technologies [silicon germanium (SiGe), BiCMOS, andRFCMOS] became available [10]. Second, in order to reduce cost and size, therewas a major push toward higher levels of integration. This trend toward high ICintegration was the key ingredient responsible for morphing the “brick” cellulartelephone of the 1990s into the palm-sized “clam shell” phone of today. Today,everyone, young children included, uses cell phones. This is true not only in theUnited States but worldwide. In terms of availability, cell phones are to this decadewhat personal computers were to the 1980s and 1990s. Mobile cellular phones haveindeed changed the world, and these emerging IC technologies had a lot to do with

Introduction 5

Figure 1.2 A timeline showing the most important application associated with each phase in thedevelopment of the RF and microwave electronics field.

it. These new product trends were driven by the availability of new and highly inte-grated RFICs. Transceiver designs moved away from realizations involving separatecomponents attached to a common PCB, to one (or a few) RF chips based on one ofthe new silicon technologies. Currently, many low-frequency analog designers areentering the field in order to apply their craft of designing very large integrated cir-cuits to the RF frequency range. Most of the GaAs technologies have been ignoredby these analog designers (because of cost) when designing the new, highly inte-grated transceiver chips.

There are two exceptions to this trend. The first is infrastructure amplifiers andmixers, which remain mostly in GaAs. The second exception includes handset PAsand T/R switches, which also remain in GaAs. The scope of this book is chiefly thosedesigns made in support of cellular infrastructure and instrument applications. So,the question remains, are these cellular infrastructure (and instrument) amplifiers,mixers, voltage-controlled oscillators (VCOs), and switches, strictly speaking,RFICs or MMICs? Good question. It all depends on how one defines MMIC andRFIC technologies.

In many ways, RFIC devices are replacements for discrete circuits. Their fre-quencies are low enough and their bandwidth is narrow enough that, in general,transmission line parasitic elements do not greatly affect performance. This is a bigrelief to the designer, who is not facing the difficult goals of wide-bandwidth,high-frequency operation where designs require modeling every transmission linelike parasitic elements in order to succeed.

RFICs have always relied on the same circuit elements used in MMICs use, suchas spiral inductors and metal insulator metal (MIM) capacitors. These elements nat-urally have complicated models, each of which must be carefully analyzed in atop-notch simulator in order to predict performance accurately. Like the MMICbefore it, the RFIC cannot be tuned, or “tweaked.” Once it is fabricated, “what yousee is what you get.” To avoid a costly series of design “spins,” it is very importantto model and simulate an RFIC accurately. However, these concerns can be miti-gated to some degree by using feedback (both digital and analog) to control perfor-mance parameters. Some examples are variable bias circuits and automaticgain-control circuits.

Concurrent with the wireless revolution of the late 1980s and early 1990s, asimilar revolution was happening in device and fabrication technology. For manyyears, the only transistor technologies available to the RFIC/MMIC designer hadbeen silicon bipolar or GaAs MESFET. That situation changed drastically duringthis period for two important reasons. The first was the exploration and exploita-tion of heterojunctions, and the second was the availability of CMOS devicesoperating at RF/microwave frequencies. Heterojunction devices were first proposedin the late 1950s by Herb Kromer, who ultimately won a Nobel Prize for thiswork [11].

Heterojunctions significantly increase the degrees of freedom available to thedevice designer. No longer are device parameters adjustable only with doping gradi-ents; with heterojunctions, the dissimilar material’s energy band gap becomes acontrolling aspect for determining performance The Ft performance ofnonheterojunction transistors (i.e., homojunction transistors) is dependent on theratio of the donor concentrated in the emitter to the acceptor concentration in the

6 Introduction

base. To increase Ft, the acceptor concentration must be kept low, raising the baseresistance. This all changes in heterojunction transistors, where energy band gradi-ents maintain high emitter injection efficiency, allowing the acceptor concentrationto rise. With this newfound design freedom, device designers were able to makegreat improvements in the design of traditional devices and also to come up withsome totally new device types. GaAs MESFETs were transformed intoGaAs/AlGaAs PHEMTs. Silicon bipolar transistors became SiGe heterojunctiontransistors. For the first time, it became possible to make GaAs bipolar transistor inthe form of InGaP/GaAs HBTs. Later on, indium phosphide (InP) HBTs becameavailable. All of these devices offer significant performance improvements overtheir nonheterojunction cousins [12].

At the same time that these advances were being made with heterojunctions, theworld of CMOS was moving up in frequency. By the late 1990s, CMOS perfor-mance had improved to the point that it also became a major player in RFIC fabri-cation technology. Instead of having only two transistor technologies available,RF/microwave circuit designers started exploring at least six options. The RFICfield had become a new world.

This revolution was most profound in the area of bipolar technologies. It hadlong been known that bipolar devices held significant advantages for designing cer-tain circuit types, such as low phase noise VCOs. Singular polarity bias is also a bigplus with bipolar devices. Also, bipolar devices are often significantly more linearthan their field-effect transistor (FET) cousins. Linearity is a key specification inmany wireless components, like power amplifiers. The main problem had beenwhat to do at high frequencies where silicon bipolar devices do not function well.Then, the InGaP/GaAs HBT transistor entered the scene, and the frequency barrierwas knocked aside. Now, bipolar designs could be produced for any wireless fre-quency that was being addressed. However, performance was not the only advan-tage offered by the heterojunction bipolar devices. High fabrication yield was also asignificant factor. The yield for this class of device was far superior to the yield expe-rienced with field-effect transistors, such as GaAs MESFET. The vastly improvedyield of InGaP/GaAs HBTs is simply related to their required metal line dimensions.GaAs MESFET and PHEMT devices require very narrow gates with lengths in the0.15–0.30µm range. As discussed above, such narrow gates are very difficult to fab-ricate consistently at high yields, as a result of the wafer-to-wafer variation associ-ated with the necessary wet processing steps. The situation changes radically withInGaP/GaAs HBTs, where the minimum required metal width is about 2µm, a rela-tively large dimension for an RF/microwave device. No longer does the metal pat-terning step control performance and yield, but the actual epitaxial deposition stepis now responsible for determining both performance and yield. Epitaxial processessuch as MBE and MOCVD are very well controlled and are uniform [13]. There-fore, InGaP/GaAs HBT devices enjoy a remarkably uniform fabrication, and electri-cal yields are usually in the high 90 percent range. In fact, yields are so high withthese devices that designing for yield, as has been done for years by GaAs MESFETdesigners, is no longer required. HBT designers simply design to meet a specifica-tion and enjoy the advantage that if one circuit works to specification, all the restwill too.

Introduction 7

Another major advantage of bipolar devices is their significantly improvedlarge-signal models relative to FET-type devices. Initially, all HBT devices weremodeled using the same Gummel Poon model originally developed for modelinglow-frequency silicon bipolar transistors. This model worked very well forInGaP/GaAs HBTs. In fact, Gummel Poon models produced simulations that werefar more accurate than those previously performed using available GaAs MESFETdevice models, such as the Curtice model or the Statz model. For the first time in theexperience of many RF/microwave designers, it became possible to simulate a com-ponent’s small-signal gain and match, dc parameters, power output, harmonics, andtwo-tone intermodulation performance, as well as to get results that closely agreedwith measurements—consistently. Since from a designer’s point of view RFICs are awhat-you-see-is-what-you-get experience, having a simulator model that reallyworks is an enormous advantage.

In spite of early successes, the Gummel Poon models had certain flaws whenapplied to GaAs devices. These deficiencies included the lack of a self-heating model(which is very significant in GaAs), the lack of Early voltage effect models, and thelack of avalanche multiplication modeling. These deficiencies were addressed in animproved model developed specifically for GaAs HBT devices: the Vertical BipolarIndustrial Committee (VBIC) model. Today, most HBT circuit designers use bothVBIC and Gummel Poon models, enjoying accurate simulations with either model.In my experience, both models do an excellent job at low frequencies, but the VBICmodel does seem to agree more closely with measurements at higher frequencies. Inthe end, the choice of model may depend on what models are available at thefoundry with which you are working. Be sure to check with the foundry for verifica-tion of model accuracy.

Since the introduction of InGaP/GaAs HBTs, two other very significant HBTtechnologies have been introduced. These are silicon germanium (SiGe) and indiumphosphide (InP). SiGe HBT transistors use a SiGe base layer that bends the energybands within the silicon. Local bending of the energy bands increases carrier mobil-ity in this region of the transistor. The high carrier mobility within the narrow baseregion of the SiGe transistor offers profound performance advantages in terms of Ft

and Fmax, relative to its all-silicon cousins. Today’s SiGe transistors offer an Ft of wellover 200 GHz. However, they have inherently low breakdown voltages, andtherefore the high Ft devices must be operated at low voltage. This is both good newsand bad news, when compared to their higher-voltage InGaP/GaAs HBT brothersand sisters. The good news is that since SiGe devices operate naturally at lower biasvoltages, they are naturals for a wide range of circuit designs intended for bat-tery-operated mobile applications. The bad news is that their inherently low break-down voltages may limit their usefulness as power amplifiers. Of course, breakdownvoltage can be traded off with Ft as a part of the device design process.

A third HBT technology looming on the horizon is InP HBT. This type of devicecombines high breakdown voltage with high Ft and Fmax. Currently, InP HBT is themost expensive of these three HBT technologies. However, if demand develops forthe performance offered by InP HBT, surely its cost will go down. Figure 1.3 showsa comparison of the three HBT technologies. SiGe offers the lowest cost in produc-tion but is somewhat limited by its low breakdown voltage. InP HBT has the highestperformance in terms of Fmax, Ft, and breakdown voltage. However, as mentioned

8 Introduction

above, right now InP HBT is very expensive. InGaP/GaAs is midway in terms of per-formance and cost and may be the ideal solution in many applications. However,InGaP/GaAs has a significant disadvantage for battery-powered wireless applica-tions because its Vbe is relatively high (1.4V). There is almost a factor of two differ-ence in Vbe between these two technologies, with SiGe having a Vbe = 0.70V. This isvery significant in battery-powered applications where +3.0V is the maximum sup-ply voltage available. In devices such as Gilbert cell mixers, where three devices areschematically “stacked” on top of each other, the device’s Vbe values will multiplyby the number of stacked devices to determine a bias requirement, which must beless than the supply voltage. For InGaP/GaAs HBT, Vbe is 1.4V, which means for amixer with three stacked devices, the supply voltage must be at least 3 × 1.4 = 4.2V,which will not work with many popular batteries. However, for SiGe, the value ofVbe is 0.70V, so the minimum supply voltage for a similar Gilbert cell mixer is3 × 0.7 = 2.1V, which is completely compatible with a lithium ion battery operatingat 3.3V.

SiGe has the additional advantage of being available as a BiCMOS process atsome additional cost. This means that in addition to the SiGe HBT bipolar devices,the designer has access to a full set of CMOS devices that are useful for designingdigital control circuits and low-frequency analog circuits. This added flexibilityoffers a very significant advantage for SiGe technology because of the ability of theCMOS devices to serve as switches and digital control elements.

Currently, the RFIC world seems to be heading in the direction of using RFCMOS designs, where the lowest possible production cost is the most importantconsideration. However, if performance (or time to market determined by reducingthe number of design spins) is also a key consideration, then SiGe technology holdsconsiderable advantages, especially in designs where low-phase-noise VCOs are ofparamount importance. Since the 1/f noise corner frequency for SiGe is about 800Hz, VCOs using SiGe offer the lowest possible phase noise and phase jitter for agiven resonator Q. By comparison, the 1/f noise corner frequency for RF CMOS is

Introduction 9

Figure 1.3 A chart comparing the collector-to-emitter breakdown voltage and the frequency ofunity current gain (Ft) for three heterojunction bipolar technologies.

between 1 and 10 MHz, which is an inherent disadvantage in extremelyphase-sensitive applications, such as higher-order phase modulations like N–quad-rature amplitude modulation (N-QAM), where a maximum number of bits per sym-bol is required to produce a high data rate. As the number of phase states, N,increases, the effects of phase noise become profound. For 16-QAM and above, LOphase noise can be a serious limiting factor relative to bit-error rate (BER) and, mostimportantly, on data rate. SiGe technology may well be the answer to these prob-lems as wireless technology moves to higher and higher data rates.

InGaP/GaAs HBT technology is the prime fabrication technology for gain blockamplifiers and power amplifiers. This situation is not likely to change any time soon.InGaP/GaAs HBT has a rare combination of high linearity and the ability to producehigh dc-to-RF conversion efficiency, making it ideal for the design of stand-aloneRF/microwave amplifiers. Since it is very difficult to design efficient power amplifi-ers at low supply voltages, it is likely that power amplifiers, even in battery-operatedequipment, will remain in InGaP/GaAs HBT technology for the foreseeable future.

In spite of its high cost, InP HBT is a rapidly expanding technology for use athigh frequencies, especially at millimeter-wavelengths (25 to 70 GHz). Thesedevices bring the advantages of bipolar transistors to a region of the spectrum thathas long been dominated by the field-effect PHEMT technology. With the combina-tion of SiGe HBT, InGaP/GaAs HBT, and InP HBT, the wireless communicationsindustry now has available the process technologies to bring the bipolar advantagesto all parts of the radio spectrum. Since circuit topologies are common for a givendevice type, circuits developed for one of these technologies are easily transferable toanother technology simply by making model changes in the simulator. Where thehighest possible performance, and shortest time to market are required, these threebipolar technologies are poised to satisfy the needs of the RFIC industry both todayand in the future.

This book is dedicated to equipping the circuit designer with all the necessarytools to be successful at RF/microwave RFIC design using HBT bipolar devices.There are several good books available for designing RFICs with CMOS technology[14, 15]. A book is urgently needed to support the designer who is working withheterojunction bipolar RFIC technologies. This book is designed to fulfill a similarneed for designers working with RFICs based on heterojunction bipolar transistors.

Applications for RFICs, along with typical chip architectures for fulfilling theneeds of these applications, are discussed within the book. Both InGaP/GaAs HBTand SiGe HBT process technologies are presented in order to provide the processknowledge the designer needs to achieve her or his goals. Several design techniquesfor passive circuits, including filters, couplers, splitters, and phase shifters, are pre-sented.

Amplifier design concepts are discussed, including specific approaches to thedesign of low-noise amplifiers (LNAs), PAs, and wideband gain blocks. Followingthe amplifier design material, there is a chapter on mixer design and a chapter on fre-quency multiplier design. The design of VCOs is covered in Chapter 13. ThroughoutChapter 13, numerous VCO design examples are presented. Phase-noise conceptsare discussed in detail, and examples of low-phase-noise VCO design are given. Alldesigns are simulated using the Agilent Advanced Design System (ADS®) simulationtool set.

10 Introduction

The final two chapters disclose, in a general way, the considerations that thedesigner must keep in mind when approaching the circuit layout, as well as eco-nomic considerations and how they effect many design decisions.

References

[1] Milnes, A., Semiconductor Devices and Integrated Electronics, New York: Van NostrandReinhold, 1980.

[2] Gunn, J., “Microwave Oscillations of Current in III–V Semiconductors,” Solid State Com-munications, Vol. 1, September 1963, pp. 88–91.

[3] Freeman, R., Telecommunication Transmission Handbook, New York: John Wiley andSons, 1981.

[4] Vendelin, G. V., Design of Amplifiers and Oscillators by the S-Parameter Method, NewYork: John Wiley and Sons, 1982.

[5] Edwards, T., Foundations for Microstrip Circuit Design, New York: John Wiley and Sons,1983.

[6] Sweet, A., MIC and MMIC Amplifier and Oscillator Circuit Design, Norwood, MA:Artech House, 1990.

[7] Johnson, E., “Physical Limitations on Frequency and Power Parameters of Transistors,”RCA Review, Vol. 26, June 1965.

[8] Williams, R., Gallium Arsenide Processing Techniques, Boston: Artech House, 1984.[9] Liu, W., Handbook of III–V Heterojunction Bipolar Transistors,” New York: John Wiley

and Sons, 1998.[10] Cressler, J. D., and Niu, G., Silicon-Germanium Heterojunction Bipolar Transistors,

Norwood, MA: Artech House, 2003.[11] Kromer, H., “Theory of a Wide-Gap Emitter for Transistors,” Proc. IRE, Vol. 45, No. 11,

November 1957, pp. 1535–1537.[12] Singh, R., Harame, D., and Oprysko, M., Silicon Germanium Technology, Modeling, and

Design, New York: IEEE Press and Wiley Interscience, 2004.[13] Liu, W. Fundamentals of III–V Devices, HBTs, MESFETS, HFETS/HEMTs, New York:

John Wiley and Sons, 1999.[14] Lee, Designing CMOS RF Integrated Circuits, Cambridge: Cambridge University Press,

1998.[15] Razavi, B., RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.

Introduction 11

C H A P T E R 2

Applications

2.1 Cellular/PCS Handsets

Almost all applications for RFIC devices lie within the family of technologies thathave come to be known as wireless communications. Although “wireless” is an oldterm that goes way back to the early days of the development of radio, it has in thelast few years been rediscovered, dusted off, and applied to a menagerie ofhandheld, battery-operated, portable applications that use radio signals instead ofwires to carry voice and digital information. But when you say the word “wireless”to laypeople today, their immediate reaction reveals that they are thinking aboutcell phones. For well over fifteen years, cellular telephones have become an increas-ingly important fixture in modern life. In the summer of 2005, my wife and Ivacationed in Alaska. Our cruise ship’s first port of call in Alaska was Ketchikan.Eager to see everything, we walked around the downtown area near where thecruise ships dock. There were countless little shops, tearooms, and such, and wewanted to look in each one. One shop sold Russian handicrafts, icons, Babushkadolls, and the like. I asked the saleslady where she was from. She told me that every-one who worked in the shop was from Russia, and her home was in a region of cen-tral Russia just north of the Caspian Sea. She showed me her hometown on the mapof Russia hanging behind the cash register. I remarked that living so far from homemust be very lonely for her. She brightened up and said that although she missed herfamily very much, every afternoon at 5 p.m., she used her cell phone to speak withher mother in Russia. It made her happy to be able to stay in touch with her familywhile so far from home. At home in Russia, her mother also used a cell phone tocommunicate with her daughter. If ever I needed proof that cell phones (and allwireless technology) have truly changed the world, there it was. Cellular telephonetechnology has quickly moved from a novelty or luxury to an important accessorythroughout the world. Cell phones have made it possible for families and friends tostay in touch regardless of the distance separating them. Wireless technology asapplied to cellular telephones has produced a worldwide revolution in the lives of somany that its impact is comparable to the revolution caused by the printing pressand later by personal computers.

Oddly enough, although cellular telephone technology was originally devel-oped in the United States in the 1960s, cellular telephone service was not consideredcommercially viable in the U.S. at the time, and was first put into commercial ser-vice in Finland and Sweden. Europe and, more recently, Asia have become leadersin cellular technology development. Much of the world looks to these geographicregions to buy both equipment and technology. Today, throughout the world are

13

communities are rushing to install cellular systems within their countries in order tohave access to modern telecommunications with quality that compares favorably tothat of the wire line phone services available in industrialized countries.

The first cell phones were for use in the car only (known as car phones) andconsisted of a transceiver box permanently mounted under the driver’s seat with ahandset attached to the steering column. An outside antenna had to be mounted onthe top of the car or on the rear trunk lid. Later, as development proceeded, a smalltransceiver and handset were placed in a carrying bag (about the size of a camerabag), along with an antenna mounted on suction cups and a rechargeable battery.The bag phone was a big step forward in terms of mobility, but it was still heavy andcumbersome. Next, on the scene was the handheld unit. Not much larger than awired phone everyone was accustomed to, this diminutive phone included a built-in antenna and a self-contained, built-in battery pack, and it demonstrated a majorstep forward in the ongoing demand for smaller and smaller phones. Because of itsweight, this new model quickly became known as “the brick.” Integrated RF circuitshave played a major role in the ongoing miniaturization of cellular telephone equip-ment, enabling cell phones to shrink down to the size they are today. Future develop-ments in RFIC technology will make it possible for a single cellular telephone tohave the flexibility to operate at many different frequencies using many differenttransmission standards. Future cellular phones, using ultraflexible RFICs, will becapable of being instantly and automatically configured to adapt to different operat-ing systems, using a concept called cognitive radio, which is discussed in more detailin Section 2.8 [1].

The first cell phone systems used analog frequency modulation (FM) and oper-ated in the 800–900 MHz region of the radio spectrum. These systems worked quitewell, especially considering just how new and revolutionary the technology was. Butthey had numerous problems with noise and interference as a result of the FM sys-tem’s analog nature. In the United States, a standard called the Advanced MobilePhone Service (AMPS) [2] was developed to cover these first analog phone systems.Today, the AMPS system is regarded as the first-generation (1G) of cellular tele-phone technology. AMPS phones had problems with “handoffs” between cell sitesand system capacity, which limited the spacing between cellular base stations andthe maximum number of users who could be on the system at the same time. In orderto resolve these problems, the cellular telephone industry next adopted digital tech-nology with the introduction of what is now known as second-generation technol-ogy (2G).

Digital cellular technology uses digital phase modulation [3] for improved sig-nal-to-noise ratio (SNR) and improved interference rejection. Digital cellular tech-nology also offers some form of “multiple access,” enabling higher system capacitythan would have ever been achievable with the analog AMPS systems. These digitalmultiple-access techniques fall into two basic approaches: the first is time domainmultiple access (TDMA), and the second is code domain multiple access (CDMA).With TDMA, the digitized voice signals are grouped into packets of bits transmittedby each mobile unit within a prearranged time slot. At the end of its assigned timeslot, the mobile unit listens for a retuning packet from the cellular base station. Allsystem users repeat this process within their own time slots, and at the end of the listof users, the process repeats. This process works in a way that is something like a

14 Applications

group of people moving through a revolving door one person at a time (each personrepresents one digital information packet). Two examples of TDMA-based systemsstandards are the North American Digital Cellular (NADC) and the Global Systemfor Mobile Communications (GSM) [4]. TDMA systems operate at frequencies of800 MHz, 1,800 MHz, and 1,900 MHz.

The second major multiple-access technique is CDMA. In CDMA systems, aprearranged code modulates the signal from the mobile unit so that it can be distin-guished from the other mobile units (which are transmitting at the same frequency)when received by the base station. The code used to distinguish mobile units iscalled a spreading code because the code is applied to the signal as modulation,which “spreads” the signals in the frequency domain, creating what is called aspread-spectrum transmission. In a spread-spectrum signal, the transmitted powerin a given narrowband frequency segment is very low, but when all of the transmit-ted power is integrated over frequency (at the base station’s receiver by using theidentical spreading code), the total received power is quite high. The base station’sreceiver will reject an interfering signal that does not have the right code modula-tion. The amount of interference rejection available in a CDMA system is called thesystem’s process gain. By taking advantage of process gain, the use of spreadingcodes in CDMA systems allows them to distinguish between mobile units and, atthe same time, provide a high degree of interference rejection.

2.2 Cellular/PCS Infrastructure

All cellular/PCS systems require that a base station be located in each of the system’scells. The total of all base stations in a given system is called the system’s infrastruc-ture. The infrastructure must contain a set of high-level, omnidirectional antennas,a high-power transmitter, a highly selective receiver, and a connection to the tele-phone system’s wire lines. Although size is not the critical factor in infrastructureapplications that it is with mobile handsets, many, if not most, of the RF circuits inmodern cellular infrastructures are now RFICs. The architecture of the base sta-tion’s receiver and transmitter is very similar to the architecture used in handsets;the primary difference is found in the higher power of the transmitter and in thehigher selectivity of the receiver. In both the receiver and the transmitter, it is abso-lutely essential that all components have the best possible linearity in order to keepdistortions in the presence of multiple signals at a minimum. Relative to the RFICsused in these applications, the linearity requirements usually translate into anintermodulation intercept point specification, or an adjacent channel power ratio(ACPR) specification. In particular, infrastructure transmitters often have long, cas-caded chains of gain block amplifiers with excellent linearity, as indicated by theirhigh intermodulation intercept point performance. Cellular base station transmitpowers often exceed 50W, making it necessary to use LDMOS devices in the laststage or two to achieve the final transmit power.

Base station mixers must also be capable of linearity performance similar to thatrequired of the base station amplifiers. Many signals simultaneously arrive at themixer, which is located within the receiver’s front end. In order for the system toremain highly selective under these conditions, it is necessary for the receiver mixer

2.2 Cellular/PCS Infrastructure 15

to have excellent linearity, as indicated by its intermodulation intercept point. Like-wise, the receiver’s LNA and its accompanying intermediate-frequency (IF) amplifi-ers also must have a high degree of linearity in order for the receiver to remainselective in the face of so many input signals.

In Europe and Asia, there is growing demand for a class of systems called cellu-lar repeaters. Cellular repeaters are located in areas where cellular reception is poorbecause of shading, multipath cancellation, or poor signal penetration. Theserepeaters can bring high-quality cellular service into areas previously considered tobe in the “fringe area” of service. Cellular repeaters are often located in office build-ings, high-rise apartment buildings, and subways. Cellular repeaters are particularlypopular in those parts of Asia where population densities are very high and cellularphone usage is much higher than wire line service. Cellular repeaters are of lessimportance in North America, where population densities are much lower thanin Asia.

Cellular repeaters come in one of two types: straight amplifier chains anddownconverting/upconverting chains. Straight amplifier chains have the advantageof simplicity but are subject to instability under certain conditions (i.e., “leakage”from the transmitting antenna to the receiving antenna). Downconverting/upconverting chains are less susceptible to instability but are more complex andmore expensive. The trend in repeaters is toward smaller and smaller units that canbe mounted almost anywhere (such as an office window). For this reason, repeatersare experiencing some of the same miniaturizing demands that affect the RFICs formobile handsets.

Recent advances in third-generation (3G) cellular technology offer higher datarates and the associated auxiliary services using higher data rates, such as textmessaging and multimedia. At present, there are many kinds of 3G systems underdevelopment, and it is likely that many different standards will be rolled out world-wide in the next few years. The first such systems are now available in Asia, but itmay take some time before similar service becomes available in North America. 3Gsystems require even higher degrees of component linearity than the equivalent 2Gsystems. Also, the 3G frequencies will be higher, and the bandwidth requirementswill be wider. This means that RFIC designs for 3G systems will be even more chal-lenging that those already developed for present 2G cellular systems.

2.3 WLANs

Wireless local-area networks (WLANs) provide computer users with high-speedwireless networks that operate very similarly to wired Ethernet. WiFi (802.11a/b/g)[5] operates in the unlicensed (ISM) bands at 2.4 GHz and 5.1–5.8 GHz. The Insti-tute of Electrical and Electronics Engineers (IEEE) standard for WLANs is 802.11,whose three versions are called “a,” “b,” and “g.” Version a operates at frequenciesin the range of 5.1 to 5.8 GHz with a data rate of 50 Mbps. Version “b” operates ata frequency of 2.4 GHz with a data rate of 11 Mbps. Version “g” operates at a fre-quency of 2.4 GHz with a data rate of 50 Mbps. The 802.11 standards of operationare often collectively called WiFi (i.e., wireless fidelity).

16 Applications

Most WiFi equipment takes the form of a PCMCIA card inserted into a laptoppersonal computer. WiFi operation may involve connecting through an “accesspoint,” making a computer part of a wireless network, or a WiFi operation may linkonly two computers, which is called “peer to peer.” WiFi equipment is capable ofconnecting a computer to an access point (or a computer to another computer) overa range of 100m indoors, or up to a quarter-mile line of site. There are fourteenWiFi channels, and most installations automatically search for the channel with theminimum amount of interference at any given time. WiFi transmit power is typi-cally 10 to 100 mW. The signal bandwidth is approximately 20 MHz wide as adirect result of the broadband nature of the information being transmitted.

WiFi systems generate and transmit “packets” of data. After the data packet istransmitted, the transceiver system will automatically be switched to receiver modefor reception of a data packet from the other computer or from an access point. Inits low-speed modes, WiFi makes use of quadrature phase-shift keying (QPSK)modulation, operating in a direct-sequence, spread-spectrum mode using a Bakerspreading code. For high data rates (up to 50 Mbps), WiFi uses orthogonal fre-quency division multiplexing (OFDM) modulation. OFDM modulation makes useof a number of subcarrier frequencies, each carrying information that is multiplexedonto this array of carrier frequencies. It is the multiplexed combination of theseOFDM subcarrier channels that makes the high data rates possible.

WiFi uses relatively high transmit power (up to 100 mW), and as a result, mostWiFi devices consume a relatively large amount of dc power. Although this factordoes not preclude the use of WiFi in small battery-operated, handheld equipment,most WiFi devices are powered from the larger power sources found in personalcomputers. These devices are commercially available in the form of PCMCIA cardsfor personal computers (both desktop and laptop). These devices are also availablein USB interface form for the same purposes. The use of external antennas canextend the range of WiFi equipment; however, most installations simply use theminiature antennas that are directly attached to the WiFi device’s PCB. In mostcases, users rely on working through access points available at “hot spots” locatedat coffee shops, hotels, airports, and so forth. In some cases, communities areinstalling hot spots in many locations in order to provide the residences with WiFiservices throughout the community. WiFi is increasingly offering the mobile PCuser a true high-speed wireless network connection where ever he or she may go.

While WiFi equipment is available in both the 2.4 GHz band and the 5.1–5.8GHz band, the radio hardware in the higher band (802.11a) does not offer a signifi-cant data-rate advantage over what is already available on the lower band (i.e.,802.11g). Since the higher-frequency equipment is more expensive and has lessrange, it is not finding the same level of market acceptance as are the two 2.4 GHzstandards (802.11b and 802.11g).

2.4 Bluetooth

Bluetooth is named for the Danish king Harald I Bluetooth, who lived from ad 940to 986. The reason for selecting King Bluetooth’s name for a wireless service derivesfrom his successful uniting of the kingdoms of Denmark and Norway. This accom-

2.4 Bluetooth 17

plishment reminds developers of their goal of providing a wireless network capableof uniting computers with their peripheral devices. The name Bluetooth also is areminder of the importance of wireless development’s originating in Scandinaviancountries.

In many ways, the Bluetooth wireless standard [6] is the mirror image of theWiFi wireless standards. WiFi offers extremely high data rates, while Bluetoothoffers relatively low data rates. WiFi offers relatively long range (up to 100m insidea building), but Bluetooth offers very short range (3 to 10 ft.). WiFi consumes a rela-tively large amount of dc power, while Bluetooth consumes a relatively smallamount of dc power. While WiFi is primarily applied to the networking of personalcomputers over relative long distances, Bluetooth is most often used to link devicesthat are close together, requiring relatively low data rates. Also, Bluetooth is a natu-ral for low-battery-powered, handheld mobile devices. Some examples of Bluetoothapplications are cordless earpieces for cellular phones, wireless keyboards, wirelessmice, linking wireless PDAs to computers, and computer-to-printer wireless connec-tions. Bluetooth operates in the same unlicensed (ISM) 2.4 GHz band as WiFi. Thetype of modulation used in Bluetooth is called Gaussian frequency-shift keying(GFSK), and Bluetooth makes use of time division duplexing of its data stream.Although relatively high-power versions of Bluetooth are allowed within the stan-dard, the most common applications are for very short ranges, where battery life(i.e., low dc power consumption) is of primary importance.

2.5 UWB

The ultrawideband (UWB) transmission draft standard [7] is designed to provideshort-range wireless communications with extremely high data rates (100 to 500Mbps). These high data rates in effect make UWB a wireless USB (WUSB) standard.The primary application of UWB is the wireless transmission of video programming.For instance, UWB can be used for the wireless transmission of movies between thehard drives of two computers over a reasonable time. UWB can also be used totransmit video in real time from a digital camcorder to a personal computer for stor-age. In effect, UWB has the potential to replace the highest-speed Ethernet cables.UWB fills the need for higher-data-rate wireless transmission than can be providedby WiFi g (above 50 Mbps).

As originally conceived, UWB technology would make use of extremelyshort-duration impulses of RF energy. In the frequency domain, these pulses wouldhave energy spread over a very wide bandwidth (thus, the name ultrawide band-width). The energy at any one frequency would be very small, so UWB would notinterfere with narrowband services operating within the same band. Integrationover a wide range of frequencies is required to produce sufficient signal energy toprovide a useful signal-to-noise ratio. However, the hardware needed to create andreceive impulse UWB signals is quite challenging to design.

The original concept of UWB is still in use; however, a second approach to UWBhas gained considerable acceptance over the last few years. In this alternateapproach, a series of OFDM subchannels in the frequency domain are tied togetherand multiplexed in such a way that the total data rate of using all RF channels work-

18 Applications

ing together is extremely high. A UWB standard has evolved along both this newfrequency-multiplexed concept, as has a separate standard covering the originalshort-impulse concept. Both UWB standards operate in the 3–10 GHz frequencyrange.

Out of concern for the possibility of interference to Global Positioning Services(GPS) signals at 1.5 GHz, the Federal Communications Commission (FCC) in theUnited States has set a lower frequency limit on UWB transmissions of 3.1 GHz.The FCC has also set the high-frequency limit for UWB transmission at 10.6 GHz.The FCC’s frequency limits are relatively easy to observe in the multichannelapproach to UWB, but they require considerable filtering in the impulse approach.For this reason, today more attention is being paid to the multichannel approach toUWB. Two new standards are under development for this multichannel approachto UWB (two versions of 802.15.3a). One version uses a high-speedpulse-modulation approach to generating UWB signals; the second uses amultiband OFDM approach. Of the two, the multiband OFDM approach seems tobe gaining wider acceptance. With this standard, there is a series of fifteen simulta-neously operating, 500 MHz–wide RF bands available, covering the 3.1–10.6 GHzrange. The equipment designer is free to use any number of these bands (up to thefull fifteen). The highest data rates are achieved by using the maximum number ofRF bands. Each RF band itself is divided into a series of QPSK modulatedsubcarriers multiplexed together according to OFDM techniques. Therefore, thereare two types of multiplexing going on simultaneously: multiplexing of thesubcarriers within each RF band and multiplexing of the RF bands. If all RF bandsare used, the potential data rate could be as high as 500 Mbps.

In order to prevent interference with narrowband service operation in the3.1–10.6 GHz portion of the spectrum, the FCC requires that UWB transmissionhave a total integrated power of less than 90 mW and a power density in any 1 MHzbandwidth of less than –40 dBm. If the entire transmitted spectrum is evenly spreadover frequency, this is not a difficult standard to meet. However, if any narrowbandsignal, such as the LO carrier frequency (i.e., mixer LO leakage), is transmitted dueto imperfect mixer isolations, the –40 dBm per MHz bandwidth becomes a chal-lenging specification.

With its ability to transmit video over reasonable time periods, UWB has highpotential for the future and ultimately may replace WiFi in many high-speed appli-cations. For instance, UWB holds the promise of a WUSB connection between com-puters, with the simplicity of no wires and the high data rate associated with USB.

2.6 WiMax

WiMax is the name of a family of transmission standards that covers a wide rangeof possible frequencies, modulations, and duplex types [8, 9]. These standards arepresently lumped under the heading of 802.16a, called broadband wireless accessfor worldwide interoperability. The basic idea of WiMax is to provide broadbandwireless connection for both fixed and mobile users that will link to the Internetthrough base stations in a similar way as cellular base stations. The maximum rangebetween the user and the base station will be as great as 30 mi. This kind of service

2.6 WiMax 19

will let users access true high-speed Internet that could be available to them any-where within a very wide-ranging geographical area (i.e., 10–30 mi. radius). Fre-quencies between 2 and 66 GHz are possible locations for WiMax transmission. Themaximum anticipated data rate is 70 Mbps. It is possible that users who are notlocated in “line of sight” from a base station antenna tower may have to acceptlower data rate as a necessary trade-off for achieving a usable signal-to-noise ratio toproduce an acceptable bit-error rate.

WiMax is still in its infancy as far as hardware development is concerned. Thereis great potential for RFIC development in support of WiMax. In fact, WiMax maybecome the number one driver of RFIC development at frequencies above 10 GHz.

2.7 Digital TV and Set-Top Boxes

At this writing, the TV industry is approximately sixty years old and is embarkingon its first major technical revolution. Digital TV is beginning to emerge, and aneager general public is ready and waiting. If events proceed according to plan, mostof the U.S. television-watching population will convert to receiving digital TV trans-mission sometime over the next five years. Digital conversion will require the pur-chase of a new (and, at first, very expensive) digital TV receiver or, alternatively,living with the existing analog TV receiver supplemented by an additional “set-topbox.” A set-top box contains digital tuners and all the necessary electronics for con-verting digital video and audio signals into a format that can be processed and dis-played by an existing analog television receiver. It is expected that there will be amass market for set-top boxes as more and better digital programming becomeswidely available to the consumer. Set-top boxes will include a number of RFICdevices, such as digital tuners, amplifiers, and switches. With the expected futurepopularity of set-top boxes as digital TV takes off, a significant RFIC developmentin support of digital TV is anticipated to take place over the next several years.

2.8 Cognitive Radio

In recent years, the pace of rolling out new wireless services has become breathtak-ing. Today, the worldwide number of wireless standards and services is truly amaz-ing, and for most of us, it has become difficult to keep up with all of the changes.This situation is particularly hard on equipment manufacturers, who must at regularintervals redesign their equipment to accommodate this flood of emerging stan-dards.

In order to prevent these redesigns from placing impossible-to-fulfill demandson designers and manufacturers alike, a desire has recently arisen on the part ofmany in the wireless industry to design equipment hardware that is sufficiently flexi-ble to be reprogrammed to instantly accommodate new standards operating in newfrequency allocations. An additional advantage of these cognitive (or soft-ware-defined) radios [10, 11] would be their ability to quickly assume a new stan-dard identity, making use of free spectrum on the fly, in order to best serve thereal-time needs of users. In fact, it is conceivable that such a cognitive radio system

20 Applications

might switch from one standard to another in short order, changing frequency witheach standard’s change, in response to free-spectrum opportunities. But what kindof hardware might be required to implement these cognitive radios?

Because of their inherent frequency agility, cognitive radios’ RF circuits mustrespond over a wide variety of frequencies. Such frequency agility will require RFcircuits with broadband designs. In spite of this broad-banding requirement, cogni-tive radio components will be required to operate at the same level of performanceas their narrowband cousins. This is because each standard by itself is demanding interms of performance and cannot be compromised. Therefore, performance factorssuch as power output, noise figure (NF), linearity, and phase noise must be of thesame level of quality as is experienced with narrowband equipment, operating to agiven standard. In particular, frequency-generating equipment, such as VCOs, willbe required to cover a wide range of frequencies (perhaps an octave or more), whilemaintaining extremely low phase noise. This is a very tall order for varactor-tunedVCOs. However, magnetically tuned yittrium iron garnet (YIG)–tuned oscillators(YTOs) are capable of simultaneously tuning over a wide frequency range (morethan an octave), while maintaining extremely low phase noise. A YTO design exam-ple is discussed in Chapter 13. This YTO is capable of octave band tuning withphase noise typically 40 dB lower than is achievable with the best varactor-tunedVCO. Cognitive radio development will require similar creative approaches to all ofits component designs.

A possible alternative approach to a cognitive radio receiver is to use anall-digital architecture connecting the antenna directly to an extremely broadbandanalog digital converter (ADC). For example, in order to achieve eleven bits of pre-cision, a 6 GHz ADC would have to be clocked at 12 GHz and, most importantly,from a clock oscillator with RMS jitter on the order of 10 to 100 fs. Recent researchfindings suggest that this jitter requirement could be relaxed to 1.0 ps [12]. At pres-ent, the 10 fs requirement cannot be achieved with existing VCOs. However, theminiature YTO design discussed in Chapter 13 is capable of about 100 fs of jitter at12 GHz. Perhaps with device improvements and/or increased YIG resonator Qs,this class of oscillators could approach 10 fs performance. Using such techniques, itis conceivable that a cognitive radio could be designed whose only analog contentwould consist of an LNA and a PA. Such an all-digital radio would be truly softwaredefined in every sense of the word.

Sections 2.9 and 2.10 list frequency allocations and physical layer standards fora number of popular wireless standards for which RFICs represent an essentialenabling technology.

2.9 Spectrum Allocation in the United States (All Frequencies inMegahertz)

• Land mobile radio (LMR): 150, 450, 850• PCS: 1,850–1,990• Paging: 901–1,990• ISM (unlicensed): 800, 2,400, 5,700 (Part 15)• Multipoint Microwave Distribution System (MMDS): ~5,000

2.9 Spectrum Allocation in the United States (All Frequencies in Megahertz) 21

• LMDS: 16,000–30,000• 3G mobile transmit: 1,710–1,755• 3G base transmit: 2,110–2,155

2.10 Physical Layer Standards

• GSM (Global System Mobile, digital cellular)• Transmission time: 260 Kbps• TDMA structure: eight time slots per radio carrier• Time slot: 0.577 ms• Bits/time slot: 156• Frame interval: eight time slots = 4.615 ms• Number of radio carriers: 124• (935–960 MHz down link, 890–915 MHz up link)• Modulation: GMSK with BT = 0.3• Frequency hopping: slow hopping (217 hops/s)• Equalizer: equalization up to 16 µs time dispersion

• NA-TDMA (IS-136 digital cellular)• 800/1,900 MHz band• Channel bandwidth: 30 KHz• TDMA frame structure: 40 ms frame in six time slots• Channel data rates: first slot, half data rate; second, third, fifth, and sixth

slots, double data rate• CDMA (IS-95 digital cellular)

• Data rate: 9,600 bps• PN chip rate: 1.2288 Mcps• Code rate: one-third bits/code symbol• Code symbol repetition: two symbols/code symbol• Transmit duty cycle: 100 percent• Code symbol rate: 28,800 sps• Modulation: six code symbols/modulation symbols• Modulation symbol rate: 4,800 sps• Walsh chip rate: 307.20 kcps• Modulation symbol duration: 208.33 µs• PN chips/code symbol: 42.67 PN chip/code symbol• PN chips/modulation symbol: 256 PN chip/modulation symbol• PN chip/Walsh chip: 4 PN chip/Walsh chip

• MMDS• 2,500–2,700 MHz• 6 MHz channel bandwidth• Thirty-three channels• Range: 35 mi.• Tx power: 1–100W

22 Applications

• Bluetooth:• System type: frequency-hopping spread spectrum• Frequency: 2,402–2,480 MHz (ISM unlicensed band)• Modulation: GFSK, +/– 160 KHz frequency shift• Channels: 79• Frequency hopping: 1,600 hops/s• Power: Class 1: +20 dBm

Class 2: +4 dBmClass 3: 0 dBm

• Duplexing: TDD• Range: 10m• Voice: up to three synchronous voice channels of 64 Kbps

• ZigBee (IEEE 802.15.4) [13]• System type: DSSS (Direct sequence spread spectrum)• Data rate: 20–250 Kbps• 2,400 MHz, 868 MHz, 915 MHz• Range: 30m• Channels: 16• Power: 0 dBm• Nodes: 64,000 on one network• Sleep mode: 15 ms transition time• Beacon mode: periodic “wake up” to receive beacon from network control

mode• UWB (IEEE 802.15.3a)

• Subbands: 3,168–3,613 MHz; 3,616–4,224 MHz; 4,224–4,752 MHz• Transmission: OFDM• Modulation: QPSK• Data rate: 100–200 Mbps• Tx power: 93 mW• Rx power: 155 µW (at 110 Mbps)• Rx power: 169 µW (200 Mbps)• Range: 20m• Power density: less than –40 dBm in any 1 MHz band-pass window

• WiFi (IEEE 802.11a/b/g/n)• 802.11a: 5.15–5.35/5.47–5.725/5.725–5.875 GHz• 802.11b: 2.400–2.500 GHz• 802.11g: 2.400–2.500 GHz• 802.11n: 2.4 and 5 GHz bands• Maximum data rate, 802.11a: 54 Mbps• Maximum data rate, 802.11b: 11 Mbps• Maximum data rate, 802.11g: 54 Mbps• Maximum data rate, 802.11n: 540 Mbps• Range: 25–50m indoors, depending on version

2.10 Physical Layer Standards 23

• Modulation type: binary phase-shift keying (BPSK)/QPSK/OFDM, depend-ing on data rate

• Tx power: +15 dBm to +30 dBm, depending on version

References

[1] Bagheri, R., et al., “Software-Defined Radio Receiver: Dream to Reality,” IEEE Communi-cations Magazine, Vol. 44, 2006, pp. 111–118.

[2] Dixon, R., Spread Spectrum Systems with Commercial Application, New York: John Wileyand Sons, 1994.

[3] Lee, W., Wireless and Cellular Telecommunication, New York: McGraw-Hill, 2006.[4] DeRose, J., The Wireless Data Handbook, New York: John Wiley and Sons, 1999.[5] IEEE Standards Working Group Committee 802.11 (WiFi).[6] IEEE Standards Working Group Committee 802.15.1 (Bluetooth).[7] IEEE Standards Working Group Committee 802.15.3a (UWB).[8] IEEE Standards Working Group Committee 802.16 (WiMAX).[9] Vaughan-Nichols, S., “Achieving Wireless Broadband with WiMAX,” IEEE Comp., Vol.

37, No. 6, June 2004, pp. 10–13.[10] Klumperink, E., et al., “Polyphase Multipath Radio Circuits for Dynamic Spectrum

Access,” IEEE Communications Magazine, Vol. 45, No. 5, May 2007, pp. 104–111.[11] IEEE Standards Working Group Committee 802.22 (Cognitive Radio).[12] Hu, W., et al., “Dynamic Frequency Hopping Communities for Efficient IEEE 802.22 Oper-

ation,” IEEE Communications Magazine, Vol. 45, No. 5, May 2007, pp. 80–87.[13] IEEE Standards Working Group Committee 802.15.4 (ZigBee).

24 Applications

C H A P T E R 3

RFIC Architectures

3.1 I/Q Receivers

In today’s wireless communications industry, most systems make use of some formof phase modulation. Phase modulation has been found to be superior to otherforms of modulation in terms of supporting high data rates with superior sig-nal-to-noise ratios at high data rates. Given the paramount importance of phasemodulation, the RFIC field has had to find circuit techniques to receive and transmitvarious types of phase modulations.

These types of modulations can be compared and contrasted by consideringtheir performance relative to three important criteria:

1. Bit-error rate (BER) = error bits/total bits per unit time2. Spectral efficiency (compared to Shannon’s information capacity of a noisy

channel) [1]3. dc power efficiency (related to battery life)

Criterion 2 relates to perhaps the most important relationship in the mathemati-cal theory of information, developed by Claude Shannon [2]. Shannon’s equationfor the information capacity (maximum data rate) of any noisy channel is given by

C (bits per second) = BW log2(1 + S/N) (3.1)

where BW is the channel’s bandwidth in hertz. S/N is the channel’s signal-to-noiseratio expressed as a number. All real communications channels observe (3.1) as anupper bound on their performance.

When dealing with phase modulations of various kinds, it is very convenient toconsider the signal divided into two components, called the I (for in-phase) compo-nent and the Q (for quadrature-phase) component. The I component can be thoughtof as a cosine-like signal, and the Q component can be thought of as a sine-likesignal. A plot of various modulation phase states on a two-dimensional graph (withthe I component playing the role of the x axis and the Q component playing the roleof the y axis) is called a signal constellation diagram. Signal constellations are veryimportant tools for understanding phase-modulated digital signals because each ofthe phase states on the constellation diagram corresponds to a digital signal level. Ifthere are N phase states in a given modulation’s constellation, the amount of infor-mation carried by each clock cycle (i.e., each symbol) will be

Information per symbol = log2(N) (3.2)

25

The information rate associated with this form of modulation is

R (bits per second) = (1/ ) log2(N) (3.3)

where is one clock period.A simple example of phase modulation is binary phase-shift keying (BPSK). A

simple circuit for generating BPSK is shown in Figure 3.1. There are two generatorsin Figure 3.1: the first is Acos( 1t), and the second is –Acos( 1t). An SP2T switch,which is activated by the data stream, switches back and forth between the two gen-erators. We will associate a digital 1 with Acos( 1t) and a digital 0 with –Acos( 1t).The only difference between a digital 1 and a digital 0 is a 180° phase shift of the sig-nal. Figure 3.2 shows the constellation diagram for a BPSK signal. Both signal stateslie along the I axis. With this type of modulation, there are no phase states lyingalong the Q axis. The signal is simply shifted back and forth between the Acos( 1t)state and the –Acos( 1t), creating a digital 1 or a digital 0 within each clock period.Since there are two digital choices (N = 2) with BPSK modulation, the data per sym-bol (one clock period) is equal to log2(2) = 1 bit.

26 RFIC Architectures

Figure 3.1 An idealized generator of BPSK phase modulation.

Figure 3.2 A constellation diagram of BPSK modulation.

If significant phase noise exists in a system using BPSK modulation, the twophase states change from points at A and –A to noise balls centered around thepoints A and –A. If these noise balls become large enough to reach all the way to theQ axis, an ambiguity develops between what is a digital 1 and what is a digital 0.When this situation develops, significant bit errors may occur. Therefore, in thiscase the Q axis becomes what is called a decision boundary. Once the phase-noiseballs associated with each of the phase states reaches the decision boundary, theBER increases significantly. This situation must be avoided by maintaining a highsignal-to-noise ratio within the radio system and maintaining low phase noise in allsignal sources.

BPSK signals can also be generated by using the circuit shown in Figure 3.3. Inthe case of this circuit, a mixer is used to enable the data input to modulate a localoscillator signal. The data is cast into bipolar form so that a digital 1 becomes 1Vand a digital 0 becomes –1V. Since the mixer acts as a mathematical multiplier, the1V data levels produce an output signal of A, and the –1V data levels produce anoutput signal of –A. This process is an exact duplication of how BPSK modulationwas produced by the circuit shown in Figure 3.1.

Mixers are often used as both modulators and receiving downconverters inphase-modulated systems. In Figure 3.4, we see how two mixers can be combinedwith a serial-to-parallel data converter to generate another type of phase modula-tion called quadrature phase-shift keying (QPSK). The data stream is broken up intotwo parallel components, which are used to drive separate mixers. The first mixer isdriven by an LO signal, which is cosinelike in terms of its phase. The second mixer isdriven by an LO signal, which is sinelike in terms of its phase relationship to the firstLO signal. As before, the cosinelike LO signal produces an output from the firstmixer, which has two phase states, A and –A. The second sinelike LO signal pro-duces an output from the second mixer, which has two phase states, +jA and –jA. Bycombining these four possibilities, the final four QPSK phase states, A+jA, –A+jA,–A–jA, and A–jA, are arrived at, as shown in the constellation diagram in Figure3.5. Since the number of phase states is now four instead of two, as in the case ofBPSK, the bits per clock period associated with QPSK is log2(4) = 2 bits. This meansthat for the same clock period, the information rate has doubled. Another way torun QPSK is to divide the clock rate by two, which improves spectral efficiency byreducing the spectra’s width by a factor of two while preserving the same data rateassociated with BPSK modulation. Either way you look at it, QPSK is a 2:1improvement relative to BPSK.

3.1 I/Q Receivers 27

Figure 3.3 An analog multiplying mixer may act as a BPSK modulator.

Next, we turn our attention to the reception and detection of phase-modulatedsignals. A very natural way to accomplish this task is to design a receiver that has anatural ability to receive the in-phase (I) component of the received signal separatelyfrom the quadrature-phase (Q) component of the signal. This task is accomplishedin the following way: a mixer is used as a downconverter and takes the signal at RFfrequencies, mixing it with an LO signal to produce an IF frequency signal suffi-ciently low in frequency that it can be converted into digital form by an ADC dataconverter. The phase of the LO signal holds the key to whether this device willdownconvert the I component of the incoming signal or the Q component of theincoming signal. If the LO signal is cosinelike, the I component will bedownconverted. However, if the LO signal is sinelike (i.e., a cosinelike signal thathas been advanced by 90º in phase), the Q component of the signal will bedownconverted. A block diagram of this I/Q downconverter is shown in Figure 3.6.The mixers are often of the Gilbert cell type (see Chapter 11). Both the I and Q out-

28 RFIC Architectures

Figure 3.5 A constellation diagram of QPSK modulation.

Figure 3.4 A block diagram of a QPSK modulator.

puts will be filtered before further amplification. In high-IF-frequency systems, thisfilter will most likely be an off-chip band-pass filter. In low- (or zero) IF-frequencysystems, this filter will most likely be an on-chip low-pass filter.

A key element in making an I/Q mixer work properly is generating the 90ºphase shift between the two LO signals. There are several ways to achieve this goal(see Chapter 6). The most straightforward way to accomplish this is to use a circuitcalled a polyphase network. This network has a single input but two outputs, one ofwhich is phase-shifted relative to the other input by exactly 90º. A circuit schematicdiagram for a polyphase network is shown in Figure 3.7. A simple single-section,low- or high-pass filter of the type discussed in Chapter 6 may also be used to gener-ate a 90º phase shift between two LO signals in an I/Q downconverting mixer.Other possibilities include the use of a quadrature VCO (see Chapter 13), whosearchitecture is shown in Figure 3.8, and the use of a digital frequency divider circuit,which naturally can produce several outputs in various phase configurations byusing digital techniques. Whatever technique is employed, creating a 90º phase shift

3.1 I/Q Receivers 29

Figure 3.6 A block diagram of an I/Q demodulator.

Figure 3.7 A schematic diagram of a polyphase circuit useful for shifting the LO signal by 90º inI/Q modulator and demodulator applications.

between LO signals of the same amplitude and frequency is an absolute necessity indesigning I/Q downconverters.

The mixers themselves are likely to be Gilbert cell mixers because this class ofmixers has high natural isolation, high conversion gain, and relatively low LOpower and dc power requirements [3]. See Chapter 11 for more details on Gilbertcell mixers. An important design criterion for this class of mixers is the necessity forboth sides of the mixer to be absolutely balanced. If any imbalance occurs, the per-formance of the mixer in terms of isolation, gain, linearity, and noise figure will suf-fer greatly. For this reason, it is important when laying out a Gilbert cell mixer totake special care to ensure that the two sides of the mixer are truly mirror images ofeach other. Even small amounts of imbalance (perhaps as physically small as a tinypiece of metal on one side of the mixer that is not reflected on the other side of themixer) will cause significant loss in performance, especially performance relative tothe true reproduction of I and Q information, which is essential to the high-qualityreception of phase-modulated digital signals. This ability of the I/Q receiver to notdistort the digital phase information is measured by a parameter called error vectormagnitude (EVM). EVM combines the effects of mixer nonidealness and LO phasenoise into one parameter that measures a receiver’s ability to reproduce the informa-tion contained in a digital phase-modulated signal without introducing significantdistortion causing bit errors. Only by combining a very low-noise-figure LNA withan extremely well-balanced pair of Gilbert cell mixers and a low-phase-noise LOsignal split into an in-phase component and a quadrature-phase component(phase-shifted by 90º) can low EVM and low BER be achieved for any or type ofphase modulation.

3.2 I/Q Modulators

I/Q modulators, which are used in transmitters, are the dual of the I/Qdownconverting mixer, that are used in receivers. The I/Q modulator in fact simplyturns the functions around and produces an output signal at RF frequencies basedon an LO input (also at RF frequencies) and a baseband input containing the modu-

30 RFIC Architectures

Figure 3.8 The block diagram of a quadrature phase VCO.

lating information in I/Q form. The architecture of an I/Q modulator is shown inFigure 3.9(a) and is easily recognized as an I/Q downconverting mixer runningbackwards. A second version of the I/Q modulator is shown in Figure 3.9(b). Thisversion of the I/Q modulator makes use of a frequency-translating upconvertingmixer to prevent PA leakage [as shown in Figure 3.9(a)] from pulling the frequencyof the VCO. A very interesting feature of an I/Q modulator is that, due to theextremely high LO to output isolation of a Gilbert cell mixer, very little, if any, LO

3.2 I/Q Modulators 31

Figure 3.9(a) The block diagram of a direct-conversion transmitter showing PA-to-VCO leakagepaths.

Figure 3.9(b) The block diagram of a double-conversion transmitter, which solves the PA-to-VCOleakage problem.

signal is present at the mixer’s output. This means properly designed I/Q modulatorsproduce output only in response to modulation inputs. These inputs come in theform of an I signal line and a Q signal line, which are connected to the two modula-tion mixers in the same way as the serial data inputs are connected to the two mixersin the QPSK generator shown in Figure 3.4. In fact, the I/Q modulator is simply ageneralization of the QPSK generator discussed previously. However, instead ofbeing modulated with only digital 1’s and digital 0’s, as was the case in the QPSKgenerator, the I/Q modulator is capable of being modulated with an analog signal onboth its I input and its Q input. This generalized modulation input allows the I/Qmodulator to cover a wide variety of phase and amplitude states. In the simplestcase, it can produce BPSK if no Q input is applied and the I input is toggled by thedata stream between +A and –A. Next, QPSK is produced if both the I and Q inputsare toggled by their respective streams by +A and –A (in exactly the same way as theQPSK generator in Figure 3.4 operates). However, since the modulator is capable ofresponding to a wide range of I and Q input signals, it is capable in general of pro-ducing a wide variety of what is called N-QAM modulations (QAM stands for“quadrature amplitude modulation”). The modulator’s linearity is an importantissue in determining signal integrity. Like the receiving I/Q downconverter, phaseerrors resulting from the nonlinear responses of the mixers, or phase noise associ-ated with the LO signal, will result in bit errors. Performance metrics such as EVM,I/Q phase imbalance, and various signal-to-noise ratios are used in evaluating thequality of an I/Q modulator. As the modulation becomes progressively more com-plex (i.e., N increases in the N-QAM signal constellation), the decision boundariesbetween phase states get closer together, making the overall system BER more sensi-tive to smaller values of EVM and signal-to-noise ratio. This is the inevitable pricethat must be paid for obtaining the higher data rates associated with higher-orderphase modulations.

3.3 Nonzero IF Receivers

Superheterodyne receivers have been in use since the 1920s. In many ways, theyremain the gold standard of receiver technology for a number of important reasons.To understand the performance trade-offs encountered with nonzero IF receivers(i.e., superheterodyne receivers) and receivers in general, we must first discuss theprimary goals of all radio receivers. Since the early days of radio, it has been widelyrecognized that any radio receiver must have two important attributes: the first issensitivity, and the second is selectivity. Sensitivity refers to a receiver’s ability todetect weak signals and is closely linked to the concept of signal-to-noise ratio. It isfor reasons of sensitivity that most receiver architectures begin with a low-noiseamplifier (LNA) connected between the receiving antenna and the rest of thereceiver (see Chapter 8). The LNA’s purpose is to build up the weak signals comingfrom the antenna to the point where they may be effectively processed by the rest ofthe receiver, while contributing little if any noise to the amplification process. Agood LNA will have very little effect on the signal-to-noise ratio of received signals;it will simply amplify their levels while adding little if any noise on its own. Thedesign of a good LNA is the key ingredient in attaining good receiver sensitivity.

32 RFIC Architectures

From this point of view, receiver sensitivity is the overall goal that is most easilyachieved. Selectivity is not so easily achieved.

The second primary goal of all receivers, selectivity, is defined as a receiver’sability to distinguish between received signals and to pick out the desired signal andreject all others. A highly selective receiver will have the ability to detect the infor-mation carried by only one signal, which it focuses on to the exclusion of all othersignals. In reality, this is a very tall order. Selectivity is difficult to obtain because ofinterference and interferers. Interference is defined as any received signal, otherthan the desired signal, that has an ability to degrade a receiver’s ability to receivethe intended signal. Some interferers may be very strong relative to the desired sig-nal. Some interferers may simultaneously be very close in frequency to the desiredsignal. Some interferers may be very strong and very close in frequency to thedesired signal. All of these situations pose great challenges for any receiver. In gen-eral, there are two circuit characteristics that the receiver’s components must havein order to reject interferers: the first is highly effective filtering, and the second ishigh linearity, even at large input signal levels. Figure 3.10 shows the heart of asuperheterodyne receiver, that is a downconverting mixer preceded by an“image-rejection” filter.

Consider filtering first. Filtering is the first line of defense against interferenceand interferers. Since the early days of radio, improvements in filtering techniqueswent hand in hand with the ability of receivers to distinguish between radio stationsin an ever increasingly crowded broadcast radio spectrum. In general, it is easier tobuild high-performance filters at low frequencies than at high frequencies due toconstruction techniques and the effects of parasitic elements at high frequencies. Forthis reason, as radio advanced to ever higher frequencies, it became more difficult toachieve the kind of filter selectivity that is achievable at lower frequencies. For thesereasons and others, which we will discuss shortly, Erwin Armstrong (1890–1954)[4] invented the superheterodyne receiver in 1919, during his World War I militaryresearch. Armstrong’s new receiver used the then revolutionary technique ofdownconverting a high-frequency input signal to a much lower frequency, calledthe IF frequency (i.e., intermediate frequency). To make this technique a reality,Armstrong pioneered the use of mixers and local oscillators to enable thedownconversion process. In return for the additional circuit complication, he got

3.3 Nonzero IF Receivers 33

Figure 3.10 The block diagram of a downconverting receiver mixer together with animage-rejecting band-pass filter.

a receiver whose major filter selectivity was achieved at a much lower frequencythan the received frequency, meaning that inexpensive high-performance filterscould be used to determine the selectivity of receivers tuned to very high-frequencysignals (such as the newly opened FM band). Armstrong’s superheterodyne receivershad razor-sharp selectivity even at very high frequencies, which proved revolution-ary for receiver technology.

There are two other advantages to using the downconversion process associatedwith the superheterodyne receiver. First, it provides most of the receiver’s gain at theIF frequency, after frequency conversion, where amplifiers are small, cheap, andperform very well, as opposed to amplifiers at the RF frequency, which may be largeand expensive and perform less well. The other advantage comes about in the detec-tor and the audio amplifier, which follows the detector, where the information con-tained in the modulation is removed from the carrier signal and amplified beforedriving a speaker. Before superheterodyne techniques became widespread, thisdetection was done directly at the RF frequency, and a great deal of audio gain wasapplied after the detector to build up the signal strength to drive the speaker. Prior tosuperheterodyne, the detector was operating at relatively low signals, requiring agreat deal of audio gain to build signal strength. Such an architecture is highly vul-nerable to 1/f noise in either the detector or the audio amplifiers. Superheterodynetechniques solve this problem by using a great deal of gain at the IF frequency tobuild the signal up so that when it reaches the detector, the signal-to-noise ratio isalready very high, and 1/f noise effects do not impact the signal. It should be pointedout that very little 1/f noise is generated in the IF amplifiers because these amplifiersare operating at sufficiently high frequencies to avoid most of the 1/f noise, which isby nature concentrated at much lower frequencies.

Figure 3.11 shows the complete block diagram of a single-conversion superhet-erodyne receiver [5]. Understanding the behavior of the band-pass filters is critical tounderstanding the operation of the whole receiver. The first band-pass filter (beforethe LNA) is the first line of defense against interferers that may be located outside of,but close to, the band of interest. For this reason, a highly selective band-pass filterin the receiver’s front end will help greatly with removing out-of-band interference.If this interference is not removed by filtering, it is very possible that two stronginterfering signals could be intermodulated within the LNA to produce new signalsthat could be located in the band of interest. This front-end filter is critical to achiev-ing high selectivity in any receiver design.

A second band-pass filter follows the LNA. This filter is called the image filter.Referring to Figure 3.12, it is possible in a downconverting receiver to encounter a

34 RFIC Architectures

Figure 3.11 The block diagram of a single-conversion superheterodyne receiver.

situation called the image problem. Assume the LO signal is higher in frequencythan the RF input signal (by the IF frequency). Unfortunately, the chance appear-ance of an interfering signal at a frequency equal to the LO frequency plus the IF fre-quency will also deliver a signal at the same IF output frequency as the signal thatwe intend to receive. Such an interfering signal is called an image signal, and its fre-quency (Flo + Fif) is called the image frequency. To guard against interference fromimage frequency signals, it is necessary to use a second band-pass filter to providesufficient rejection at the image frequency so that any interfering signal appearing atthat frequency will be suppressed to a large enough degree that it will be renderedundetectable. To accomplish the filtering of the image frequency, we encounter aproblem. If the IF frequency is very high, it is not difficult to filter the image with asimple band-pass filter, as shown in Figure 3.13. However, the requirement of ahigh IF frequency means that the band-pass filters in the receiver’s IF section mustoperate at very high frequencies, which means these filters will require difficult andexpensive designs. However, consider the alternative. The IF frequency can bereduced to frequencies where the IF filters become easy to design, and even inexpen-

3.3 Nonzero IF Receivers 35

Figure 3.12 The spectrum of a downconverting receiving mixer showing the frequency compo-nents associated with frequency conversion and with the image problem.

Figure 3.13 A wideband (i.e., low Q) image-rejection filter is used with receivers that operatewith a high IF frequency.

sive filters perform very well. But the burden is now placed on the image filterbecause, as shown in Figure 3.14, the image frequency, the LO frequency, and theRF input frequency are now very close together. This means that in order to be trulyeffective, the image filter must be very sharp so that it can pass the RF input signalwith little or no attenuation but still have adequate rejection at the now close byimage frequency.

This no-win filter dilemma led receiver designers to an architectural conceptcalled the double-conversion superheterodyne receiver. A block diagram of the dou-ble-conversion receiver is shown in Figure 3.15. With the double-conversion super-heterodyne, it is possible to “have our cake and eat it too.” With this architecture,there are two frequency downconversions and two IF frequencies. This means it ispossible to choose the first IF frequency to be high in order to simplify the design ofthe image filter and, at the same time, to choose the second IF frequency to be low inorder to allow the channel-select filter to be simple, inexpensive, and effective as theultimate determiner of the channel bandwidth and interference rejection.

The double-conversion superheterodyne receiver is truly the gold standard of allcommunications receiver architectures, and it has remained in this enviable positionfor many years. I/Q demodulation is done at the second IF frequency, taking advan-tage of the razor-sharp IF filters to reject interfering signals. However, there are cer-tain practical problems with a double-conversion superheterodyne architecture inRFIC applications. The basic problem is the requirement for too many off-chip com-

36 RFIC Architectures

Figure 3.14 A narrowband (i.e., high Q) image-rejection filter is used with receivers that operatewith a low IF frequency.

Figure 3.15 The block diagram of a double-conversion superheterodyne receiver. This architecture solvesthe high-IF-versus-low-IF-frequency dilemma that must be confronted when choosing an image-rejectingband-pass filter for a single-conversion superheterodyne receiver.

ponents. Both the input band-pass filter and the image filter are too selective (highQ) to be realized on-chip. Therefore, they must be treated as off-chip componentsand attached to the PCB next to the RFIC chip. Also, the requirement for two IF fre-quencies means the necessity for two IF band-pass filters, as well as twodownconverting mixers and two local oscillators. Some of this circuitry can belocated on-chip, but much of it (like both of the IF filters) may be more effectivelylocated off-chip. Also, two different frequency reference oscillators may be neces-sary for the phase-locked loops composing the two local oscillators. These referenceoscillators will be located off-chip, adding to the collection of off-chip components.Because of the large number of off-chip components needed to support a dou-ble-conversion superheterodyne architecture, designers of RFIC circuits are lookingfor simpler alternative architectures capable of reducing the required number ofoff-chip components. The answer to this search is the so-called zero IF receiver.

3.4 Zero IF Receivers

The basic architecture of a zero IF receiver is shown in Figure 3.16. Zero IF receiversare a kind of superheterodyne receiver in which the IF frequency has been reducedto zero. This is done in a very clever way by combining an I/Q downconverter with afront-end LNA and band-pass filter [6]. By using this technique, the I/Qdownconverter is both a frequency-converting device from RF to base band, as wellas a demodulating device that resolves a modulated signal into its in-phase andquadrature-phase components [7]. By using zero IF techniques, the IF filters take theform of low-pass filters (which filter base band) rather than the customaryband-pass filters used in nonzero IF receivers. Also, only one frequencydownconverter is required, and because the RF and the LO frequencies are thesame, there is no image frequency, eliminating the need for an image filter. Theseconsiderations greatly simplify the architecture of a zero IF receiver relative to non-

3.4 Zero IF Receivers 37

Figure 3.16 The block diagram of a zero IF, direct-conversion receiver.

zero IF receivers. An additional simplification is in the LO. Since the LO frequency isthe same as the RF input frequency, in most cases where there is a common RFfrequency for both transmitting and receiving, the LO signal can be used for bothtransmitting and receiving. This consideration alone greatly simplifies the architec-ture of a combined receiver and transmitter, called a transceiver. With all of theseadvantages, why are any receivers built with a nonzero IF architecture? The answeris that to gain all of the advantages of a zero IF receiver, it is necessary to live with itsshort, but significant, list of shortcomings.

The leading disadvantage of a zero IF receiver is the problem of dc offsets. Thisis a particularly difficult problem to live with because of all the gain available at dcin the variable gain amplifiers at the receiver’s back end. These relativelylow-frequency amplifiers are responsible for most of the receiver’s overall gain.Most receivers must have 80 to 90 dB gain between the antenna and the detector toeffectively receive the extremely weak signals that reach the antenna in any realisticwireless link. If the LNA has 30 dB gain (to overcome the mixer’s second-stage con-tribution to noise figure), and the mixer has 10 dB gain, that is only 40 dB of arequired 80 to 90 dB total. This means that the variable gain amplifier (VGA) mustcontribute a gain of 40 to 50 dB. This includes dc because, in effect, with this class ofreceiver, dc is the IF frequency. The high-frequency limit of the VGA is determinedby the low-pass filter (which plays the same role as the IF-band selecting filter in anonzero architecture). Ultimately, the upper frequency limit of both the low-pass fil-ter and the VGA are determined by the modulation information rate of the datapassing through the receiver. For instance, in a WiFi receiver, the filter’s upper fre-quency is about 11 MHz, corresponding to a data rate of about 22 Mbps with QPSKmodulation (two bits per symbol). Should a significant (or, for that matter, insignifi-cant) dc imbalance develop within the mixer, the VGA will immediately go to therail and become saturated by this dc offset. It does not take much input dc offsetto saturate a 50 dB gain dc-coupled amplifier. Let’s examine the root causes of dcoffset.

One of the causes of dc offset is LO leakage from the mixer’s input port. Suchleakage is also a problem from a different perspective: if this leakage reaches theantenna, the receiver can be acting as a transmitter by radiating the LO signal. SuchLO radiation can act as an interfering signal to other receivers located close by.However, this LO radiation is partially reflected by the antenna and reenters theLNA input, where it experiences gain before entering the mixer’s input with a differ-ent phase relationship than the LO signal, which is being supplied by the LO circuitsto the mixer’s LO port. Since the LO leakage has a unique phase relationship (whichmay even depend on objects close by the antenna), it mixes with the LO in unpre-dictable ways. Since both the leakage signal and the intentional LO are at the samefrequency, the result of their interaction can only be a dc output from the mixer. Ineffect, the mixer is functioning as a phase detector, measuring the phase relationshipof the leakage to the intended LO’s phase. The unpredictable dc offsets produced bythis LO leakage can potentially send the VGA into saturation and severely disablethe receiver. Figure 3.17(a) gives a block diagram presentation of how LO leakageaffects the performance of a zero IF receiver.

Before we present solutions to the dc-offset problem, let us consider a secondsource of dc offsets. If strong in band interfering signals are amplified by the LNA

38 RFIC Architectures

and enter the mixer’s input, these interfering signals, if they are strong enough, canact as spurious LO signals as they are transferred to the mixer’s LO port as a resultof imperfect R to L isolation. In effect, these strong spurious signals (they must beclose enough in frequency to be passed by the front-end band-pass filter) serve asself-mixing signals that are downconverted to dc by the mixer. As with LOleakage, the strong interferer becomes the cause of unpredictable dc offsets at themixer’s output with the potential to send the VGA into saturation, as shown inFigure 3.17(b). VGA saturation is a very serious situation because of gain saturation

3.4 Zero IF Receivers 39

Figure 3.17(a) LO leakage paths associated with a direct-conversion receiver may cause dc offsets at thereceiver’s output and LO radiation from the system’s antenna.

Figure 3.17(b) Self-mixing strong interfering signals may also cause dc offsets at the receiver’s output.

and the potential for intermodulation to create serious limitations on receiverperformance.

There are two possible solutions to the dc-offset problems in zero IF receivers.The first solution to the dc-offset problem is simply to ac-couple the outputs of thelow-pass filters to the VGAs with series capacitors, as shown in Figure 3.18. Thissimple technique completely eliminates the dc offsets and solves the problem. How-ever, this simple solution comes with its own penalties, the most important being theloss of signal-to-noise ratio because the signal energy contained in each symbol iseffectively being high-pass-filtered by the capacitors. Also, to keep loss of sig-nal-to-noise ratio to a minimum, it may be necessary to locate the capacitorsoff-chip as surface-mounted capacitor chips, in order to accomodate their values.

A second technique for eliminating dc offsets is to use feedback around the VGAto cancel out any dc-offset voltages that may develop. This technique is demandingin terms of circuit design; however, it has the advantage of being entirely on-chipand does not contribute to any loss of signal-to-noise ratio. However, it must beemphasized that in order to make such a feedback loop work, the designer must takespecial care to ensure that the loop is stable over a wide range of frequencies.Insuring stability can be a difficult task, considering that the VGA’s gain is between40 and 50 dB and its bandwidth is dc to perhaps 100 MHz.

The effectiveness of a zero IF receiver is measured by two metrics called sig-nal-to-noise (S/N) and error vector magnitude (EVM) [8]. The phase-modulated sig-nal passing through the receiver is changed from its original form to a modified formthat is observed in the output of the receiver. The modified form is a result of LOphase noise, which tends to draw phase state points into arcs, and phasenonlinearity, which offsets the relative position of the phase state vectors. To func-tion in a fully nondistorting way and to assure the receiver’s user of a very low

40 RFIC Architectures

Figure 3.18 ac coupling of a direct-conversion receiver’s output solves the dc-offset problem at the priceof reducing the received signal’s signal-to-noise ratio.

bit-error rate, it is necessary that the EVM specification be less than 15 to 20 per-cent. To realize this goal, a zero IF receiver must have extremely low LO phasenoise, very accurate 90º offset of the LO signal between mixer 1 and mixer 2, andvery low phase nonlinearity throughout.

These requirements can pose a difficult challenge to the RFIC designer; how-ever, the zero IF receiver has the powerful advantage of requiring few, if any,off-chip components. About the only components that are certain to be off-chip arethe front-end band-pass filter and the dc-blocking capacitors, which prevent dc off-sets from saturating the VGA. If feedback techniques are used in the VGA to cancelthe dc offsets, the off-chip capacitors are eliminated. This reduces the set of off-chipcomponents to only the front-end band-pass filter. Even though the dou-ble-conversion superheterodyne receiver is hard to beat in terms of performance, itrequires a great many off-chip components, which are serious cost and size drivers.Because of all of these considerations, the wireless industry has embraced the zero IFarchitecture over the last decade, and it has become the de facto standard for mostRFICs used in today’s wireless applications.

3.5 Differential versus Single-Ended Topologies

Gilbert cell mixers (see Chapter 11) form the heart of both receivers and transmit-ters in the wireless industry. Because these mixers have fully differential inputs andoutputs, it is very tempting to configure all of the components connected to Gilbertcell mixers as fully differential. This means that LNAs, buffer amplifiers, and filtersmust also be differential if an on-chip conversion from single-ended to differential isto be avoided. In fact, if all of the on-chip circuits are in differential form, the con-version to single-ended need never be done on-chip but can be put off until a signalinput or output allows the use of an off-chip balun, which can be mounted on thesame circuit board that the RFIC is connected to. In fact, it makes no sense to beconstantly making differential-to-single conversions on-chip. Since the Gilbert cellmixers are naturally differential, it makes a great deal of sense to remain in a com-pletely differential format on-chip, converting to single-ended when necessary,using off-chip baluns.

A second advantage to using all differential topologies with the on-chip compo-nents is the avoidance of common mode problems. If grounds are for any reasonincomplete or inconsistent, no common mode problem will result with a differentialtopology. However, if some of the on-chip circuits are single-ended, it is possiblethat grounding problems may affect the LO leakage paths associated with adirect-conversion receiver and may cause dc offsets at the receiver’s output and LOradiation from the system’s antenna. Problems such as these can be difficult tounderstand and troubleshoot.

References

[1] Shannon, C., and Weaver, W., A Mathematical Theory of Communications, Urbana: Uni-versity of Illinois Press, 1949.

3.5 Differential versus Single-Ended Topologies 41

[2] Shannon, C., “A Mathematical Theory of Communications,” Bell Sys. Technical J., Vol. 27,July 1948, pp. 379–423, and October 1948, pp. 623–656.

[3] Armstrong, E., “Some Recent Developments in the Audion Receiver,” Proc. IRE, Vol. 3,1915, pp. 215–247.

[4] Maas, S., Microwave Mixers, Boston: Artech House, 1986.[5] Razavi, B., RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.[6] Lee, T., The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge: Cam-

bridge University Press, 1998.[7] Tiebout, M., “Low Power, Low Phase Noise Differential Quadrature VCO in CMOS,”

IEEE J. of Solid State Circuits, Vol. 36, July 2001, pp. 1018–1024.[8] Ristenbatt, M., “Alternatives in Digital Communications,” Proc. IEEE, Vol. 61, June 1973.

42 RFIC Architectures

C H A P T E R 4

InGaP/GaAs HBT Fabrication Technology

4.1 Transistor Structures

In order to fabricate RFIC circuits, it is necessary to adhere to a strict set of designrules and device models supplied to the designer by the foundry. In the case ofInGaP/GaAs HBT technology, the design rules give the designer a complete set oflayout rules, which in effect tell what physical limitations have been encountered bythe fabrication equipment at the foundry’s wafer-fabrication facility. For example,a design rule requiring a minimum line width for a particular metal layer informsthe designer of the foundry’s photolithographic equipment’s resolution limits forthat particular layer.

Design rules assure the designer that his or her RFIC design can be fabricated tothe dimensions and tolerances required by the design. To be sure that the designinformation is conveyed to the foundry in the most unambiguous way, it is impor-tant that both foundries and designers agree upon a common set of units to assureclear communications of design data. The following is a set of units universallyaccepted by GaAs HBT foundries (and foundries in most other technologies).

1. Spatial dimensions are measured in microns or µm (1E–6m).2. The smallest grid used in computer-aided design (CAD) layout tools is

0.5 µm.3. Capacitance is measured in either pF or fF.4. Inductance is measured in nH.5. Resistance is measured in ohms.

Two distinct IC structures are fabricated by the foundry. The first set of struc-tures involves all of the necessary layers for the fabrication of transistors. The sec-ond set of structures includes all of the metal and dielectric layers that make up themetal interconnects, resistors, capacitors, and inductors.

With regard to transistor fabrication, every foundry is unique in its approach totransistor layout and fabrication. Some foundries will allow the designer completecontrol over the geometry of the transistor’s design, while other foundries simplysupply what, in effect, is an appliqué containing all of the necessary layers to fabri-cate a single-emitter-finger transistor. In the case of the appliqué transistor, thedesigner is free to make larger transistors by connecting a number of these appliqué“unit cell” transistors in parallel. This is a very common approach, and some found-ries simply provide the designer with a “dummy” unit cell, with all of its inputs andoutput at the proper locations. In this case, at the time of mask making, the foundry

43

will read into each dummy cell all of the layers needed to fabricate the unit celltransistor that resides in the dummy cell.

Let us go back to the beginning of the wafer-fabrication process to see how thetransistors are processed. The first step is called deposition of the epitaxial layer onthe top surface of the wafer. The word “epitaxial” is derived from the Latin rootwords “epidermis,” meaning the outer layer of skin, and “taxial,” referring to crys-tals. In effect, “epitaxial” means “the skin of the crystal,” which is exactly what it is.Only a very thin top surface of an epitaxial wafer is electrically conductive, but it isthese thin layers that completely determine the electrical characteristics of the tran-sistors that will be fabricated on the wafer. The wafer itself is semi-insulating, whichmeans its electrical conductivity is very low, in effect making it behave like an insula-tor, such as glass or quartz. On top of this insulating substrate, several (five) conduc-tive layers are deposited, as shown in Figure 4.1. The bottom layer is an N+ GaAssubcollector, the next is an N GaAs collector, the next is a P+ GaAs base, the next isa N InGaP emitter, and the topmost layer is a N+ GaAs emitter contact. Because ofthe presence of the InGaP emitter layer, the transistors formed by this process areknown as heterojunction bipolar transistors (HBTs). HBTs have superior electricalcharacteristics at high frequencies, making them ideal devices for RFICs operating atthe frequencies of wireless communications.

The initial photolithographic wafer fabrication of GaAs HBT RFIC circuits con-sists of patterning and fabricating the HBT devices themselves. This process involvessuccessive steps involving selective etching of the wafer’s epitaxial layers. Upon etch-ing these layers into a mesa structure with collector, base, and emitter structuresformed with the proper length and width dimensions, a metal contact layer is pat-terned and deposited on top of the corresponding semiconductor layer. The finishedtransistor structure is shown in Figure 4.2, including all contact metals. Foundriessupply designers with layout “applicas,” which include all of the necessary layers forpatterning and fabricating single-emitter-finger unit cell transistors. At the periph-ery of each unit cell transistor are first-metal (M1) pads, where connections to thegreater circuit must be made. Larger transistors are made by combining many unitcell transistors in order to create a device properly sized with the number of emitterfingers called for by the requirements of the design.

Once all transistors and diodes (devices that use only the base-to-emitterjunction of a transistor, with the collector and base terminals hardwired together)have been fabricated, any remaining epitaxial layer material is stripped off, exposing

44 InGaP/GaAs HBT Fabrication Technology

N+ EMITTER CONTACT

N+ GaAs SUB COLLECTORN GaAs COLLECTORP+ GaAs BASEN InGaP EMITTER

SUBSTRATE

S.I. GaAs

Figure 4.1 Cross section of a GaAs HBT wafer showing the various epitaxial layers associated withthe transistor’s structure.

the bare GaAs semi-insulting substrate in preparation for deposition of the metalsand insulators that will define all of the passive and interconnecting elements withinthe RFIC.

4.2 Device Models

InGaP/GaAs HBT devices make use of one of two possible device large-signal elec-trical models. Large-signal models make it possible for designers to literally simu-late all device and circuit performance parameters that can be measured in thelaboratory. The oldest of these models is the Gummel Poon model [1], and the morerecent model is the VBIC [2] model. The Gummel Poon model was originally devel-oped for use in single-element silicon bipolar devices. It is an excellent model and isused widely in bipolar circuit design for a wide variety of device and material tech-nologies, but it has a few shortcomings related to GaAs HBT devices. The first limi-tation of the Gummel Poon model is its lack of a way to account for the effects ofself-heating. In silicon devices, this is not a major factor because of the high thermalconductivity of silicon, but in GaAs it is a different story. GaAs devices experienceconsiderable self-heating as a direct result of this material’s low thermal conductiv-ity. This means a GaAs HBT transistor will experience significant temperature risewhen operating near its maximum power ratings. Such temperature rise will affectthe elements in the model’s equivalent circuit and, if not accounted for, may proveto be the cause of significant error when modeled circuits which are compared toexperimental measurements. A second shortcoming of the Gummel Poon model isits inability to model the electrical behavior of a transistor on the verge of avalanchebreakdown. Avalanche breakdown occurs when electrons and holes receive suffi-cient energy from the device’s internal electric fields to cause a chain reaction tooccur, releasing additional electrons and holes that add to a growing wave of excesscurrent. Left unchecked, this avalanching current will destroy the device in a phe-nomenon called breakdown. If breakdown is only approached on the peak of eachRF cycle, this phenomenon can serve as a waveform-modifying mechanism thatcontributes to the nonlinear behavior of an HBT device operating at large-signallevels. As with self-heating, breakdown phenomena are not accounted for in theGummel Poon model. The intent of the developers of the VBIC model was to correctthese deficiencies and to create a more accurate model for all types of GaAs HBTtransistors. A generic Gummel Poon model for a single-finger unit cell device with

4.2 Device Models 45

Figure 4.2 Cross section of an InGaP/GaAs heterojunction bipolar transistor.

an emitter measuring 2µm × 15µm is shown in Figures 4.3(a–c). A generic VBICmodel for a similar unit cell device is shown in Figures 4.4(a–c). Simulated DC IVcurves and small signal s-parameters for each model are shown in Figure 4.3(b,c)and Figure 4.4 (b,c). These generic device models are used to simulate many of thecircuits which are presented in the following chapters. The generic models describedevice behavior that is very similar to current foundry devices. Large transistors canbe conveniently sized in simulations either by paralleling a number of unit cells inthe simulator’s schematic diagram or by simply increasing the area (in steps of inte-ger numbers of emitter fingers) in the schematic symbol for the transistor, as shownfor ADS [3] schematic symbols given in Figure 4.5. These large-signal device modelsgive the designer all the information necessary to accurately model transistor behav-ior to simulate dc conditions, small-signal RF conditions, and large-signal RFconditions (including several measures of nonlinearity). The modeling of nonlineardevice behavior is extremely important in the design of PAs. The Gummel Poon andVBIC models both contain ways of modeling thermal noise and 1/f noise. The ambi-

46 InGaP/GaAs HBT Fabrication Technology

Figure 4.3 An ADS schematic diagram for generating the dc IV curves of a bipolar transistor using aGummel Poon device model.

Figure 4.3(a) A generic Gummel Poon large-signal scalable device model for a single unit cellHBT.

ent temperature can be specified, like any other variable in both models. This capa-bility makes it possible for a designer to check how a particular design will functionat temperature extremes. This vital capability, which is offered only by theselarge-signal device models, is critical to the design of LNAs and low-phase-noiseVCOs.

4.2 Device Models 47

Figure 4.3(b) Simulated dc IV curves for a single unit cell Gummel Poon HBT device model.

Figure 4.3(c) Single unit cell S-parameters simulated using the Gummel Poon HBT device model.

4.3 Passive Structures, Their Electrical Models, and LayoutDesign Rules

Once the transistors are patterned and fabricated, the process of patterning and fab-ricating the metal and dielectric layers, which define the RFIC’s passive devices andinterconnections, can begin. It is in this area that most of the elements associatedwith circuit design will be defined and fabricated. Figure 4.6 gives a cross-sectionalview of the sequence of metal and dielectric layers that define a typical InGaP/GaAsHBT RFIC structure. This picture is realistic but simplified. Each foundry has itsown process, which will represent some variation on the basic theme presented here.It is very important that the designer become intimately familiar with the foundry’sdesign rules and regard the material that follows as a typical, but simplified, general

48 InGaP/GaAs HBT Fabrication Technology

Figure 4.4 An ADS schematic diagram for generating the dc IV curves of a bipolar transistor using a VBICdevice model.

Figure 4.4(a) A generic VBIC large-signal scalable device model for a single unit cell HBT.

process for this technology. The design rule parameters presented in this book aretypical of many foundries but are not specific to any one foundry.

The fabrication layers, starting up from the semi-insulting GaAs substrate are:

1. Thin film resistor (TFR)2. Collector contact metal (CM): used in some processes as an alternate resistor

material and an adhesion layer under bonding pads, adding additionalmechanical strength

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules 49

Figure 4.4(b) Simulated dc IV curves for a single unit cell VBIC HBT device model.

Figure 4.4(c) Single unit cell S-parameters simulated using the VBIC HBT device model.

3. First metal (M1): used for interconnects, resistor and transistor contacts,inductors, and capacitor bottom plates

4. Nitride: a thin dielectric material forming capacitors5. Polyimide: a thick dielectric material providing low coupling capacitance

separation between the first metal and the second metal.6. Second metal (M2): used for overpass interconnects and capacitor top plates7. Scratch protection: passivating and protection dielectric material that coats

the entire chip

In addition to these metal and dielectric layers, there are also four vias associ-ated with this process that open holes in the dielectrics to allow metal to be depos-ited in the next process step to flow though the via in order to establish ametal-to-metal contact or to make a capacitor top plate. These three four are

1. Nitride via (NV) used in forming M1-to-M2 vias and bonding pads2. Polyimide via (PV) used in forming M1-to-M2 vias, bonding pads, and

capacitor tops

50 InGaP/GaAs HBT Fabrication Technology

Figure 4.5 Transistor model ADS schematic symbols.

Figure 4.6 The cross section of an InGaP/GaAs HBT wafer showing the metal and dielectric lay-ers, which are used to form circuit elements and interconnects.

3. Scratch protect via (SPV) to open holes in the scratch protect layer to formbonding pad contacts

4. Substrate via (SV), a metalized via opened from the chip’s backside andrunning through the substrate for the purpose of bring a ground contact upto the top side of the chip from the grounded back of the chip

By combining the deposited metal layers with the dielectric vias, we arrive at aset of layout levels that must be determined by the designer as the final layout step ofthe design process. It is important to realize that in the design process, the designerdefines the pattern of the metal layers, but the designer also defines the holes (vias)in a particular dielectric layers. If nothing appears in the artwork for a given dielec-tric via layer, this particular dielectric material will extend over the entire chip area,without holes or breaks. Figure 4.7 shows a list of the eight metal and dielectric vialayers that comprise an RFIC design in InGaP/GaAs technology. This list applys tothe building blocks of passive circuit elements only, and does not cover transistorfabrication, which is handled separately, as discussed above. The layer numbers andcolor choices are particular to a given CAD layout system and are in no way general.The designer is free to use his or her own choice of layer colors and layer numbers.The designer should set up the CAD system to use a set of colors that attract thedesigner’s eye quickly and provide the designer with unambiguous, quickly per-ceived layer information.

The foundry design rules will provide the designer with information about thethickness and resistivity of each metal and dielectric layer. Typical design rule infor-mation of this kind is shown in Figures 4.8 and 4.9. Figures 4.10 and 4.11 give theminimum metal and dielectric via widths and spacings. These parameters in effectspecify the maximum capability of the foundry’s process to pattern small structures.Using a narrower line than the minimum width specified in Figure 4.10 will risk abreak in the line. A closer line spacing than that specified in Figure 4.11 will risk ashort circuit between lines. Two items to note: the minimum diameter and spacingof substrate vias are based on mechanical problems that can occur if too many holesin the substrate are spaced too closely. Such a situation can weaken the substrateand possibly causing cracking. Also, the reference to donuts refers to a problem thatcan arise with the lift-off metal photolithography process, which is used to definelayers M1 and M2 [4]. If an unwanted piece of metal in an interior pattern (donuthole) is not connected to the greater body of metal that is to be removed by “liftingoff,” it could possibly be left behind to cause problems like short circuits. For safety

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules 51

Figure 4.7 A table of layer names and possible color assignments to be used with the layout tool.

reasons, it is always best to avoid donuts. If you inadvertently include a donut inyour design, the foundry will flag the problem in a design rule correction (DRC)report.

Next, we look at various circuit structures that can be patterned with thisprocess.

52 InGaP/GaAs HBT Fabrication Technology

Figure 4.8 A table of InGaP/GaAs process layer thickness.

Figure 4.9 A table of InGaP/GaAs process layer resistivity.

Figure 4.10 Design rules for InGaP/GaAs process minimum layer line widths.

Figure 4.11 Design rules for InGaP/GaAs process minimum layer line spacing.

4.3.1 Microstrip Lines

The first structure is a microstrip line [5], which is shown in cross section in Figures4.12(b) and Figure 4.13, and from the top in Figure 4.12(a). Microstrip transmis-sion lines can be formed with either M1 or M2. They are both equivalent in thisrespect because the dielectric layers between them are so thin compared to the sub-strate thickness that dominates the microstrip line’s dielectric thickness, as shown inFigure 4.14. All the designer need specify in the design of a microstrip line is itslength L and its width W. The electrical behavior of the microstrip line can be com-municated to a simulator, such as the Agilent ADS system, by entering the lineslength L and width W, along with entering the substrate and line thickness informa-tion in the simulator’s MSUB controller block. See Figure 4.15 for an example ofentering the microstrip line parameters into an ADS circuit schematic diagram. TheADS element for a microstrip line is MLIN. Microstrip lines may be an intentionalpart of a design, or they may be regarded as a parasitic effect resulting from thenecessity of connecting two points in an RFIC layout together with a metal line. Ineither case, these metal traces should be modeled as microstrip lines in all simulatormodels. This is especially true at high frequencies. At 900 GHz, short microstriplines may have little effect on electrical performance, but above 2.0 GHz, the effects,depending on line length and width, can become very significant.

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules 53

Figure 4.12(a) The electrically critical dimensions of any microstrip metal line.

Figure 4.12(b) Cross section of microstrip metal (either M1 or M2) interconnect lines.

Two microstrip lines running parallel to each other are called coupled linesbecause energy can be coupled from one line to the other if they are close enoughtogether. Coupled lines may cause unwanted cross talk to occur between uncon-nected portions of a circuit and, in most cases, should be avoided if possible. Ofcourse, this requirement is at odds with the general desire to reduce the overall chiparea for economic reasons. If a parallel run of either M1 or M2 is unavoidable in agiven design; as shown in Figure 4.16, it is necessary to include this parallel

54 InGaP/GaAs HBT Fabrication Technology

Figure 4.13 The layouts of microstrip interconnect metal lines using either M1 or M2.

Figure 4.14 A table of dielectric layer thickness.

Figure 4.15 An ADS schematic symbol for microstrip metal lines.

microstrip line section as a part of the simulation schematic. In ADS, the elementthat models parallel microstrip lines is MCLIN, which is shown in Figure 4.17.

4.3.2 TFR Resistors

Resistors are formed by using a combination of M1 (as a contact on both sides ofthe resistor trace) and thin film 50 ohms per square resistor (TFR) as the resistor ele-ment. The structure of a TFR resistor is shown in Figure 4.18. Notice that forproper contacting, M1 must overlap the TFR material by at least 2µm. The resultingresistor will have a dc resistance of

R = (L/W) 50 ohms (4.1)

The cross section of a TFR resistor is shown in Figure 4.19. If the resistor is to bea part of the high-frequency RF circuit, then its length and width will act as a para-sitic microstrip element, which must be modeled in simulation. Therefore, the com-plete model for a TFR resistor is a lumped-element resistor based on (4.1) in series

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules 55

Figure 4.16 The layouts of coupled microstrip interconnect metal lines using either M1 or M2.

Figure 4.17 An ADS schematic symbol for coupled microstrip metal lines.

with a microstrip line with the same length and width (L and W) that define theresistor. The simulator schematic for a TFR element is shown in Figure 4.20.

56 InGaP/GaAs HBT Fabrication Technology

Figure 4.18 The layout of a TFR.

Figure 4.19 The cross section of a thin film resistor.

Figure 4.20 Simulator model of a thin film resistor.

4.3.3 M1-to-M2 Vias

Interconnections between the M1 and M2 layers must be accomplished by anM1-to-M2 via. The layout details of the M1-to-M2 via are shown in Figure 4.21,and the via is shown in cross section in Figure 4.22. This via is formed by openingholes in both the polyimide dielectric and the nitride dielectric layers. Once theseholes are opened in the dielectric layers, while M2 is being deposited by sputtering,M2 metal will flow down through the holes and come into intimate electricalcontact with M1 at the bottom of the hole. All M1-to-M2 connections must beaccomplished by using an M1-to-M2 via.

4.3.4 MIM Capacitors

The layout of an MIM capacitor is shown in Figure 4.23. The fabrication of anMIM capacitor is actually very similar to that of an M1-to-M2 via, differing only inthe lack of a nitride via (NV) opening in the case of a capacitor. The capacitor isshown in cross section in Figure 4.24. During fabrication, M2 is deposited into thehole that has been opened in the polyimide layer (PV) and comes to rest on top ofthe nitride dielectric. It is the “sandwich” of M1/nitride/M2 that forms the capaci-tor. The nitride dielectric layer is kept intentionally thin (about 2,000 angstroms) in

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules 57

Figure 4.21 The layout of an M1-to-M2 via.

Figure 4.22 Cross section of an M1-to-M2 via.

order to insure high capacitance per unit area. The capacitor’s value may be calcu-lated from the relationship

C = LW (0.300) fF (4.2)

where L and W are the length and width of the M2 top plate in microns. Capacitorsneed not be square, and if required may be designed with a wide range of aspectratios.

Because the M1 bottom plate is in contact with the substrate, it forms anopen-circuit microstrip stub and must be modeled as such in simulations. Figure4.25 gives the ADS simulator schematic for an MIM capacitor, including themicrostrip stub created by the M1 back plate. It is important always to rememberthat one capacitor contact is the M1 back plate, and the other contact is the M2 topplate. Attention to this detail will save the designer much trouble from hard-to-spotlayout errors.

4.3.5 Substrate Vias

It is possible to create excellent grounds at any point in a RFIC layout by using a sub-strate via. Substrate vias are metalized holes that reach from the top side of the chipto the bottom side. Since the metal on the chip’s bottom side is the truest groundreference, these vias provide the designer with an easy and fool proof way to groundany portion of the circuit without having to rely on attaching bond wire from the

58 InGaP/GaAs HBT Fabrication Technology

Figure 4.23 The layout of an MIM capacitor.

Figure 4.24 Cross section of an MIM capacitor.

edge of the chip to a ground pad in the chip’s package. By using substrate vias tocreate low-inductance grounds, a whole class of parasitic problems can be avoided.

The layout of a substrate via is shown in Figure 4.26. The central circle is themetalized hole, which extends from the bottom side to the top side of the chip. Allmetal layers (including collector metal) and all dielectric vias are present in thestructure of a substrate via. This is to add mechanical strength in this importantstructure. For safety reasons, substrate vias must not be placed too closely together,and they cannot be placed too close to the edge of a chip. The design rules given inFigures 4.8 to 4.11 specify the limits of these dimensions. The cross section of thesubstrate via is shown in Figure 4.27. To first approximation, a substrate via is aperfect ground contact. However, at higher frequencies, the metal in the backside totopside hole will have some small amount of inductance, which will act as a para-sitic element. There are existing simulator elements for substrate vias that can beused in the simulator schematic when the operating frequency is sufficiently high(above 5 GHz).

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules 59

Figure 4.25 Simulator model of an MIM capacitor.

Figure 4.26 The layout of a substrate via that provides direct grounding to the backside metal.

4.3.6 Bonding Pads

In order to connect external inputs and outputs to the RFIC, it is necessary to pro-vide metal bending pads where these wires can be connected using thermo-compression bonding techniques [3]. Mechanical strength is extremely important inthe structure of bond pads because the process of attaching a bond wire to a pad is soforceful that it can crack or delaminate the metal layers forming the pad. For thisreason, all metal layers (including collector metal, which has excellent adhesionproperties) and all dielectric vias are included in bonding pads. The layout of abonding pad is shown in Figure 4.28, and its cross section is shown in Figure 4.29. Inaddition, bonding pads, and bonding pads alone, require the presence of the scratchprotection via (SPV) layer to insure that an opening in the scratch protection dielec-tric has been made to allow the bond wire to contact M2 directly.

60 InGaP/GaAs HBT Fabrication Technology

Figure 4.28 The layout of a bonding pad.

Figure 4.27 Cross section of a substrate via.

Bonding pads also play an important role in on-wafer testing. This powerful testtechnique uses a carefully prepared set of RF probes that contact the inputs and out-puts of an RFIC die before it is separated from its wafer. In order to make this usefuland powerful test system work, a set of two (in the case of a signal-ground test probeconfiguration) or three (in the case of a ground-signal-ground test probe configura-tion) bond pads must be arranged in an array at each input/output to act as contactsfor the probes. Because of standard probe dimensions in use within the industry, thebond pads need to be 100µm × 100µm square and spaced at 150µm center to center.This probe-ready pad pattern is shown in Figure 4.30. Each RF input and RF outputneeds to be supplied with this probe pattern if on-wafer probe testing is to be doneafter wafer fabrication, but before die separation.

4.3.7 Crossover Capacitances

Whenever an M2 line crosses over either an M1 line or a TFR line, there will besome amount of crossover coupling capacitance. This capacitance is kept to a mini-

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules 61

Figure 4.29 Cross section of a bonding pad.

Figure 4.30 A pattern of input/output bonding pads that allows for convenient on-wafer RFprobe testing.

mum by the presence of the thick polyimide dielectric layer in this technology. Justas in the case of the intended capacitance of an MIM capacitor (Section 4.3.4), thecrossover capacitances are calculated by multiplying the overlap area between thetwo lines by the crossover capacitance per unit area of 0.15 fF/µm2. Figures 4.31 and4.32 show the layout and electrical model for M1-to-M2 overlap capacitance. Fig-ures 4.33 and 4.34 show the layout and electrical model for TFR-to-M2 overlapcapacitance. This capacitance is to be avoided whenever possible, even if it means“necking down” the lines in the region of overlap to avoid high overlap area. Ofcourse, circuit simulations will be the final determinant as to whether a given cross-over capacitance is excessive or not.

4.3.8 Spiral Inductors

RFIC’s inductor elements must be fabricated with a planar geometry. This needtranslates into spirals. Square spirals are most popular because they are the easiest to

62 InGaP/GaAs HBT Fabrication Technology

Figure 4.31 The layout of an M1-to-M2 crossover.

Figure 4.32 An electrical model for simulating the M1-to-M2 crossover capacitance.

create in layout; however, round spirals are also used extensively. Any spiral withmore than one turn must use a metal crossover in order to be attachable to the restof the circuit. If the spiral is formed from M1, this crossover will be an M2 “over-pass.” If the spiral is formed from M2, the crossover will be an M1 “underpass.”Both techniques work well, and both metals work well as inductors. Perhaps M2forms slightly higher-Q inductors owing to its slightly greater thickness. Of course,in both cases, an M1-to-M2 via will be required to transition from the spiral metalto the overpass or underpass metal. Figure 4.35(a) shows the layout of an M1 spiralinductor using an M2 overpass and an M1-to-M2 via. An ADS spiral inductor ele-ment (MRIND) is shown in Figure 4.35. Spiral inductors are very important ele-ments in RFIC designs because they are an integral part of all filtering and matchingcircuits. Also, spiral inductors can form resonator elements in VCO designs. Forthis reason, special attention needs to be focused on their design. It is importantto remember that there is no requirement that spiral inductors be square. Anycombination of length and width will serve as well as the better-known square lay-

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules 63

Figure 4.33 The layout of an M2-to-TFR crossover.

Figure 4.34 An electrical model for simulating the M2-to-TFR crossover capacitance.

out. This can be a valuable asset in the layout portion of any design because spiralinductors can become area drivers, and it is a big help for keeping chip area withinreasonable bounds to make the inductors fit the available space by changing theiraspect ratios.

4.3.9 Transistor Dummy Cells

In the case of some foundries, a transistor dummy cell will be provided for thedesigner to use for the purpose of keeping specific areas available for the insertion bythe foundry of all layers necessary to define a transistor’s unit cell. Such a dummycell is shown in Figure 4.36. All that needs to be done with the dummy cell is tolocate it within the circuit’s layout wherever a transistor unit cell is required and tocontact the dummy cell with M1 metal lines connecting it to other parts of the circuitas required.

64 InGaP/GaAs HBT Fabrication Technology

Figure 4.35 The layout of a spiral inductor using M1 metal.

Figure 4.35(a) An electrical model for simulating a spiral inductor.

4.3.10 Significant Layout Parasitic Elements

At low frequencies, it is possible to ignore many or most layout parasitic elementsand still produce a successful simulation. However, as the frequency increases, thesituation changes, and it becomes increasingly important to include a wider varietyof layout parasitic elements. Most simulators include a wide variety of these ele-ments, and it takes considerable skill and experience to know which parasitic ele-ments must be included and which can be safely ignored. My own experience is that5 GHz serves as a kind of dividing line in frequency. Below 5 GHz, only a few para-sitic elements need be included in simulation files. However, above 5 GHz, thedesigner cannot get away with ignoring certain additional elements. Figure 4.37shows the basic set of parasitic elements that need to be included for frequenciesbelow 5 GHz, and Figure 4.38 shows those additional layout parasitic elements thatmust be included for designs operating above 5 GHz.

4.3.11 Simple Layout Example

Figures 4.39 to 4.42 give simple layout examples using the concepts that have beendeveloped in this chapter. The first example structure is a three-finger transistorusing three unit dummy cells. The second example is a simple one-finger transistorfeedback amplifier with wafer probable bonding pads at the design’s input an out-put terminals. Notice the use and placement of M1-to-M2 vias where ever anM1-to-M2 connection is needed. Also, note the use of M2 base and collector buslines in the case of the three-finger transistor.

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules 65

Figure 4.36 The layout of a single-emitter-finger unit cell (dummy cell).

66 InGaP/GaAs HBT Fabrication Technology

Figure 4.38 Additional layout parasitic elements that must be included in simulator models tosupport operation above 5 GHz.

Figure 4.37 Significant layout parasitic elements that must be included in simulator models tosupport operation below 5 GHz.

4.4 Maximum Electrical Ratings

It is very important in all IC designs that maximum current limits in all conductorsbe observed. This is, first and foremost, a reliability issue. The major reliabilityproblem encountered with conductors carrying current is metal migration. Figure4.43 presents a table showing the maximum current density, expressed in milliam-peres per micron of line width for each conductor layer. These limits must be strictlyobserved to avoid any reliability problems that can shorten the lifetime of a chiponce it is in the field. The current referred to in Figure 4.43 is dc current; ac current,although it may be much higher that the dc current on peaks, does not cause the

4.4 Maximum Electrical Ratings 67

Figure 4.40 Details of three unit cell transistor layout showing how the collector contacts areconnected together.

Figure 4.39 The layout of a three unit cell transistor.

same level of metal migration to occur and, therefore, does not pose the same threatto reliability.

Metal migration may be understood in the following way. Referring to Figure4.44, we can envision that a current-carrying conductor is like a stream of waterwith a sandy bottom. We associate the water with the stream of flowing charge,which is the electrical current, and the sand on the bottom of the stream with the

68 InGaP/GaAs HBT Fabrication Technology

Figure 4.42 Layout details of the simple feedback amplifier layout example, showing intercon-necting metal lines and M1-to-M2 vias.

Figure 4.41 The layout of a simple single transistor feedback amplifier.

Figure 4.43 A table of maximum metal current densities, in milliamperes per unit metal width(measured in microns).

atoms at the conductor’s lattice sites. As the steam flows more rapidly, sand ispicked up from the bottom by the fast-moving water and deposited downstream.This process creates a series of holes (which, as all fisherman know, make goodhomes for trout and other game fish), where the water has scooped out the sand,and sand bars, where a buildup of sand occurs as it is carried to be deposited down-stream. In the same way, some metal atoms at lattice sites within the conductor aredislodged from their positions within the crystal lattice and transported “down-stream” by the steam of flowing electric charge, which forms the current. Just as inthe case of the steam of water, holes are formed where large groups of atoms are dis-lodged, and accumulations of atoms form “downstream” where these dislodgedatoms come to rest. The danger to reliability comes from the holes, where the con-ductor’s width is locally reduced by the “scooping out” of atoms from their latticesites. These areas of metallic “Swiss cheese” have increased resistivity relative to theunaffected portions of the conductor. Heating can occur locally at these “weak-nesses” within the conductor; over time, with sufficient current, the local tempera-ture rise can be sufficient to cause a failure. For this reason, all foundries provide alist of maximum dc current densities for each conductor layer within their designrules, much like the table given in Figure 4.43. A safety factor has already been builtinto this design rule. So, to produce a reliable device, all the designer need do isobserve these maximum current densities for all conductors within a design. Prob-lems sometime arise in resistors whose maximum current density is often less thanconductor lines, and with spiral inductors, which are often required to carry thelarge collector currents needed in power amplifiers. In the case of the resistor, theproblem can usually be solved by simply increasing the resistors width and recalcu-lating the resistors length using (4.1). Spiral inductors are more difficult to deal withrelative to current limits. The straightforward approach is simply to increase theinductor’s width until the current density limit is observed. The problem with thisapproach is that it often leads to the design of a very large inductor, which canbecome an area driver for the overall RFIC. An alternative that should be consid-ered, but is not always practical, is to place high-current carrying choke inductorsoff-chip. Many excellent surface-mount technology (SMT) inductors exist thatoccupy very little board space and carry high dc currents. Designers will need tomake this decision on a case-by-case basis.

4.4 Maximum Electrical Ratings 69

Figure 4.44 A diagram depicting the process of metal migration that occurs in a current-carryingmetal line.

The transistor unit cell also has current limits based on reliability consider-ations. These limits are based both on metal migration considerations, as discussedabove, and on self-heating due to power dissipation. The ultimate reliability of theRFIC’s transistors is a complicated function of temperature, time, and current. Mostfoundries perform extensive life tests of their IC transistors to insure that they willmeet their customers’ needs in this regard. It is very important for the designer tobecome familiar with the latest reliability tests published by the chosen foundry.

4.5 CAD Layout Tools

A CAD layout system is an absolute necessity for RFIC design layout. Many design-ers do their own layout, while other designers rely on the services of companies within-house departments that specialize in producing high-quality IC layouts. Whetheryou do the layout yourself or use a service is largely a choice determined by howyour organization does business. Both approaches can be made to work. If you dothe work yourself, it will be necessary for you to obtain the proper design tools forthis purpose. While layouts can be produced on any CAD software that allows formultiple overlapping layers (such as AutoCAD®), it is more preferable to use a toolset specifically developed for IC layout. Excellent, but very expensive, layout toolpackages are available from Cadence Design and Mentor Graphics. Amedium-priced layout tool is available from IC Editors. The IC Editors layout toolset was used to produce all of the RFIC layout shown in this book. I have personallyused the IC Editors tools for several years with excellent results.

Generally speaking, once a designer has experience with one set of IC layouttools, it is relatively easy to “come up to speed” on another tool. This is becausemost of the layout functions used in IC layout are common to all tools, and all ittakes to translate to another tool set is simply learning how to use these functions ina new environment.

References

[1] Matthias, M., Introduction to Modeling HBTs, Norwood, MA: Artech House, 2006.[2] Liu, W., Fundamentals of III–V Devices, HBTs, MESFETS, HFETS/HEMTs, New York:

John Wiley and Sons, 1999.[3] Sweet, A., MIC and MMIC Amplifier and Oscillator Circuit Design, Norwood, MA: Artech

House, 1990.[4] Ghandi, S., VLSI Fabrication Principles, Silicon and Gallium Arsenide, New York: John

Wiley and Sons, 1983.[5] Edwards, T., Foundations for Microstrip Circuit Design, New York: John Wiley and Sons,

1983.

70 InGaP/GaAs HBT Fabrication Technology

C H A P T E R 5

SiGe HBT Fabrication Technology

5.1 SiGe HBT Transistor Structures

Unlike GaAs HBT devices that represented a radical departure from the traditionaldesign of GaAs MESFET RF/microwave transistor devices, SiGe HBT devices haveevolved as the next logical step in the development of silicon BJT devices andBiCMOS fabrication [1]. The pure silicon BJT devices of the late 1980s were limitedto a Ft performance level of less than 40 GHz without any noticeable improvementas a function of time [2]. Ft represents the frequency at which the device’s currentgain has fallen to unity. One problem contributing to this lagging performance wasrelated to how the base layer was formed. In those days, BJT base layers were fabri-cated by an ion implantation process [3] that introduced a very thin layer of borondoping to establish the boundaries of the base layer. The fabrication of a thinnerbase layer was needed to improve the device’s Ft significantly. The problem with thisapproach was related to how the layers were heat-treated during the annealing pro-cess (activating the boron acceptor sites) after the implantation of the base layer.Unfortunately, every attempt to maintain a very thin boron doping profile (i.e., avery thin base layer) during ion implantation was countered by a diffusion of theboron atoms during the annealing heat-treating process [4], effectively broadeningthe base layer and reducing Ft. Any attempt to raise the performance of the device(i.e., increase Ft) was self-defeating due to high-temperature wafer processing. Anew paradigm for the design and fabrication of Si BJT devices was needed toachieve significant improvement in performance.

The new paradigm for Si BJT device design and fabrication came at IBM’s T. J.Watson Research Center in the mid-1980s [5]. Until this point, all BJT fabricationhad involved process steps that often reached over 1,000°C. It is these high tempera-tures that cause boron diffusion, which broadens the base layer, lowering RF per-formance. Also, high-temperature fabrication can significantly impact the purity ofthe silicon by introducing dislocations and other electrically active impurities.Device designers reasoned that to achieve the twin goals of a thinner base layer (toraise Ft) and higher-purity silicon, an inherently lower-temperature process wouldbe needed. But what were the alternatives? Since the 1960s, ion implantation hadbeen the tried-and-true approach to fabricating high-performance RF BJTs. Theanswer came in two separate pieces to the puzzle. The first major change was toreplace the ion-implanted base-fabrication process with a low-temperatureepitaxial base process. The second major change called for the introduction of asmall amount of SiGe into the epitaxial base. This SiGe-Si alloy base had its ownspecial properties that led to spectacular improvements in performance.

71

It was low-temperature epitaxy that really made the ultimate improvementspossible. A process called ultrahigh vacuum chemical vapor deposition (UHV/CVD)[6] was developed at IBM for this part of the device-fabrication process. Workers atIBM found that wafers fabricated by UHV/CVD epitaxy could be processed at tem-peratures below 500ºC and still reach a purity exceeding that of wafers that hadbeen processed traditionally at temperatures exceeding 1,000°C. When treated witha hydrofluoric acid (HF) solution, these wafers proved to be highly hydrophobic(i.e., would not wet). This condition was understood to mean that the wafer hadacquired hydrogen-terminated silicon bonds across its surface [7]. This intrinsicdewetting behavior made wafers thus treated thirteen orders of magnitude less reac-tive with the air. It is this reluctance to react with air that gives UHV/CVD epitaxialwafers their ability to maintain high purity in spite of their ultimate processing attemperatures less than 500ºC. By achieving this low-temperature epitaxial base pro-cess, extremely thin, high-purity base layers became possible [8].

We return now to the reasons for introducing a SiGe-Si alloy into the device’sbase layer. The introduction of a SiGe-Si alloy into the base layer producesheterojunctions at both the emitter-base junction and the collector-base junction,unlike GaAs/InGaP HBT devices, which have a single heterojunction at their emit-ter-base junction; resulting from their InGaP emitters. In the case of the dualheterojunction SiGe HBTs, the valance-to-conduction band-gap energy is signifi-cantly reduced by the introduction of as little as 4 percent SiGe into the base layer.Since the band-gap energy in the base layer is reduced, the potential barrier encoun-tered by electrons moving across the emitter-base junction is lowered; therefore, fora given base-hole current flowing into the emitter, the electron current flowing fromthe emitter through the base (and into the collector) is substantially increased by thepresence of SiGe in the base layer. This increase in electron flow translates intohigher collector current, which means that collector current is increased by the pres-ence of SiGe in the base with no increase in the base current. The net effect is todirectly increase the transistor’s current gain, . Both hole and electron mobilitiesare increased by the addition of SiGe to the base layer. In addition to improvementsin and mobility, Ft and Fmax (the frequency at which the transistor’s power gainbecomes unity) are each increased by the presence of SiGe in the base. Also, thedevice’s Early voltage is increased, and its output conductance is decreased. Bothchanges represent significant performance improvements. Since is largely deter-mined by the base’s SiGe content, it is possible to boron-dope the base heavily inorder to lower the base resistance without affecting . This technique further raisesboth Ft and Fmax. Figure 5.1 shows the energy band structure of a pure Si BJT over-laid with that of a SiGe HBT. Best device performance is achieved when the germa-nium (Ge) concentration in the base is graded toward the collector-base junction.Figure 5.2 shows the profile of a typical SiGe HBT device, indicating the shape ofboth the doping profile and the epitaxial SiGe concentration. Figure 5.3 gives aGummel plot (a log-log plot of base current and collector current versusbase-to-emitter voltage) for a SiGe transistor showing dramatically how the transis-tor’s full is realized at Vbe values in the range of 0.70V to 0.80V. This low value ofVbe is achieved because of the relatively low band-gap energy of Si and SiGe com-pared to the high band-gap energy of GaAs (which leads to a Vbe of 1.4V to 1.5V insimilar GaAs HBT devices). A plot of Ft versus collector current (for an emitter size

72 SiGe HBT Fabrication Technology

of 0.5m × 2.5m) is given in Figure 5.4 [9]. Excellent Ft is available over a wide rangeof collector currents. Ft reaches its maximum value at a collector current of 1.0 mAand decreases for higher collector currents. This decrease of Ft for higher collectorcurrents is called the Kirk effect [10] and is related to the shifting of the electric fieldswithin the transistor’s junctions under high-current conditions. The user of thedevice has the option of obtaining the highest frequency and gain capability of thedevice when operating it at 1.0 mA collector current, or the user may accept aslightly lower maximum frequency and gain at a given frequency by reducing thecollector current (by as much as a factor of five) in order to reduce dc power.

A major issue in the fabrication of epitaxial SiGe base layers is associated withthe stability of thin SiGe films that are grown onto a pure silicon crystal. Both sili-

5.1 SiGe HBT Transistor Structures 73

Figure 5.1 An energy band diagram within an NPN transistor showing how the introduction of agraded germanium profile within the base region causes the conduction band energy to decreasebetween the emitter-to-base junction and the base-to-collector junction. This sloping conductionband energy greatly enhances the emitter electron injection efficiency of a SiGe HBT relative tothat of a pure silicon BJT.

Figure 5.2 A diagram of typical doping type and concentration (and percentage of graded ger-manium within the base region) for an NPN SiGe transistor.

con and germanium crystals have a diamond crystal lattice structure. However,instability in the SiGe layer may result because a lattice constant mismatch of aboutfour percent exists between silicon and germanium at room temperature. Pure sili-con has a lattice constant of 5.43 Angstroms, while pure germanium has a latticeconstant of 5.66 Angstroms [11]. The question is, does the resulting SiGe filmassume the lattice constant of the pure silicon crystal (upon which it is grown), ordoes it revert to its natural lattice constant, which is midway between 5.43 Ang-stroms and 5.66 Angstroms (depending upon the relative germanium concentra-tion)? The answer is that as long as the SiGe film is quite thin, the film retains thelattice constant of pure silicon up to a certain critical thickness, at which point insta-bility begins. A natural strain energy is built into such a film as a natural result of thislattice constant mismatch. Such films are called “pseudomorphic,” a term derivedfrom the Latin words meaning “false form.” Pseudomorphic films, under stress,assume the lattice constant of the substrate host. However, once a critical film thick-

74 SiGe HBT Fabrication Technology

Figure 5.4 A plot of Ft and Fmax of a SiGe HBT as a function of current density, demonstrating theKirk effect as maximum performance is reached at some critical current density.

Figure 5.3 A Gummel plot comparing the collector and base currents of a standard silicon BJTwith that of a SiGe HBT. This diagram indicates the presence of significantly higher beta with theSiGe HBT device relative to a standard silicon BJT.

ness has been reached, the SiGe film can no longer conform to the lattice constant ofsilicon and must “relax” to its natural value, causing crystal defects, called disloca-tions, to form at the Si-SiGe interface. Such defects act as impurities that limit theusefulness of the base film as a part of the transistor as a whole. Therefore, it is ofparamount importance that the epitaxial base layer thickness not exceed the criticalthickness for stability. The critical thickness for maintaining stability depends onboth the germanium concentration and on the “grading” of the germanium concen-tration within the base film. In very rough terms, to remain stable, the SiGe basefilm must have a thickness that remains less than about 100 nm for an average ger-manium concentration between 5 and 10 percent. It is possible to increase the stablethickness of the SiGe base layer by the epitaxial growth of a pure silicon cap on topof the SiGe base film. However, since device performance (i.e., Ft) is enhanced by athinner base, every effort is made during fabrication to keep the base as thin as pos-sible for both stability and performance reasons. Figure 5.5 shows how the criticalfilm thickness for stability varies with both germanium concentration and siliconcap thickness.

By fully exploiting the techniques described above, it has been possible toincrease the Ft of a BJT device from under 40 GHz in the late 1980s to more than200 GHz today [12]. These amazing improvements are directly attributable to theuse of low-temperature UHV/CVD epitaxial SiGe base films. These epitaxial filmsmay be grown at any point in the fabrication process and need not be associatedwith pre-photolithographically processed wafers only, as is the case withGaAs/InGaP HBT technology, where HBT device isolation is often achieved byetching away all of the initial epitaxial film, except at the locations of a device“mesa.”

Next, let us turn our attention to the structure of an NPN HBT device. The crosssection of a latest-generation SiGe HBT device structure is shown in Figure 5.6. Itshould be noted that today almost no stand-alone SiGe fabrication facilities exist.All foundries offering a SiGe process make use of a BiCMOS process that uses theSiGe HBT devices as the “Bi” part of the fabrication process by integrating theminto an existing CMOS “backbone” process. This BiCMOS approach has the

5.1 SiGe HBT Transistor Structures 75

Figure 5.5 Maximum stable SiGe base thickness as a function of germanium concentration witha silicon cap thickness as a parameter.

advantage to the designer of offering a full range of CMOS components that can beused for digital control and low-frequency analog circuits, while the SiGe devices areused for the high-speed/high-frequency portions of the RFIC’s system.

The SiGe bipolar devices may be introduced into the otherwise CMOS processin one of two ways. The first approach is called “base during gate” (BDG), referringto the ability of this process to use a common process step to fabricate both CMOSgates and HBT bases simultaneously. The second approach is called “base aftergate” (BAG), referring to the ability of this process to fabricate the CMOS gatesfirst, and then, as a separate process step, to fabricate the SiGe HBT base layer. TheBAG technique has the advantage that since the HBT base fabrication comes afterthe CMOS gate fabrication, the base epitaxial films do not experience thehigh-temperature portions of the CMOS fabrication process. Therefore, thebase’s boron doping experiences fewer diffusion effects that could broaden thebase’s width, lowering Ft. For this reason, the BAG technique has become increas-ingly popular in the latest generation of SiGe devices as a way of increasing devicespeeds.

Areas of critical importance in the design of the HBT device are the necessity fordevice-to-device isolation structures (since mesas are not used in a BiCMOS process)and finding ways to minimize the effects on the SiGe base epitaxial layer resultingfrom ion implantation of the extrinsic base and its electrical parasitic effects. Interms of the base structure, best results have been obtained [13] using a raisedextrinsic base. This technique shields the epitaxial intrinsic base film from crystaldamage caused by implantation of the extrinsic base. Another useful technique for

76 SiGe HBT Fabrication Technology

Figure 5.6 The cross section of a high-performance, raised, extrinsic-base SiGe HBT.

minimizing the depth of the base layer is the introduction of some carbon dopinginto the base layer (along with the germanium and boron). These carbon atomshave the ability to suppress out-diffusion of the boron doping atoms within the baseduring fabrication, with the net effect of keeping the width of the base film razorthin.

Device-to-device isolation is provided by an array of shallow and deeppolysilicon-filled “trenches” that act as electromagnetic shields around the HBTdevice. The trenches must be deep enough to completely surround the device’ssubcollector down to the conductive substrate, or device-to-device coupling couldoccur via the subcollectors. As it is, the potential of coupling through the conductivesilicon substrate is always a possibility that must be dealt with.

Silicide contacts are grown on the emitter, base, and collector regions of thedevice in order to facilitate low-contact-resistance interconnects to the rest of thecircuit. The emitter itself consists of an in situ doped polysilicon structure of a typethat has achieved Ft’s greater than 200 GHz [14]. These extremely high-frequencydevices have found application in a wide variety of microwave, millimeter-wave,and optical applications.

A useful expression for the Ft of a SiGe HBT device is based on diffusion capaci-tance charging is given as [3]

1/2 Ft = (kT/qIe) (Ceb + Ccb) + RcCcb + b + c (5.1)

where

k is Boltzman’s constant (1.38E–23 J/K).T is the temperature in degrees kelvin.q is the charge of an electron.Ie is the emitter current.Ccb is the collector-base diffusion capacitance.Ceb is the emitter-base diffusion capacitance.Rc is the collector resistance.

b is the base transit time.

c is the collector space charge transit time.

An expression for Fmax is given as follows:

F F R Ct bb cbmax /= 8π (5.2)

where

Rbb is the parasitic base resistance.

Another important issue in many applications (such as power amplifiers) isbreakdown voltage. From an applications viewpoint, the most important break-down voltage is BVceo. BVceo is the breakdown voltage from collector-to-emitterwith zero base current. This breakdown voltage determines the maximum useful

5.1 SiGe HBT Transistor Structures 77

range of collector-to-emitter voltages for a given application. Power amplifiers are agood example of applications where this breakdown voltage is of critical impor-tance. The cause of this breakdown voltage is a phenomenon called avalanche multi-plication [15]. During avalanche multiplication, a process called impact ionizationoccurs when carriers are accelerated to sufficiently high energies by the electric fieldsuch that, upon impact with a lattice site, these carriers become capable of elevatingan electron from the material’s valence band to its conduction band. Such an impactcan set off a chain reaction whereby the newly generated free electrons and holesthemselves acquire enough energy from the electric field to generate more electronsand holes. This process creates a chain reaction (similar to the chain reaction set upduring nuclear fission). Under these conditions, device current becomes very highand threatens to destroy the device. Avalanche multiplication is caused by the peakelectric field within these devices. In devices with very thin base layers, the peak elec-tric field can become high, especially if the doping level is high in the collectorregion. Therefore, the combination of very thin layers and high doping can add up tovery low values of BVceo, which can be in the range of 1.5V to 3.0V with the highestFt devices.

There is a fundamental device limitation relationship between a device’s Ft andits breakdown voltage called the Johnson power limit [16]. The simplest statementof the Johnson limit is

(BVceo) Ft = Emax Vs/2 (5.3)

where

BVceo is the device’s collector-to-emitter breakdown voltage.

Ft is the frequency at unity current gain.

Emax is the maximum electric field within the device.

Vs is the maximum carrier drift velocity.

For SiGe devices, the value of the Johnson limit is approximately 200 GHz-V.This limit implies that for a device with an Ft of 50 GHz, the value of BVceo is 4V, adevice with an Ft of 100 GHz would have a BVceo of 2V, and a device with an Ft of200 GHz would have a BVceo of 1V.

The Johnson limit strongly implies that an absolute limit exists on thepower-generating capability of a SiGe device (and any other type of device) that isstrongly frequency dependant. The Johnson limit describes a fundamental devicetrade-off between breakdown voltage (related to power-generating capability)and Ft (related to maximum frequency of operation). A third element in the trade-offis gain, which for a given frequency increases with increasing Ft, which inturn decreases BVceo. Therefore, a three-way trade-off exists between RFpower-generation capability, maximum usable frequency, and gain at a givenfrequency. For a given device design, the maximum usable frequency and gain canbe raised (by reducing the width of the base layer for instance), but only at theexpense of breakdown voltage and power-generation capability for a given overalldevice size [17].

78 SiGe HBT Fabrication Technology

5.2 Transistor Device Models

Like all bipolar transistors, the SiGe HBT was originally modeled using GummelPoon SPICE models (SPG) of the same kind that are used with GaAs/InGaP HBTdevices. These models were found to be deficient in several areas, including Earlyvoltage modeling, output conductance modeling, avalanche multiplication (break-down voltage), thermal self-heating, and transit-time modeling. The later VBICmodels were successfully applied to SiGe HBT, with significant improvementsresulting in all of the areas where the SPG models are deficient. Today, most SiGefoundry design kits include HBT models that effectively integrate the SPG and VBICmodels. The net result is a scalable large-signal device model that very effectivelysimulates all of the dc, small-signal, and large-signal performance characteristics ofthe SiGe HBT device. Two additional bipolar models (HiCUM and MEXSTRAM)are under evaluation at IBM and other foundries in order to increase model accu-racy relative to what is available right now with the VBIC models.

A generic SPG SiGe model is given in Figures 5.7(a–c). Device S-parametersderived from the SPG model are shown in Figure 5.8. These models can be useddirectly in the Agilent ADS simulation tool and other similar tools. The model mayalso be used with the Cadence tool set that integrates the schematic capture, simula-tion, and layout functions. Since all SiGe foundry processes are BiCMOS, it isimportant that the designer’s choice of CAD tool set be capable of working easilywith all of the foundry’s CMOS models in addition to the bipolar models. TheseCMOS devices come along as freebies, and most, if not all, designers will want totake full advantage of the design flexibility and capability these CMOS devicesoffer.

The Cadence tools have become increasingly popular for designing SiGe circuitsbecause of their ability to integrate the functions of simulation and layout when

5.2 Transistor Device Models 79

Figure 5.7(a) An ADS circuit schematic diagram for simulating the IV curves of a generic Gummel Poonmodel for a unit cell SiGe NPN HBT.

using a large number of highly specialized CMOS models and passive device modelsin addition to the HBT device models. The complex BiCMOS nature of all SiGefoundry processes makes the use of a highly integrated CAD tool set, such asCadence, a necessity. The Cadence Spectra RF® simulation tool is based on a peri-odic steady state time domain simulator. In this regard, a third-party harmonic-balance-based simulation tool (Golden Gate®) is available from Xpedion Design,

80 SiGe HBT Fabrication Technology

Figure 5.7(b) Generic, large-signal, scalable, Gummel Poon device model for a SiGe HBT unitcell.

Figure 5.7(c) Simulated IV curves for the generic unit cell SiGe HBT using the Gummel Poonmodel.

Inc., an independent company (now part of Agilent, Inc.) whose simulation tool canbe integrated into the Cadence tool set. The Golden Gate harmonic-balance simula-tor works directly with the Cadence tool set, giving the designer a harmonic-balancesimulation capability, rather than the periodic steady state time domain simulationthat normally is available with the Cadence tools. Golden Gate also offers a full setof transmission line elements that are very useful for modeling parasitic effects athigh frequencies. The use of a harmonic-balance simulator has certain advantagesin RF applications. In addition to simulation speed, harmonic-balance techniquesyield more robust convergence and greater accuracy at high signal levels, which aresignificant advantages in power amplifier and modulator design.

5.3 Passive Device Structures and Models

It is in the area of passive devices that SiGe and GaAs/InGaP technologies differmost profoundly. This technology difference is based on three areas of uniqueness.The first concerns the nature of substrates, the second concerns the number andtypes of interconnect metals, and the third has to do with the many unique passivedevice structures that come along with SiGe’s CMOS backbone process.

Substrate characteristics in the case of the GaAs/InGaP process are straightfor-ward and easy to work with. After patterning and photolithography fabrication, theindividual HBT devices in those regions of the wafer where epitaxial materialremains are etched away to expose the underlying semi-insulating GaAs substrate.This underlying substrate is an almost perfect medium for patterning and fabricat-ing gold metalized microstrip lines. The substrate’s resistivity is similar to that ofceramic or glass, which means the dielectric loss of any microstrip line making useof this substrate material is very low—almost zero loss. The GaAs substrate’s dielec-tric constant is 12.5. Therefore, even at very high frequencies, all microstrip linesmaking use of this substrate are essentially lossless (except for the metal loss in thetopside gold traces). These highly ideal IC microstrip lines make excellent,high-quality, low-loss, low-parasitic interconnects at high frequencies. In fact, the

5.3 Passive Device Structures and Models 81

Figure 5.8 Simulated small-signal S-parameters using the generic SiGe unit cell Gummel Poon model.

electrical behavior of the GaAs/InGaP interconnect lines can be very accuratelymodeled by making use of the various microstrip transmission line elements in ADS®

and similar simulators (see Chapter 4). From the viewpoint of modeling such a cir-cuit, the situation is no different from modeling a metalized ceramic substrate or anFR4 PCB. Microstrip elements determine the reactive portion of the interconnec-tion’s behavior. Even cross-coupling between various parts of a circuit can be accu-rately modeled by using coupled microstrip transmission line simulator models. (SeeChapter 4 for details of the modeling process with GaAs/InGaP technology.) Sincetheir line loss is very low, the net effect of the microstrip interconnects is to intro-duce reactive elements between the circuit nodes being connected. These reactiveelements must be included in any matching structures that are designed to matchthe devices being interconnected. Especially at high frequencies, it becomes veryimportant (and straightforward in application) to include the metal interconnectelements within the total circuit model as some form of ideal microstrip transmis-sion line.

When contrasting the nature of a GaAs substrate with a silicon substrate as isencountered in SiGe technology, the following conclusions may be drawn: In silicontechnology there is no equivalent to the semi-insulating substrate that is availablewith GaAs technology. Most commonly, SiGe wafers use an underlying P+ sub-strate. Since there is doping within the substrate, there will always be some dielectricloss associated with any passive device fabricated on this substrate. For example,resistors fabricated on these substrates will have some backside coupling to the sub-strate through the parasitic parallel plate capacitance to the substrate. This couplingwill be inherently lossy due to the conductive nature of the P+ substrate. Therefore,unlike corresponding resistors in GaAs technology, resistors in SiGe technology willalways experience some amount of frequency-dependent loss associated with theircapacitive coupling to the lossy substrate. It is the same situation with capacitors ofall kinds. The bottom plate of the capacitor will have a parasitic capacitor that cou-ples it to the lossy substrate. This substrate coupling will introduce lossy elementsinto the capacitor’s equivalent circuit. The same situation exists with spiralinductors, where the issue can be particularly profound owing to the size ofinductors compared to resistors and capacitors. Diodes (including varactor diodes)and interconnecting metal lines (including microstrip transmission lines) suffer fromthe same situation. The backside metallization is coupled (via the equivalent circuitcapacitors) to the lossy substrate, introducing lossy elements into the device’s overallmodel. The equivalent circuit of a SiGe technology resistor is shown in Figure 5.9,and the equivalent circuit of a SiGe technology capacitor is shown in Figure 5.10.The equivalent circuit of a SiGe technology inductor is shown in Figure 5.11.Models contained in a foundry design kit will always account for substrate effects.Therefore, it is critical to use only these models during the design process.

The P+ substrate introduces some additional problems into the circuit model.First, because it is somewhat conductive, all circuit elements are connected (or cou-pled via capacitance) to each other. This coupling can introduce a highly objection-able loss of isolation between certain parts of the circuit. For example, low levels ofcross-coupled LO’s signal arriving at a mixer’s input can be highly objectionable incertain applications. To isolate one region of the circuit from another may requirethe introduction of conductive trenches and guard rings into the design in order to

82 SiGe HBT Fabrication Technology

counter the conductive substrate’s tendency to couple all parts of the circuit, one toanother. In addition to the ability to introduce signals into circuit nodes where theydon’t belong, there is a second negative side to this coupling issue, which is the abil-ity of a conductive substrate to couple noise from digital portions of the circuit (i.e.,CMOS control circuits) into the RF/analog portions of the circuit. Such noise cou-pling can cause some potentially very troublesome noise modulations. In manycases, especially at high frequencies, standard circuit simulation tools are unable tosimulate these substrate-coupling effects accurately. However, substrate effects canoften cause serious problems, making additional design iterations necessary at sig-nificant cost and schedule slippage. Therefore, it may become necessary (and timeand money will be well spent) to model the substrate effects using three-dimensionalelectromagnetic simulators such as those available from Sonnet Software, Inc. Elec-tromagnetic simulations for a general set of metal and dielectric conditions are pos-sible but require a lot of effort. However, if substrate effects are to be simulatedaccurately, this approach must at least be considered and probably followed since

5.3 Passive Device Structures and Models 83

Figure 5.9 Simulator model for a resistor in a SiGe BiCMOS process.

Figure 5.10 Simulator model for a capacitor in a SiGe BiCMOS process.

the circuit element simulation tools (such as ADS® and CADENCE®) are not capableof handling the required degree of geometric uniqueness. This is especially true athigh frequencies, where coupling effects become much stronger than in the 1–3 GHzrange of most wireless applications. However, it is at these very high frequenciesthat SiGe HBT devices hold their greatest promise because of extremely high Ft.

SiGe technology has the ability to fabricate a large number of metal layers (asmany as six), some of them quite thick. However, SiGe technology makes use of analuminum metal system (there is a recent trend toward the use of copper metal forsome layers, but this change is still in the early stages). Aluminum metal and evenaluminum metal plus copper do not possess the same low resistivity as the goldmetal system used in GaAs technology. Table 5.1 lists the typical metal layer optionsalong with their resistivity in milliohms per square. Since thick metals are often usedto fabricate spiral inductors, the approximate Q of a 1 nH inductor fabricated froma given metal layer is also listed in Table 5.1.

In some cases these metal layers can be “stacked” on top of each other toincrease the Q of the resulting structure. However, even with thick metal layers,inductor Q’s may be limited by the effect of the lossy substrate. Some foundries offermetal ground layers (Faraday shields) between the inductor and the lossy substrate.These structures have the ability to increase Q, but they also add to the designer’sproblems in terms of scaling the inductor’s size. Because the foundry typically mod-els only a few different sizes of inductors, the designer is placed in the uncomfortable

84 SiGe HBT Fabrication Technology

Figure 5.11 Simulator model for a spiral inductor in a SiGe BiCMOS process.

Table 5.1 Typical Metal Layer Parameters for a SiGe BiCMOS Process

Metal Rs in milliohms Inductor Q at 4 GHz

2 um Al 14 74 um Al 7 184 um Al/3 um Cu 3 28

position of having only a limited range of inductor sizes with associated simulatormodels. If the designer wishes to use an inductor whose value lies outside of themodeled range, there is uncertainty about the model’s applicability. The same situa-tion exists for intermediate values of inductors; the exact model may not exist, forc-ing the designer to guess the intermediate model values. For this reason, designersoften feel their range of inductor-value options is significantly limited in compari-son to GaAs technology, where just about any size inductor may be accurately mod-eled using standard simulator spiral inductor models. Quite often, the solution tothis problem is to fall back on electromagnetic simulations to provide an accuratemodel for an inductor whose size or shape does not fit with the standard foundryinductor models. Even with careful modeling of a nonstandard inductor, thedesigner may find it is a hard sell to convince the foundry to include such nonstan-dard inductors in their final design.

Because SiGe technology is built around a CMOS fabrication backbone, quite anumber of CMOS passive devices become available to the designer as options thatcan be used whenever it makes sense for a given design. Table 5.2 lists the resistoroptions a SiGe designer can call upon as needed. Table 5.2 includes each resistor’ssheet resistance, its TCR, its parasitic capacitance, and its maximum current.

Likewise, a family of capacitor options is also available. These capacitors arelisted in Table 5.3, along with the capacitance per unit area, tolerance, and TCC foreach option. Some foundries are now offering advanced capacitor options, such asvertical plate capacitors with high breakdown voltages.

Families of varactor diodes are also available with SiGe technology. Thesevaractor diodes are used as tuning elements for the VCO circuits used inphase-locked loops. Some varactor diodes have more available tuning range thanothers. The three varactor diode options available with most SiGe fabrication pro-cesses are listed in Table 5.4, with their approximate available tuning ratio. It isimportant for the designer to check carefully the degree of tuning linearity availablewith each varactor option. The required varactor tuning linearity is very applicationdependent. Most foundries provide excellent models for their varactor diode

5.3 Passive Device Structures and Models 85

Table 5.2 Typical Resistor Options with Electrical Parameters for a SiGe BiCMOS Process

ResistorResistance(Ohm/sq.)

TCR(ppm/c)

Para cap(fF/sq. um)

Max I(mA/um)

P+ polysilicon 270 21 0.11 0.6P polysilicon 1,600 –1,105 0.09 0.1N+ diffusion 72 1,751 1 1N subcollector 8 1,460 0.12 1TaN 142 –728 0.03 0.5

Table 5.3 Typical Capacitor Options with Electrical Parameters for a SiGe BiCMOS Process

Capacitor C0 (fF/sq. m) Tolerance (%) TCC (ppm/C)

MOSCAP 1.5 10 48Poly-poly 1.6 25 21MIM 0.7 15 –57

options. However, in general, there is a lot of variability from foundry to foundry interms of scalable models and substrate options. Some foundries supply the designera full set of scalable models, including spiral inductors. Others do not. Also, sub-strate options such as ground shield and deep trenches are available from somefoundries but not from others.

5.4 Design Rules

The design rules associated with a SiGe technology process are, by their very nature,extremely complex. It is more than is reasonable to expect any designer to keep trackmanually of the whole interwoven set of geometric rules that determine the possiblerelationships (and their violations) within and among all of the metal and dielectriclayers of a SiGe BiCMOS process. Thus, it is necessary for designers to have avail-able to them a set of CAD tools that internalize and automate the complete set ofdesign rules. This implies that an ideal tool set is one that can at any time perform aDRC on the whole circuit or any part of the circuit. It is also important that the toolset make available to the designer all foundry device models with computationallyeasy ways to modify and scale these models. In most cases, the foundry will providethe designer with a process design kit (PDK) that installs inside the software tools allof the necessary models for characterizing the foundry’s available devices, includingboth active devices, such as transistors, and passive devices, such as resistors, capaci-tors, inductors, and varactor diodes.

5.5 CAD Layout

Once the lumped-element circuit design has been completed, it is necessary to turnthe new design into a layout. With SiGe technology, this can be a difficult and exact-ing process. A major concern is the need for component-to-component isolationwithin the circuit. Some techniques for providing this isolation include using guardrings and deep and shallow conductive trenches around specific devices. It can alsobe helpful to provide an RF ground layer under some or all of the RF circuit in orderto reduce digital noise and increase the isolation of stray device-to-device paths. Fig-ure 5.12 shows a diagram of the various techniques for increasing isolations within adesign. None of these techniques is completely foolproof, and all should be regardedas suggestions rather that requirements [18, 19]. Sometimes electromagnetic simula-tions can raise confidence that a given isolation technique is truly as effective as thedesigner hopes. Without this kind of confirmation, the designer is forced to go backthrough wafer fabrication yet another time to confirm experimentally that a givenset of isolation techniques is truly effective. The designer’s best defense against hav-

86 SiGe HBT Fabrication Technology

Table 5.4 Varactor Diode Options for a Typical SiGe BiCMOS Process

Varactor Type Tuning Ratio

Collector-base 1.3:1Hyperabrupt 3.4:1MOS accumulation 2.5:1

ing to make an excessive number of prototype wafer-fabrication iterations is to havean excellent CAD tool set that, to the highest degree possible, automates the designprocess, freeing the designer to concentrate on thinking through concepts andevaluating circuit options. Additionally, the designer must have access to a three-dimensional electromagnetic simulator with the ability to provide insight into theeffectiveness of a given structure relative to combating stray isolation and substratenoise problems. Generally speaking, the CAD tools pay for themselves in terms ofreducing the number of prototype “spins” required in order to ensure that a newdesign meets all of its specifications. This goal is not unreasonable, considering thatprototype wafer-fabrication costs can run in the range of $70,000 to $100,000,depending on process speed (i.e., Ft).

If you are able to reduce the number of prototype spins by two, the potentialsavings are as much as $200,000, not to mention a significantly accelerated time tomarket. The bottom line is that designing SiGe RFICs is an CAD-intensive enter-prise. There seems to be no way of avoiding a large tool budget and high prototypeengineering costs.

References

[1] Groves, R., et al., “High Q Inductors in SiGe BiCMOS Process Utilizing a Thick MetalAdd-on Module,” Proc. 1999 BCTM, 1999.

[2] Rieh, J., et al., “SiGe HBTs with Cut-off Frequency of 350 GHz,” International ElectronDevice Meeting, December 2002, pp. 771–774.

[3] Singh, R., Harame, D., and Oprysko, M., Silicon Germanium Technology, Modeling, andDesign, New York: IEEE Press and Wiley Interscience, 2004.

[4] Ashok, K., et al., Polysilicon Emitter Bipolar Transistors, New York: IEEE Press, 1989.[5] Meyerson, B., “Low Temperature Silicon Epitaxy for Ultra-High Vacuum/Chemical Vapor

Deposition,” Applied Physics Letters, Vol. 48, 1986, pp. 797–799.[6] Patton, G., et al., “Graded SiGe Base Poly-Emitter Heterojunction Bipolar Transistors,”

IEEE Electron Device Letters, Vol. 10, No. 12, 1989, pp. 534–536.

5.5 CAD Layout 87

Figure 5.12 Isolation device structures for reducing substrate noise and cross talk substrate cou-pling with SiGe BiCMOS device technology.

[7] Meyerson, B., “Bistable Conditions for Low Temperature Silicon Epitaxy,” Applied PhysicsLetters, Vol. 57, 1990, pp. 1034–1036.

[8] Stiffler, S., et al., “The Thermal Stability of SiGe Films Deposited by Ultra-High VacuumChemical Vapor Deposition,” J. Applied Physics, No. 70, 1991, p. 1416.

[9] Patton, G., et al., “Graded SiGe Base Poly-Emitter Heterojunction Bipolar Transistors,”IEEE Electron Device Letters, Vol. 10, No. 12, 1989, pp. 534–536.

[10] King, C., et al., “Bandgap and Transport Properties of Si1-xGex by Analysis of Nealy IdealSi/Si1-xGex/Si Heterojunction Bipolar Transistors,” IEEE Transactions of ElectronDevices, Vol. 36, No.10, October 1989, pp. 2093–2104.

[11] Patton, G., et al., “Graded SiGe Base Poly-Emitter Heterojunction Bipolar Transistors,”IEEE Electron Device Letters, Vol. 10, No. 12, 1989, pp. 534–536.

[12] Koester, S., et al., “High Ft n-MODFETs Fabrication on Si/SiGe Heterostructures Grown byUHV-CVD,” IEEE Electron Device Letters, Vol. 21, No. 3, March 2000.

[13] Singh, R., Harame, D., and Oprysko, M., Silicon Germanium Technology, Modeling, andDesign, New York: IEEE Press and Wiley Interscience, 2004.

[14] Cressler, J. D., and Niu, G., Silicon-Germanium Heterojunction Bipolar Transistors,Norwood, MA: Artech House, 2003.

[15] Rickelt, M., et al., “Influence of Impact-Ionization-Induced Instabilities on the MaximumUsable Output Voltage of Si Bipolar Transistors,” IEEE Transactions on Electron Devices,Vol. 48, No. 4, April 2001, pp. 774–783.

[16] Johnson, E., “Physical Limitations on Frequency and Power Parameters of Transistors,”RCA Review, Vol. 26, June 1965.

[17] Veenstra, H., et al., “Analysis and Design of Bias Circuits Tolerating Output Voltages aboveBVceo,” IEEE J. Solid State Circuits, Vol. 40, No. 10, October 2005, pp. 2008–2018.

[18] Casalta, J., et al., “Substrate Coupling Evaluation in BiCMOS Technology,” IEEE J. SolidState Circuits, Vol. 28, 1997, pp. 598–603.

[19] Mayaram, K., “Substrate Noise Coupling Modeling and Applications to RF VCOs,” IEEESCV SSC Meeting, November 2000.

88 SiGe HBT Fabrication Technology

C H A P T E R 6

Passive Circuit Design

6.1 Low-Pass Filters

RFICs are capable of fabricating a wide variety of passive RF/microwave circuits.The most important class of passive devices is filters (low pass, high pass, and bandpass). However, phase shifters and power splitters (and couplers) are also designedand fabricated successfully on RFICs. This chapter is devoted to the details of pas-sive circuit designs. Armed with this capability, the designer will be in a position torealize a significant portion of a system, on-chip; or perhaps the whole system.

We first consider the design of low-pass filters. Figure 6.1 gives the schematicdiagram of a single-section low-pass filter (LPF). The inductors are easy to realize inan RFIC by using spiral inductors, and the capacitor is simply an MIM capacitor inan RFIC environment. Of course, all layout parasitic elements must be accountedfor to ensure close agreement between simulations and measurements. The basicdesign equations for a single-section LPF are given below. The design method usedhere is that of artificial transmission lines [1] of the kind used in distributed- or trav-eling-wave amplifiers [2]. To obtain higher rejection at high frequencies, it may benecessary to add additional filter sections. This is a straightforward matter of calcu-lating how much rejection at a given frequency is available from a single section,then estimating how many sections will be needed to realize the desired rejection[3]. First, the filter’s characteristic impedance, which should be set to match theimpedance of surrounding circuits, is calculated as

Z L C0 = / (6.1)

The filter’s cutoff frequency is

Fc = 1/ Z0C (6.2)

89

Figure 6.1 A schematic diagram of an ideal single-section low-pass filter based on an artificialtransmission line structure.

The value of the filter’s inductors, L, is

L = (Z0)2C (6.3)

The time delay per section is given as

τ = LC (6.4)

and the phase shift in degrees is

= –360 F0 (6.5)

The approximate frequency where filter roll-off begins is

Fh = Fc/2 (6.6)

Of course, this roll-off frequency is only an approximation and must be verifiedby simulation.

Filter phase shift at Fh is about –90° per section, and filter rejection at Fc (i.e., 2 ×Fh) is about 10 dB per section.

As an example, consider the design of a single-section low-pass filter, assumingthat

Fh = 3 GHz.Z0 = 50Ω.Fc = 2 × 3 = 6 GHz, which means C = 1/ (50)(6 GHz) = 1.06 pF.L = (50)2(1.06E–12) = 2.65 nH.

The filter’s time delay is calculated as

τ = − − =( . ) ( . )2 65 9 106 12 53E E pS

The phase shift per section is calculated to be

φ = 360(3 GHz) (53 pS) = –57º

A simulator schematic for this LPF in lumped-element (prelayout) form is shownin Figure 6.2. The filter’s simulated performance is shown in Figure 6.3. Notice thatthe simulated performance closely matches the performance predicted by using (6.1)to (6.6). All that needs to be done to turn this filter into a real design is to convert itsinductors into spiral inductors and add the parasitic open-circuited stub associatedwith the shunt capacitor. Figures 6.4 and 6.5 show a very useful technique for con-verting a lumped-element inductor into a spiral inductor. A two-stage low-pass fil-ter, including spiral inductors, is shown schematically in Figure 6.6. This filter wasdesigned for an Fh frequency of 3.0 GHz (i.e., Fc = 6 GHz). The simulated perfor-mance of this filter is given in Figure 6.7. The simulations come out to be very closeto the estimated performance per stage (rejection at Fc = 20 dB, phase shift at Fh =

90 Passive Circuit Design

–180°), demonstrating that even after conversion to a layout-ready spiral inductor,the estimated performance of a multistage LPF is very similar to the performancecalculated from the design equations.

6.1 Low-Pass Filters 91

Figure 6.2 A schematic diagram for a single-section low-pass filter with a 3 GHz roll-off fre-quency.

Figure 6.3 The simulated S-parameters of a single-section low-pass filter.

Figure 6.4 A simulator schematic diagram for transforming an ideal inductor into a spiral induc-tor based on comparing the value of inductive reactance at the frequency (or frequencies) of inter-est.

92 Passive Circuit Design

Figure 6.5 A comparison of the simulated reactance of an ideal inductor with that of a physicalspiral inductor, making it possible for the spiral inductor to replace the ideal inductor when theirreactance is made equal at the frequency (frequencies) of interest.

Figure 6.6 The schematic diagram of a two-section, 3 GHz, roll-off-frequency, low-pass filter withspiral inductors replacing the ideal inductors.

Figure 6.7 The simulated S-parameters of the two-section low-pass filter using spiral inductors.

6.2 High-Pass Filters

A schematic diagram of a single-section high-pass filter (HPF) is shown inFigure 6.8. We recognize that this filter is simply the inverted dual of the LPF dis-cussed above. Therefore, the filter parameters calculated with (6.1) to (6.6) mayalso be applied to the design of its dual high-pass filter with the schematic shown inFigure 6.8. In the case of the high-pass filter, Fh is still the frequency where filterroll-off begins. However, it is at Fh/2 that a single-section HPF achieves 10 dB rejec-tion relative to Fh. The phase shift at Fh with the high-pass filter is +90°, instead ofthe –90° associated with the equivalent LPF dual. This characteristic makes it possi-ble to design a balun (a single-ended-to-differential conversion device with 180°phase shift) by using an equivalent LPF/HPF pair fed at a common point anddesigned to operate at Fh (see section 6.7).

One stage of a two-stage HPF designed for Fh = 3 GHz is shown schematically inFigure 6.9. This filter can use spiral inductors and is “buildable” in InGaP/GaAstechnology by simply including the back plate parasitic element associated witheach capacitor.

Figure 6.10 shows the simulated performance of this filter. The filter’s insertionloss is under 0.1 dB at Fh, and its rejection at Fh/2 is nearly 30 dB. The total phaseshift is 180°. Like the two-stage LPF, the two-stage HPF design has simulated per-formance very near what is calculated from the design equations multiplied by two.

6.3 Band-Pass Filters

There are two ways to construct RF band-pass filters (BPFs). The first is simply tocascade the low-pass and high-pass filter designs discussed above. The pass band of

6.2 High-Pass Filters 93

Figure 6.8 A schematic diagram of an ideal single-section high-pass filter based on an artificialtransmission line structure.

Figure 6.9 The schematic diagram of a 3 GHz, roll-off-frequency, two-section high-pass filterwith spiral inductors replacing ideal inductors.

the resulting filter will be determined by the difference between the Fh of thelow-pass filter and the Fh of the high-pass filter. High-end rejection at the 2Fh associ-ated with the low-pass filter will depend upon the number of LPF stages (it will beapproximately N × 10 dB, where N is the number of LPF sections). Low-end rejec-tion at Fh/2 associated with the high-pass filter will depend on the number of HPFstages (again, approximately N × 10 dB, where N is the number of HPF sections).This technique is very effective in designing band-pass filters because the filter’sbandwidth and the high-frequency and low-frequency roll-offs are determined inde-pendently and are controlled by different design parameters. This is a powerful plusfor choosing this kind of BPF topology in RFIC designs. Figure 6.11 shows a sche-matic diagram of a BPF designed using this technique for combining the two-stageLPFs and HPFs discussed above. The simulated performance of the resulting BPF isshown in Figure 6.12. The high- and low-end filter rejection is almost exactly whatwas already simulated for the LPF and HPF operating separately, demonstratinghow independently these filters behave, even when combined into a BPF cascade.Notice also that the LPF and HPF phase shifts nearly cancel each other out toabout 0°.

A second technique for designing lumped-element band-pass filters involves theuse of multiple parallel LC resonator sections loosely coupled together with smallseries capacitors. The LC resonator sections may be “stagger-tuned” in order toachieve the desired BPF bandwidth. Of course, increased resonant-frequency sepa-ration between the resonators will result in increased pass-band ripple. The trick isto use enough resonators so that the in-band ripple is not too great, while achievingthe desired roll-off characteristics. Too many resonators will increase the chip’s areaand add insertion loss, while two few resonators will result in excessive band ripple.

94 Passive Circuit Design

Figure 6.10 The simulated S-parameters of a 3 GHz, roll-off-frequency, two-section high-pass filter usingspiral inductors.

The schematic diagram for this type of BPF is shown in Figure 6.13, and its simu-lated performance is given in Figure 6.14. While this type of filter is highly interac-tive, making it difficult to design, it can yield excellent performance with few partsin a very compact layout.

6.4 Differential Filters

Often RFICs use a totally differential topology because components such as Gilbertcell mixers, differential VCOs, and differential amplifiers are naturally suited to acompletely differential environment. To remain consistent with this technique,components such as filters must also be designed in a differential format. If all com-

6.4 Differential Filters 95

Figure 6.11 The schematic diagram of a two-section low-pass filter cascaded with a two-sectionhigh-pass filter forming a band-pass filter. This filter uses spiral inductors throughout.

Figure 6.12 The simulated S-parameters of a two-section high-pass filter cascaded with a two-sectionlow-pass filter to form a band-pass filter. The center frequency of this band-pass filter is 3.0 GHz, withapproximately 800 MHz of flat bandwidth.

ponents can be kept strictly differential, the only differential-to-single-ended trans-formations that need be made can be done off-chip, using surface-mounted baluns.

Fortunately, it is not difficult to convert filter designs from single-ended to dif-ferential. This requires only that, during the simulations of these filters, the designerprovide two center-tapped transformers (whose center taps represent the filter’svirtual ground) and place between them two single-ended filters whose ground ref-erence becomes the virtual grounds, which are determined by the transformer’s cen-ter taps. The center taps may be connected to system ground, or they may float; ineither case, they determine the virtual ground for the filters. At the transformer’s sec-

96 Passive Circuit Design

Figure 6.13

Figure 6.14 Simulated S-parameters of a two-section parallel LC resonator band-pass filter. Thisband-pass filter has a center frequency of 2.2 GHz and a flat bandwidth of 600 MHz.

ondary winding, the differential filter is converted back to single-ended input andoutput if this is needed in simulating a number of cascaded components. Figure6.15(a) shows two such transformers connected together at their differential sec-ondary windings. Notice that the center of the circuit is at the virtual ground poten-tial. The impedance from each side to ground is exactly 50 ohms, meaning that thetotal impedance of the secondary is 100 ohms. The correct impedances are achiev-able by setting both of the transformers’ turn ratios to exactly 1.41. Figure 6.15(b)gives the overall insertion loss of the two back-to-back connected transformers.Once this is done, the secondary-to-secondary connections may be replaced by two50 ohms, matched, single-ended filters as shown in Figures 6.16(a, b). If the filterhas shunt components connected to the virtual ground (capacitors in LPFs andinductors in HPFs), these components may be considered to be in series, and con-verted into a single capacitor or a single inductor connected between the sides of thedifferential filter (see Figure 6.17). The simulation of the low-pass differential filteris shown in Figure 6.18. Notice that the differential filter behaves exactly as the sin-gle-ended filter did. If the differential filter is intended to be placed in an area of thecircuit where the impedance is significantly different than 50 ohms, it may makesense in the initial design of the single-ended filters to start off with the non-50 ohmsimpedance as a design goal, rather than to try to match the surrounding circuits tothe 50 ohms filters.

6.4 Differential Filters 97

Figure 6.15(a) The schematic diagram of two back-to-back center-tapped transformers, whichare used to facilitate the simulation of a wide variety of differential circuits.

Figure 6.15(b) The simulated insertion loss of the back-to-back transformer pair shown in Figure6.15(a). The simulated loss is vanishingly small, meaning that this technique for simulating a differ-ential circuit has no inherent loss by itself.

98 Passive Circuit Design

1.06 pF

2.65 nH

2.65 nH

2.65 nH

2.65 nH

1.06 pF

Figure 6.16(a) The schematic diagram of a differential low-pass filter formed by combining twosingle-ended low-pass filters inside a pair of back-to-back center-tapped transformers.

Figure 6.16(b) The simulated S-parameters of the differential low-pass filter shown in Figure 6.16(a). TheS-parameter performance of the differential filter is absolutely identical to that of its equivalent single-endedfilter, which is shown in Figure 6.3.

Figure 6.17 The schematic diagram of a differential low-pass filter with series-combined shuntelements at the virtual ground common point.

6.5 Technology and Substrates

InGaP/GaAs technology provides an ideal substrate for passive circuits. In this typeof process, the substrate is a true lossless insulator with an approximate thickness of100µm. Metal traces on this type of substrate will behave as standard (and highlypredictable) microstrip transmission lines [4]. However, this is not the case withSiGe BiCMOS technology (see Chapter 5) because the silicon substrates used by thistechnology are not lossless, and their proximity may affect the behavior of spiralinductors and other metal traces in ways that are not ideal. In the case of SiGe cir-cuits, the designer has several choices in approaching this dilemma. The first choiceis simply to rely on the validity (including substrate effects) of the foundry electricalmodels for resistors, capacitors, and inductors. These foundry models may or maynot include metal traces. A second approach is to use one of the BiCMOS process’smetal layers as a ground plane, essentially shielding the traces on the substrate fromlosses deep in the underlying substrate. The difficulty with this approach is that theeffective dielectric thickness may be very thin (less than 5µm), leading to narrow,therefore lossy (based on metal loss), 50 ohm lines. The designer must be preparedto exercise judgment to settle this issue.

6.6 Splitters/Dividers

Power splitters and power dividers are important components in most RFICs. Twoof the more popular designs are called in-phase splitters (Wilkinsons) and resistivedividers. The Wilkinson in-phase power splitter has approximately 3 dB insertion

6.5 Technology and Substrates 99

Figure 6.18 The simulated S-parameters of a differential low-pass filter with series-combined shunt ele-ments.

loss in each of its two outputs, producing an almost perfect half-power division. Asthe name implies, the in-phase Wilkinson divider has no differential phase shiftbetween the two outputs. All inputs and outputs are well matched to 50 ohms with aWilkinson. On the other hand, the resistive power divider uses dissipative resistorcomponents to accomplish power division. This means that power will be lost, andthere will be additional attenuation beyond the natural half division of theWilkinson. Most resistive power dividers have a 6 dB loss between input and eachoutput. Like the Wilkinson, they are well matched to 50 ohms and have zero differ-ential phase shift between the outputs.

Figure 6.19 gives the circuit schematic of a basic Wilkinson power splitter usingquarter-wavelength microstrip transmission lines. Since these lines may becomequite long at low frequencies, it is a good idea to “wrap them up” into spiralinductors, as shown in Figure 6.20. Figure 6.21 gives the simulated performance of

100 Passive Circuit Design

Figure 6.19 The schematic diagram of a Wilkinson power combiner/splitter using quar-ter-wavelength microstrip lines.

Figure 6.20 The schematic diagram of a Wilkinson power combiner/splitter using spiralinductors.

the Wilkinson power splitter using spiral inductors. The performance is very similarto that obtained with quarter-wavelength transmission lines, but the spiral splitter ismuch smaller in layout. Performance peaks up at the frequency corresponding tothe quarter-wavelength frequency associated with the spiral inductors.

Figure 6.22 shows the schematic diagram of a resistive power splitter. This is avery simple structure, using three 17 ohm resistors in a “Y” configuration. As seenin Figure 6.23, the resistive splitter offers perfect 6 dB power split with a perfectmatch and no differential phase shift over a very wide frequency range.

Both kinds of power splitters can be “run backwards” as power combiners. TheWilkinson combiner will almost perfectly add the two input powers, whereas theresistive power combiner will suffer a 3 dB loss in total power relative to its inputsbecause of its dissipative nature.

6.6 Splitters/Dividers 101

Figure 6.22 The schematic diagram of a 6 dB resistive power combiner/splitter.

Figure 6.21 The simulated three-port S-parameters of a Wilkinson power combiner/splitter usingspiral inductors.

In general, all splitters and combiners will be designed to have a 50 ohm imped-ances at their inputs and outputs. As such, it makes good sense to interconnect thesecircuits (and also filters) with metal traces whose characteristic impedance is also50 ohms. Tables of microstrip design data for various line lengths and widths can befound in several references.

Whenever spiral inductors are a part of any circuit element (especially when theyare in series with an input or output), it is good practice to use an inductor line widththat translates into a 50 ohm characteristic impedance for the metal trace function-ing as a micro strip transmission line. By following this suggestion, impedancemismatches between filters/splitters and their interconnecting metal lines can beavoided.

6.7 Phase Shifters and Baluns

It is possible to use filter structures to achieve certain kinds of advantageous phaseshifts for certain applications. For instance, as we have seen, a LPF provides exactly–90° of phase shift at Fh, whereas its dual HPF provides exactly +90° phase shift atthe same frequency. If we combine these two filters into a two-channel structure asshown in Figure 6.24, the outputs will be have 180° of phase shift relative toeach other. This is exactly the performance required of a balun (short for “balanced-unbalanced”), which is used to translate from single-ended transmission to

102 Passive Circuit Design

Figure 6.23 The simulated three port S-parameters of a 6 dB resistive power combiner/splitter.The insertion loss in both paths is exactly 6.0 dB. There is no frequency dependence because thecircuit contains no reactive elements.

differential transmission. Although baluns are often located off-chip, by using thedual LPF/HPF phase shifter, it is possible to achieve balun function in a compacton-chip environment.

Figure 6.25 gives the schematic diagram of a 90° phase shifter that makes use ofa single-section high-pass filter and a resistive splitter. This circuit can serve the roleof an LO quadrature-phase shifter in an I/Q mixer or an I/Q modulator applications(see Chapter 11). In the case of a differential LO line driving a mixer with a differen-tial LO input (such as a Gilbert cell mixer), the block diagram in Figure 6.26 showshow to connect two 90° phase shifters in order to provide 90° of phase shift at the Qmixer. An alternate 90° phase-shifter circuit using a single-section low-pass filter isshown in Figure 6.27. The low-pass, high-pass, and polyphase circuits (shown inChapter 3) are equally useful for shifting the phase of an LO signal by 90° (over anarrow band of frequencies). If a quadrature phase shift is required over a broadband of frequencies, it is best to use a digital frequency divider circuit to output ahalf frequency with quadrature outputs. The price paid for this approach is thenecessity to design a VCO to operate at two times the desired frequency.

6.7 Phase Shifters and Baluns 103

Figure 6.25 The schematic diagram of an HPF 90º phase shifter. This circuit is useful for shiftingthe phase of an LO signal by 90º in I/Q mixer/modulator applications.

Figure 6.24 The schematic diagram of an HPF/LPF balun (single-ended input and 180º phaseshift between its two differential outputs).

References

[1] Beyer, J., et al., “MESFET Distributed Amplifier Design Guide Lines,” IEEE Transactionson Microwave Theory and Technique, MTT-32, March 1984.

[2] Sweet, A., MIC and MMIC Amplifier and Oscillator Circuit Design, Norwood, MA: ArtechHouse, 1990.

[3] Nilsson, J., and Riedel, S., Electric Circuits, Upper Saddle River, NJ: Prentice Hall, 2005.[4] Edwards, T. C., Foundations for Microstrip Circuit Design, New York: John Wiley and

Sons, 1983.

104 Passive Circuit Design

Figure 6.27 The schematic diagram of an LPF 90º phase shifter.

Figure 6.26 The block diagram of a differential I/Q phase-shifting network. This network pro-duces two differential outputs that are 90º apart from each other in order to shift the phase of adifferential LO in I/Q mixer/modulator applications.

C H A P T E R 7

Amplifier Design Basics

7.1 Matching Techniques

All RF/microwave transistor amplifiers rely on some form of matching to achieveflat gain over a desired frequency range [1]. We mathematically define a conjugatematch as Γl = Γ*g, where Γg is the transistor’s reflection coefficient, and Γl is theload’s reflection coefficient. Transistors have a maximum gain that decreases as afunction of frequency. Any amplifier is designed to operate from fl to fh, with a theo-retical maximum available gain (MAG) at fh and flat gain at all frequencies betweenfl and fh. Matching for flat gain becomes a matter of providing the best possiblematch into and out of the transistor at fh (in order to achieve a gain at fh that is asclose as possible to MAG) and providing selective mismatch between fl and fh to“throw away” gain at frequencies between fl and fh to provide flat gain, which isgain as close as possible in value to MAG at fh. Selective mismatching compensatesfor the transistor’s increasing MAG as frequency decreases. Figure 7.1 graphicallyportrays the gain-compensation process over a band of frequencies from fl to fh.

If an amplifier is to operate over a narrow bandwidth, the matching problembecomes a simple matter of achieving a good match at fh. But if a broad bandwidthis needed, the selective mismatch concept must be employed to ensure flat, broadbandwidth gain. Mismatch loss, Mc, is defined as the ratio of the power availablefrom a generator to the power delivered to the load:

105

Figure 7.1 Amplifier gain equalization with the introduction of a selective mismatch loss, Lm. Thisequalization process achieves flat gain over a wide bandwidth.

Mc = [1 – ΓlΓg]2/(1 – Γl

2) (1 – Γg2) (7.1)

where

Γl is the load’s reflection coefficient.Γg is the generator’s reflection coefficient.

Mismatch may be applied at either the transistor’s input or the transistor’s out-put, or both.

7.2 Gain Compensation

The selective mismatch concept can be applied to either the circuit between the gen-erator and the input to the transistor or to the circuit between the transistor’s outputand its load. It is common practice, however, to provide a selective mismatch only atthe transistor’s input and to provide a conjugate match at the transistor’s output tomaximize the transistor’s power transfer to the load. Figure 7.2 shows a Smith chartdiagram [2] displaying how the input and the output matching circuits provide aselective mismatch to the transistor’s input (S11) and a conjugate match to the tran-sistor’s output (S22). Notice that the conjugate match is provided only to the transis-tor’s input at the highest operating frequency, fh. However, the transistor’s output isclosely matched to the load over the entire frequency range, fl to fh.

7.3 Fano’s Limit

Calculations by Fano [3] have shown there is a bandwidth limit for reactivelymatched amplifiers. Assuming that the input matching is provided by a high-pass

106 Amplifier Design Basics

F2

Zin*

Zout*

F2S11

F1

S22

F1

Figure 7.2 A Smith chart displaying the selective mismatch process of a wideband transistoramplifier.

network and the output matching is provided by a low-pass network, the gain of atransistor amplifier is given by

Ga (f) = G0 (f/fh)–k (7.2)

and the mismatch loss for flat gain from fL to fH is LM(f)=K(f/fH)k

where k is the gain reduction factor, which predicts how far below MAG, at thehigh end, the gain must be to realize flat gain over the bandwidth fl to fh.

If the high-pass input matching network is lossless and reciprocal, Fano hasshown that

( ) [ ]πτhp >∞

∫ 1 12

0/ ln /Ω Γ Ωin d (7.3)

where

Ω = f/fh = normalized frequency.

hp = 2 fhRinCin.Rin = the transistor’s input resistance.Cin = the transistor’s input capacitance.Γin = input reflection coefficient.

Equation (7.3) indicates that Γin cannot be zero over any finite bandwidth. If Γin

is sloped with frequency such that it is lower at fh (the high-end frequency) than at fl

(the low-end frequency), it can be shown that

( ) ( )[ ]1 1 1 221/ ln / ( / )Ω Ω

fl

KK f fh d∫ − < πτhp (7.4)

Figure 7.3 shows how much bandwidth is achievable with no high-end gainreduction for various degrees of input-circuit frequency slope.

For the output circuit, it can be shown that

( )[ ]ln / ( / ) /1 1 21

− <∫ K f fh dK

flΩ π τlp (7.5)

where

lp = 2 fhRoutCout.Rout = the transistor’s output resistance.Cout = the transistor’s output resistance.

Figure 7.4 shows how much bandwidth is achievable with no high-end gainreduction for various degrees of output-circuit frequency slope.

7.4 Stability

Any amplifier is unconditionally stable if the source or load impedances necessaryto cause instability are outside of the Γ = 1.0 circle (that is, unachievable without

7.4 Stability 107

some form of negative resistance). An amplifier is conditionally stable if the imped-ances that produce instability do not include 50 ohms pure real at either the input orthe output ports. A stability factor, k, of an amplifier is defined in terms of the ampli-fier’s S-parameters as [4]

k = (1 – (MAGS11)2 – (MAGS22)2 + D2)/2(MAGS11)(MAGS22) (7.6)

108 Amplifier Design Basics

Figure 7.3 Maximum Fano bandwidth of an amplifier that is limited by its input (high-pass) cir-cuit. No reduction in gain relative to MAG can occur at the high-frequency limit. The most com-mon input-circuit roll-off slope is 6 dB per octave per stage.

Figure 7.4 Maximum Fano bandwidth for an amplifier that is limited by its output (low-pass) cir-cuit. No reduction in gain relative to MAG can occur at the high-frequency limit. The most com-mon input-circuit roll-off slope is 0 dB per octave per stage.

where

S11 and S22 are the amplifier’s complex input and output S-parameters.D = (S11S22 – S12S21)For unconditional stability, k > 1.0.For conditional stability, 0 < k < 1.0.

If the designer is to be sure that an amplifier design is unconditionally stable atall frequencies, it is very important to test stability over a very broad range of fre-quencies, not just the frequencies within the specified bandwidth. Oftentimes, insta-bility problems occur at frequencies far below the intended operating range.

7.5 Noise Match

Matching a transistor amplifier for lowest possible noise figure over a band of fre-quencies requires that a particular impedance be presented to the transistor’s input.The noise-optimized source impedance is called Γopt, which may be obtained frommeasurements or from the transistors manufacturer’s data sheet. The noise figure ofa transistor amplifier with an arbitrary source reflection coefficient, Γ, is givenby [5]

F = Fmin + 4Rn[Γ – Γopt]2/[1 – (sq MAGΓ)][1 + Γopt]

2 (7.7)

where

Fmin = the transistor’s minimum noise figure.Rn is the transistor’s noise resistance, normalized to 50Ù.Γ is the source’s reflection coefficient.Γopt is the ideal source reflection coefficient for minimum noise figure.

7.6 Differential Amplifiers

Differential amplifiers are of great general value in RFIC design because so many ofthe current RFIC architectures are built around Gilbert cell mixers, which require acompletely differential circuit approach. For this reason, many LO buffer amplifiersand gain block amplifiers that interface directly to Gilbert cell mixers are requiredto be differential. It is usually very desirable for these amplifiers to have high reverseisolation so that mixing products generated in the Gilbert cell are not transferredback into the rest of the system, where they can cause self-generated spuriousresponses. An example of a basic differential amplifier topology is shown in Figure7.5. As shown in Figure 7.5, a differential amplifier circuit makes use of two emit-ter-coupled transistors, Q1 and Q2, whose dc current is controlled by a “tail” tran-sistor. The tail transistor acts as a source of dc current and, at the same time, as a

7.5 Noise Match 109

high-RF impedance, suppressing the common mode signal. The resistors, Rb (typi-cally about 5k), are a part of the base-biasing circuit. From the Eber-Moll equation[6], it can be shown that for identical transistors

Ic1/Ic2 = exp(Vid/VT) (7.8)

where

Vid = ( )V Vin in+ −− .

VT = thermal voltage (25 mV at 300K).

The output voltages are

Vout+ = Vcc – Ic1Rc (7.9)

Vout− = Vcc – Ic2Rc (7.10)

The differential output voltage is

Vod = (Vout+ – Vout

− ) = fItailRctanh(–Vid/2VT) (7.11)

where F1 = F2 = F (assuring identical transistors), and Rc is the collector load resis-tance.

Since Vid is zero when Vod is zero, if identical transistors and resistors are used,this circuit allows direct coupling of identical stages without creating offset voltages.

If a differential RF signal is presented to the differential amplifier’s input, avoltage gain may be calculated for the amplifier.

By representing the transistor as a transconductance, Gm, it can be shown that

Vod = –2GmRc(Vid/2) (7.12)

110 Amplifier Design Basics

Figure 7.5 The schematic diagram (transistor level only) of a basic differential amplifier circuit.The tail transistor controls the dc current of the two “top” amplifying transistors. The 5K feedbackresistors connected from the transistor’s base to its collector are for promoting stability.

It follows that the amplifier’s differential voltage gain is given as

Ad = Vod/Vid = –GmRc (7.13)

Referring to Figure 7.5, transformers are used to create and uncreate the differ-ential signals. Figure 7.6 shows the simulated gain of the differential amplifier as afunction of frequency.

The amplifier consists simply of a differential pair of identical transistors whosecurrents are controlled by the “tail” transistor. The collector terminations arepurely resistive. In many cases, differential amplifiers can become unstable at highgains. For this reason, a resistor network provides parallel feedback between thecollector and the base of each transistor in the differential pair. The values of thefeedback elements are chosen to ensure unconditional stability over a wide fre-quency range while maintaining high gain. Typical performance of a differentialamplifier is shown in Figure 7.6. If the amplifier is placed in front of a receivingmixer, noise figure will become a very important consideration. Differentialamplifiers are capable of achieving very low noise figures and can serve as LNAs.

7.7 Cascode Amplifiers

Cascode amplifiers derive their name from the original vacuum-tube version of thecircuit, which consists of the “cascade” of two vacuum tubes in such a way that acommon cathode tube and a common grid tube are joined such that the “anode” ofthe first tube is connected to the cathode of the second tube (i.e., the tubes are“cascoded”). This arrangement has the ability to increase output resistance and, atthe same time, reduce unwanted feedback associated with parasitic capacitance.

Cascode amplifiers may be constructed in either single-ended or differentialform. A differential version of a cascode amplifier is shown in Figure 7.7. For anequivalent single-ended cascode amplifier, the input resistance is

7.7 Cascode Amplifiers 111

Figure 7.6 The simulated gain and stability for the basic differential amplifier circuit shown inFigure 7.5.

Ri = r 1 (7.14)

Following P. Gray it can be shown that the cascode amplifier’s output resistance is

Ro = r02(1 + Gm2 r02/ ) (7.15)

where

= (1 + Gm2 r01/ 0).r01 is the common emitter transistor’s (Q1,Q2) output resistance.r02 is the common-base transistor’s (Q3,Q4) output resistance.Gm2 is the common-base transistor’s (Q3,Q4) transconductance.

0 is the transistor’s dc current gain.

If Gm2 r01 >> 0 and 0 >>1, (7.15) reduces to

R0 = r02 (7.16)

Therefore, the two transistors connected in cascode have an output resistancethat is larger by a factor of 0 than the output resistance (r02) of the common emittertransistor alone. If we assume a very high collector load resistance, Rc, the cascodeamplifier has a voltage gain of

Av = Vo/Vi = –GmRo = –Gm 0r02 (7.17)

Therefore, a cascode amplifier has a voltage gain that is higher than the voltagegain of a single transistor amplifier (–Gm r02) by a factor of 0. This additional gaincan be very useful in a wide variety of applications. Figure 7.8 shows the simulatedpower gain for this circuit, while working into a high impedance load (similar tovoltage amplification).

112 Amplifier Design Basics

Figure 7.7 The schematic diagram (transistor level only) of a differential cascode amplifier circuit.Notice the common-base connection of the “top” two transistors and that large capacitors areused to connect the top transistors’ bases to ground in order to achieve common-base operationover a wide range of frequencies.

References

[1] Vendelin, G., Design of Amplifiers and Oscillators by the S-Parameter Method, New York:John Wiley and Sons, 1982.

[2] Smith, P., Electronic Applications of the Smith Chart, New York: McGraw-Hill, 1969.[3] Fano, R., “Theoretical Limitations on the Broadband Matching of Arbitrary Impedances,”

J. Franklin Institute, Vol. 249, January 1960, pp. 57–83, and February 1960, pp. 139–155.[4] Vendelin, G., et al., Microwave Circuit Design Using Linear and Nonlinear Techniques,

New York: John Wiley and Sons, 1990.[5] Razavi, B., RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.[6] Gray, P., et al., Analysis and Design of Analog Integrated Circuits, New York: John Wiley

and Sons, 2001.

7.7 Cascode Amplifiers 113

Figure 7.8 The simulated gain, reverse isolation, and stability of the differential cascode amplifiershown in Figure 7.7 Notice that with the cascode-amplifier circuit configuration, the gain is higher,the isolation is higher, and the stability is improved relative to a basic differential amplifier circuit.

C H A P T E R 8

Low-Noise Amplifier Design

8.1 Noise Figure Concepts

It is the purpose of low-noise amplifiers (LNAs) to amplify weak signals beingreceived directly from an antenna and to amplify them sufficiently, adding a mini-mum of additional noise, so that the signals may be efficiently processed and theirinformation content extracted with a minimum of errors. LNAs are usually locatedas the first stage of a receiver; therefore, they receive input signals directly from theantenna.

The effectiveness of a low-noise amplifier is specified by an important metriccalled noise figure (NF). Figure 8.1 provides a plot of signal level and noise level as afunction of frequency to help explain the concept of noise figure. At the receiver’sinput, the signal level, S, is above the noise level, N, by a ratio called the sig-nal-to-noise ratio, S/N. Typically, thermal noise power at the input of a receiver isgiven by

N = kTB (8.1)

where

k = 1.38E–23 J/K.T is the ambient temperature in degrees kelvin.B is the receiver’s bandwidth in hertz.

115

Figure 8.1 The noise figure of an LNA is defined as the ratio of SNR at the amplifier’s input to theSNR at the amplifier’s output. A perfect LNA (one that adds no noise to the signal it is amplifying)would have a noise figure of 1.0 (or 0.0 in decibels).

The LNA’s noise figure is defined as the ratio of signal-to-noise power at theinput of the LNA, divided by the ratio of signal-to-noise power at the output of theLNA.

NF = (S/N)in/(S/N)out (8.2a)

Noise figure may be expressed in decibels by using the following expression:

NF (dB) = 10log[(S/N)in/(S/N)out] (8.2b)

If the LNA internally generated absolutely no noise, NF would equal exactly 1.0in numbers (or 0.0 dB). This is because both the signal and the noise are amplified bythe amplifier’s gain, and their ratio will be unchanged. However, in any real ampli-fier, the electronics within the LNA will contribute some amount of noise output,making the signal-to-noise ratio at the output less than the signal-to-noise ratio atthe LNA’s input. This situation is demonstrated graphically in Figure 8.1. Any sig-nal passing through a realistic (nonideal) LNA encounters noise generated withinthe LNA’s circuitry. The signal-to-noise ratio at the LNA’s output is degraded bythis noise, raising the noise figure. An elevated noise figure means that, at the output,the noise power will be greater than simply the noise input times the amplifier’s gain.In fact, the noise output from a low-noise amplifier is given by

Nout = (NF) GkTB (8.3)

where G is the amplifier’s gain.

8.2 Noise Temperature

In certain highly specialized applications, such as radio astronomy and deep-spacecommunications, LNAs must have extremely low noise figures in order to receivethe weak signals required by these applications. The difference between an 0.80 and0.60 dB noise figure may make a great deal of difference in overall system perfor-mance. Since, numerically, such small differences are difficult to measure, a differentsystem of specifying noise has evolved within these highly specialized applicationswhich is called noise temperature [1]. Noise temperature is simply a measure ofwhat the ambient temperature of the environment would have to be to account fullyfor all noise sources with in the LNA. Since many internal noise sources within theLNA are directly related to the ambient temperature of the LNA’s components, inmany cases the physical temperature of these “super LNAs” is reduced with cooling(liquid nitrogen or liquid helium). Cooled LNA’s for radio astronomy applicationsmay have noise temperatures as low as 30°K. It is much easier to compare andunderstand the difference between 30°K and 100°K than to comprehend the differ-ence between 0.35 and 0.70 dB.

Noise figure can be converted to noise temperature using the following equation

Tn = T0 (NF – 1) (8.4)

116 Low-Noise Amplifier Design

where T0 is the ambient temperature of the environment (about 290ºK).Noise temperature may be converted back to noise figure with the following

expression

NF = (1 + Tn/T0) (8.5)

8.3 Front-end Attenuation and LNAs

Sometimes there is signal attenuation between the antenna and the LNA in manyreceiver systems. Connectors and transmission lines all have some degree of attenu-ation. Also, devices such as band-pass filters and switches may precede the LNA andadd to the overall noise figure. Such attenuation affects noise figure profoundlybecause the attenuation reduces the signal level, but not the noise level, whichalways remains at kTB. Figure 8.2 shows how a signal from an antenna passingthrough a front-end attenuation (A) will already experience a decrease in sig-nal-to-noise ratio in direct proportion to A. Therefore, A will reduce the sig-nal-to-noise ratio of the receiver’s front end by reducing the signal level into theLNA, and the LNA will reduce the front end’s signal-to-noise ratio by raising thenoise power associated with the signal. The combined effect will yield a noise figureexpressed in decibels as

NF (attenuation plus LNA) = [A + NF (LNA only)] (8.6)

8.4 Multistage Noise Figure Contributions

In the multistage amplifier shown in Figure 8.3, the opposite situation to front-endattenuation is encountered. The first stage amplifies the signal to a level significantlyabove the noise level in the second stage. For this reason, the second stage’s contri-bution to the LNA’s noise figure is diminished by the gain of the first stage. In thesame way, the noise-figure contribution of the third stage is diminished by the gain

8.3 Front-end Attenuation and LNAs 117

Figure 8.2 Attenuation in front of an LNA reduces overall SNR by reducing the signal thatreaches the LNA. The reduction in SNR, caused by attenuation, raises the overall noise figure of theattenuator plus the LNA by exactly the amount of attenuation. If calculated in decibels, the overallnoise figure is simply the noise figure of the LNA, in decibels, plus the attenuation in decibels.

of the first and the second stages. The total noise figure (in numbers) for a multistageamplifier is given below.

NF (total) = NF1 + (NF2 – 1)/G1 + (NF3 – 1)/G1G2 + … (8.7)

Equation (8.7) tells us that the first stage is absolutely critical in determining anLNA’s noise figure, both in terms of its noise figure but also in terms of its gain. Thesecond stage’s contribution to total noise is divided by the gain of the first stage. Allfollowing stages have noise-figure contributions that are divided by factors evenlarger than the second stage. It is good practice to design the first stage of an LNAwith over 10 dB of gain. This ensures that the second- and all-subsequent-stage con-tributions will be reduced by a factor of ten as a minimum. Referring to Figure 8.4,we see that second-stage contributions can also be calculated for LNAs that arespecified in terms of a noise temperature. The total noise temperature of a multistageLNA is

Tn (total) = Tn1 + Tn2/G1 + Tn3/G1G2 + … (8.8)

8.5 Circuit Topologies for Low Noise

Before discussing LNA circuit topologies, it is necessary to discuss physical sourcesof noise in the transistors that comprise the active devices in these amplifiers [2].

There are three principle physical sources of noise in bipolar transistors:

1. Thermal noise: Pn = kTB (8.9)

2. Shot noise: mean square noise current = qIdcB (8.10)

3. 1/f or flicker noise: mean square noise current = qIdcB/f (8.11)

118 Low-Noise Amplifier Design

Figure 8.3 Second- and third-stage contributions to the noise figure of a multistage LNA arereduced by the gains of the first and second stages. Therefore, it is important for at least the firststage of a cascaded LNA to have the highest possible gain.

Figure 8.4 Noise temperature is an alternative way to express noise figure. Noise temperature isoften used to express the noise performance of extremely low-noise LNAs, such as those used inradio astronomy.

where k is Boltzmann’s constant, and q is the charge on an electron.Figure 8.5 shows the spectrum of each physical source of noise. Notice that both

thermal and shot noise are white noise sources, meaning that their noise power den-sity does not change with frequency. However, as its name implies, 1/f noisebecomes quite strong at low frequencies and gradually declines as frequencyincreases. Figure 8.6 is a typical LNA noise figure plotted against frequency, show-ing how these physical sources of noise are affected by the filtering effects at work inthe amplifier’s matching circuits. An important frequency is the 1/f noise corner fre-quency. The corner frequency is that frequency where the 1/f noise contributionbecomes just equal to the “white” sources of noise, like thermal noise and shotnoise. At frequencies below the corner frequency, the amplifier’s noise figure isdominated by 1/f noise, but above the corner frequency, the amplifier’s noise figurebecomes dominated by one or both of the “white” noise sources.

We now briefly discuss the physics of these three noise sources. 1/f noise is aresult of so-called trapping states that exist just below the conduction band energylevel in the semiconductor’s energy band structure. These energy states are locatedin the so-called forbidden band and are not available for conduction. Trapping lev-els are often associated with impurity atoms in the crystal structure of the transistor.Often, these impurities are located on the surface of the crystal, although they may

8.5 Circuit Topologies for Low Noise 119

Figure 8.5 The spectrum of the three most important physical sources of noise in electronic cir-cuits: thermal noise, shot noise, and 1/f noise.

Figure 8.6 The noise-figure spectrum of a typical LNA, showing a 1/f region at low frequenciesand a thermal noise (or shot noise) region at high frequencies. The high-frequency region hasincreasing noise figure as a result of increasing circuit attenuation at higher frequencies. The fre-quency where minimum noise figure occurs is called the noise corner frequency.

be found in the bulk of the crystal as well. Referring to Figure 8.7, we see that thetrapping states can “capture” conduction electrons and hold them hostage for a verylong time. While hostage, these electrons are not available for conduction, so a cur-rent spike occurs whenever one of these “trapped” electrons is either trapped orreleased from a trap. The time constant of the trap depends on how far below theconduction band energy, Ec, the trap is located. Traps with energies nearly equal toEc are very slow and release their captured electrons after a very long time. Trapswith energies significantly below Ec are much faster and capture and release theirelectrons much more quickly. The net effect is for many time constants to be at workat the same time, making a “smear” of noise power within frequency, with thegreater power appearing at low frequency. 1/f noise can be a big problem with manykinds of transistors, especially transistors in the field-effect family. However, bipo-lar transistors have much less susceptibility to 1/f noise than their field-effect cous-ins. Saying this in numbers means that field-effect transistors have cornerfrequencies ranging from 10 to 500 MHz, while bipolar transistors have a cornerfrequency that ranges from 100 Hz to 100 KHz—a difference of almost five ordersof magnitude. In applications where low 1/f noise is of critical importance (likelow-phase-noise VCOs), bipolar transistors have a distinct advantage over theirfield-effect cousins.

Thermal noise is a direct result of the thermal agitation of the electron gas withinany conductor. This noise source is also called resistor noise because it was firstobserved in resistors. Thermal noise is associated with any resistive region or struc-ture within an RFIC. In general, it is not the dominant source of noise in bipolardevices. That distinction is left for shot noise. Referring to Figure 8.8, we see that, ina bipolar transistor, carriers fall through the potential gradients at both the collec-tor-to-base junction and the base-to-emitter junction. The electrons in these regionsbehave like individual charged particles, and as they pass through the junction, theeffect of each one’s contribution to current is a little like big rain drops falling on atin roof in a heavy rain storm. They create a loud noise as their individual impactsblend with all of the other electron impacts all around them. This so-called shotnoise (the name association is with bird shot falling on a roof like rain drops, butlouder) has a mean square current intensity proportional to the average dc current

120 Low-Noise Amplifier Design

Figure 8.7 1/f noise in electronic devices is caused by trapping states on the surface of the semi-conductor, alternately capturing and releasing carriers, with a distribution of time constants. Theseoverlapping noise spectra, with wide distributions of corner frequencies (the inverse of the timeconstants), tend to average out to a 1/f-behaving spectrum over a wide frequency range.

multiplied by the charge e of a single electron times the measurement bandwidth, asgiven in (8.10). It turns out that shot noise is the dominant noise source in bipolartransistors, and since shot noise is proportional to dc current, it is vary advanta-geous in bipolar LNA circuits to keep the dc bias current in all transistors to anabsolute minimum. In bipolar transistors, both base current and collector currentcan serve as the source of shot noise.

While shot noise sources are at a minimum, the noise figure also includes thetransfer function of the transistor since noise figure depends on the ratio of the totalnoise compared to the noise of the input source. Noise due to collector shot noiseincreases more slowly than noise from the input source as the collector currentincreases [3]. Therefore, higher collector current may reduce the effect of collectorshot noise on overall noise figure. Noise due to base shot noise increases more rap-idly than noise from the input source as the base current increases, so, in this case,low dc base current helps to reduce overall noise figure. Noise associated with thebase resistance increases at the same rate as noise from the input source. Therefore,at low dc current, the noise figure may be improved by raising the dc current todecrease the effects of collector shot noise. As the dc current increases, eventuallythe base shot noise dominates, and the overall noise figure increases. For any partic-ular transistor size, there is an optimum dc current for achieving the lowest possiblenoise figure. The input impedance for achieving a minimum noise figure depends ondevice size. Often, an optimum device size can be determined that simultaneouslyproduces minimum noise figure and matches the transistor to a 50 ohm load formaximum gain.

LNAs are like any other amplifier circuit requiring input and output matchingfor maximum gain; in addition, however, LNAs require input mismatch to insurethe lowest possible noise figure in the first stage. In Figure 8.9, we see that the matchfor minimum noise figure is somewhat displaced from the match for maximum gain(conjugate of S11). This displaced matching impedance is called Γopt and is locatedat about the same angle as conjugate S11, but at about half the magnitude of S11.This is only a rule of thumb, and the exact impedance of lowest noise figure can onlybe found by using the device’s large-signal model to predict gain and noise figure

8.5 Circuit Topologies for Low Noise 121

Figure 8.8 With bipolar transistors, the primary noise source is the shot noise generated in boththe base region and the collector region. Both Gummel Poon and VBIC device models allow accu-rate simulation of shot noise effects.

based on the exact impedance presented to the transistor’s input and output by thematching networks.

A low-noise amplifier requires matching circuits like any other amplifier. Theoutput matching network is normally designed for maximum gain, minimum S22,based on small-signal conditions. The exception is so-called high dynamic rangeapplications, which require an LNA that has both a low noise figure and a relativelyhigh third-order intermodulation intercept point (OIP3). This type of amplifiershould be designed like an LNA at its input and like a PA at its output.

A more conventional LNA requires a certain amount of intentional mismatch atits input in order to present Γopt to the transistor’s input. In many cases, it is purely amatter of choosing a well-understood matching topology and adjusting it carefullyuntil the transistor’s minimum noise figure is obtained. This process is not as easy asit sounds and can sometimes be quite challenging. A key point to remember is thatany loss element in front of the LNA’s transistor will serve to introduce attenuationat the LNA’s input, which adds directly to the overall noise figure. For this reasonalone, elements with high loss should be avoided in the LNA’s input matching struc-ture. Matching elements, such as spiral inductors, can be major contributors to noisefigure because of the metal loss associated with their structure. In designs seeking thelowest possible noise figure, it sometimes makes sense to use off-chip matchinginductors in the amplifier’s input circuit to avoid losses in this critical area. Manyexcellent surface-mount inductors are available with practically no electrical loss.

A brief word about device models is in order at this point [4]. Both the GummelPoon and VBIC devices include all noise mechanisms within their parameter set. Solong as the factory has measured the device’s 1/f noise and included parameters inthe device model, both types of scalable large-signal device models will fully accountfor the effects of thermal, shot, and 1/f noise, However, not all foundry modelsinclude 1/f parameters, so the designer must check with the foundry to be sure.

The actual matching topology may be one of the standard types, such aslow-pass and high-pass matching. Figure 8.10 shows the topology of alow-pass-matched LNA. Both the amplifier’s input and output use nearly identicalsingle-section low-pass-matching structures. Base bias is provided by an RF chokeconnected to a high-value resistor and a low-voltage base-bias supply. Collector biasis provided by a single RF choke. Optimization of this circuit proceeds from the

122 Low-Noise Amplifier Design

Figure 8.9 The input match for achieving a transistor’s minimum noise figure (Γopt) may not bethe same as the input match for achieving the transistor’s maximum gain (S11*).

input to the output. The first step is to adjust the input matching network for mini-mum noise figure and, at the same time, the maximum gain that can be associatedwith minimum noise figure. The simulator’s optimization function can be very use-ful in this regard, but the designer must be very careful to set the goal in a reasonablefashion to be sure that the best compromise between minimum noise figure andmaximum gain is actually accomplished. Once the input matching network hasbeen optimized, the output matching network is tuned to provide a minimum valueof MAG[S22], which corresponds to matching for maximum gain in the amplifier’soutput circuit. Once both input and output matching circuits have been optimized,the amplifier needs to be analyzed for stability. If there are problems, stabilizationelements, such as series RL and series RC networks, must be introduced into thetopology to cure these problems. It is very important to be very careful not to com-promise noise figure when adding stabilization networks (see Chapter 9).

Sometimes feedback can be helpful in stabilizing an LNA. Figure 8.11 gives theschematic diagram of an LNA similar to the one that has just been described butwith the addition of parallel feedback. These feedback elements must be applied“sparingly” to avoid the feedback resistor’s loss contributing to the LNA’s noisefigure. This is best accomplished by maintaining this resistor at a high value. How-ever, properly applied, parallel feedback can be a powerful tool in achieving excel-lent overall LNA performance.

The alternative form of feedback is series feedback in the form of an inductorplaced between the transistor’s emitter and ground. This circuit option is shown inFigure 8.12. This particular type of series feedback is called emitter degenerationand is of particular interest in LNA design because emitter degeneration has thecapacity to move Γopt closer to conjugate [S11], which means that by applying thistype of feedback, the designer may have the freedom to have his or her cake and eatit too in the sense that minimum noise figure and maximum gain may be achievableat the same time with this technique. In addition, because the match is movingcloser to achieving a perfect match relative to S11, it is possible by using this tech-nique to achieve excellent MAG[S11] at the same time as achieving minimum noisefigure and maximum gain. Of course, as always, stability remains an issue, and onlywhen the optimum matching conditions for best performance and unconditionalstability have been achieved simultaneously is a final, successful design produced.

8.5 Circuit Topologies for Low Noise 123

Figure 8.10 The schematic diagram of a single-stage LNA, making use of low-pass filter elementsin both its input and output matching circuits.

Following B. Razavi [5], it is possible to analyze how to obtain the lowest noisefigure and an excellent input match to 50 ohm simultaneously by using inductiveemitter degeneration. Refer to Figure 8.13 for a schematic diagram of this LNA’scircuit. The input-referred mean-squared noise voltage per unit bandwidth for thiscircuit is (based on the input circuit shown in Figure 8.12)

Vn2 = 4kT(Rb + 1/2Gm) (8.12)

where

k is Boltzmann’s constant (1.38E–23 J/K).T is the temperature in degrees kelvin.Rb is the transistor’s base resistance.Gm is the transistor’s transconductance.

This expression may be expanded to include the base shot noise for aninput-referred noise source resistance including that of Rs, as

124 Low-Noise Amplifier Design

Figure 8.11 The schematic diagram of a single-stage LNA making use of both low-pass input andoutput matching elements and parallel feedback to achieve maximum gain, minimum noise fig-ure, best match, and good stability—all simultaneously.

Figure 8.12 The input circuit of an LNA that is used to calculate the effects of emitter inductanceseries feedback (emitter degeneration) on gain and noise figure.

Vnt2 = 4kT(Rs + Rb + 1/2Gm + GmRs

2/2 ) (8.13)

where is the transistor’s current gain.The input impedance of this circuit is

Zin = Rb + GmLe/C + Le – 1/ C (8.14)

where

Le is the emitter degeneration inductance.C is the transistor’s shunt input capacitance.ω is 2π times frequency

By making the proper selection of Le and C it is possible to make the last twoterms in (8.14) cancel out, leaving the input impedance as simply

Zin = Rb + GmLe/C (8.15)

By correctly choosing Rb, Gm, Le, and C , Zin can be set to exactly 50 ohms, toprovide an excellent input match.

The LNA’s noise figure is calculated as the ratio of the amplifier’s input referrednoise voltage Vnt, divided by the source’s thermal noise.

NF = Vnt2 /4kTRs = 1 + Rb/Rs + 1/2GmRs + GmRs/2 (8.16)

The LNA’s noise figure reaches a minimum of

NFmin = 1+sqr[(1 + 2GmRb)/ ] (8.17)

When the source’s resistance is set to its optimized value, Rs opt,

Rs opt = sqr[ (1 + 2GmRb)]/Gm (8.18)

This result ignores the effect of parasitic capacitance.

8.5 Circuit Topologies for Low Noise 125

Figure 8.13 The schematic diagram of a single-stage LNA that uses an inductive emitter degener-ation technique to achieve improved balance between lowest noise figure and maximum gain at agiven frequency.

An estimate of the transistor’s high frequency can be made as follows:

= Ft/F (8.19)

where Ft is the transistor’s current gain cutoff frequency, and F is the frequency ofoperation. Of course, accurate values of noise figure, match, and gain as a functionof frequency must ultimately be obtained from simulations.

LNA projects must balance the sometimes conflicting demands of noise figure,gain, match, intermodulation intercept point, and stability with the device’s size.Ordinarily, a small device with minimum collector current is used in LNAs in orderto minimize both shot noise and 1/f noise. However, this straightforward approachdoes not always yield the best overall performance. Sometimes a slightly largerdevice with less-than-usual current per finger gives better overall results. Someexperimentation on the designer’s part is necessary to arrive at the final best combi-nation of factors that contribute to an optimized final design. The simultaed perfor-mance of the amplifier circuit shown in Figure 8.13 is given in Figure 8.14.

8.6 Design Example 1: Single-Ended PCS LNA

Very effective LNAs can be designed using a combination of input and outputmatching and parallel feedback. This amplifier’s topology is shown in Figure 8.15.The amplifier uses low-pass matching circuit elements consisting of a single series

126 Low-Noise Amplifier Design

Figure 8.14 The simulated S-parameters and noise-figure performance of the LNA circuit shownin Figure 8.13. The design frequency is 3.8 GHz.

inductor and a single shunt capacitor at both its input and its output. The seriesinductors could be on-chip spiral inductors for compactness; however, in the case ofan LNA, it makes more sense to have at least the input inductor placed off-chipsince off-chip, surface-mounted, wire-wounded inductors have significantly higherQ than on-chip spiral inductors can possibly have. The reason for the inherentlylow-Q nature of the “on-chip” inductors is that the spiral inductor winding tracemetal is very thin, and is subject the high metal losses associated with skin effects.

An additional key circuit element in this LNA is a parallel feedback networkprovided by a series RC circuit connected between the transistor’s base and its col-lector. This network enhances stability and improves the amplifier’s input and out-put match. The amplifier’s transistor is sized to be very small in order to keep the dccollector current as low as possible in order to minimize the shot noise contributionto noise figure. For this design, a single-finger InGaP/GaAs transistor is the onlytransistor in the LNA. During simulations, both the input and output matching ele-ments and the feedback network may be optimized to achieve the best combinationof gain, noise figure, and match over the band of interest. In the case of this design,performance has been optimized for the 1.7–2.5 GHz band, which includes the PCS,3G, and WiFi b bands. Simulated gain is about 15 dB over this frequency range,with a noise figure of about 2.8 dB. The input and output match (S11 and S22) are–10 to –15 dB across this frequency band. Graphs of simulated gain, noise figure,and match as a function of frequency are shown in Figure 8.16. Details of the ampli-fier’s layout (showing the placement of the transistor, the resistors, and the capaci-tors) are shown in Figure 8.17.

8.7 Design Example 2: Three-Transistor Hybrid Darlington DifferentialLNA Using SiGe Technology

An excellent single-ended (or as an option differential) broadband LNA can bedesigned using just three transistors and four resistors. The single-ended topologyfor this hybrid Darlington LNA is shown in Figure 8.18. The amplifier is capable of

8.7 Design Example 2 127

Figure 8.15 The schematic diagram of a single-stage LNA for PCS applications. This LNA makesuse of parallel feedback and low-pass matching circuits. The input and output series matchinginductors are located off-chip in order to achieve maximum Q to minimize noise figure by mini-mizing front-end losses. This circuit uses InGaP/GaAs technology.

30 dB gain from dc to over 6 GHz with InGaP/GaAs technology and over 30 dBfrom dc to 12 GHz with SiGe technology. The LNA’s noise figure ranges from about1.5 dB at 2 GHz to 2.5 dB at 6 GHz. The SiGe designs operate at 3.0V dc, whileInGaP/GaAs designs operate at 4.0V to 5.0V.

The following design rules apply in determining the values of R1, R2, R3, and R4.All three transistors are of equal size. For lowest noise figure, use very small (per-haps minimum-size) transistors. If power output and/or OIP3 (see Chapter 9) are

128 Low-Noise Amplifier Design

Figure 8.17 The layout of the PCS LNA shown in Figure 8.15.

Figure 8.16 The simulated S-parameter and noise figure of the single-stage PCS LNA shown inFigure 8.15.

important considerations, the size of Q1, Q2, and Q3 must be increased until thedesired value of P – 1 dB and/or OIP3 is obtained. The values of R1, R2, R3, and R4

should be adjusted to make all transistor dc currents approximately equal. For low-est possible noise figure, very low dc current should be used in all transistors. Forhighest possible power output and OIP3, the transistor’s dc current should be setclose to the maximum allowable current. The value of R1 determines the dc currentsin transistors Q1 and Q2. Values of R3 and R4 determine the current in transistor Q3.As a starting point, R3 is approximately equal to Vbe/IQ2.

Once the dc levels are set, the design can proceed to simulating RF performance.These simulations, using SiGe technology, are shown in Figure 8.19. The microstriptransmission line MLIN should be adjusted to achieve the best possible S11 over the

8.7 Design Example 2 129

R1=500

10 pFIN

Q1 Q2 Q3

10 pFOUT

A=2 A=2 A=2

R2=800

R3=250

10 nH

R4=10

Vcc=3.0 V

Figure 8.18 The schematic diagram of a single-ended, “Darlington-like,” broadband LNA usingthree transistors and InGaP/GaAs technology.

Figure 8.19 The simulated S-parameters and noise figure of the “Darlington-like” LNA shown inFigure 8.18.

desired band of interest. With the single-ended LNA, it is very important to takemuch care in determining the amplifier’s stability. With this topology, any commonmode inductance between the amplifier’s ground and system ground will degradestability significantly and must be avoided. For this reason, this particular topologyis best suited to be used as a differential LNA, where common mode inductance isvirtually nonexistent. For receiver architectures using Gilbert cell mixers, the differ-ential LNA is an ideal situation because the mixer’s input terminals are naturally dif-ferential, exactly matching the differential outputs of the LNA. A layout of thesingle-ended LNA (using InGaP/GaAs technology) is shown in Figure 8.20.

Figure 8.21 shows a block diagram for the differential LNA. Notice that allgrounding points tie together at a common “virtual” ground, preventing stabilityproblems caused by stray common mode inductance.

Figure 8.22 shows the small-signal performance of the differential LNA usingSiGe technology device models. Notice that owing to the higher Ft of the SiGedevices, the LNA’s gain using this technology is relatively flat from dc to 15 GHz.The SiGe version of this LNA can only be modeled here using ideal lumped-element

130 Low-Noise Amplifier Design

Figure 8.20 The layout of the three-transistor “Darlington-like” LNA shown in Figure 8.18. Inputis on the left.

Figure 8.21 The block diagram of a differential broadband, “Darlington-like” LNA using SiGetechnology.

devices because of a lack of foundry models based on the normally conductive SiGesubstrate. Actual foundry models, including lossy substrate effects, may reduce per-formance.

A simulation of Pin versus Pout, showing the P – 1 dB point is given inFigure 8.23. Also, a simulation of OIP3 versus frequency is shown in Figure 8.28.Notice that the simulated value of OIP3 and P – 1 dB are both approximately +15

8.7 Design Example 2 131

Figure 8.22 The simulated S-parameters and noise figure of the differential “Darlington-like”SiGe LNA shown in Figure 8.21.

Figure 8.23 The simulated Pin versus Pout and 1 dB compression point of the “Darlington-like”SiGe LNA shown in Figure 8.21.

dBm. This is an unusual situation since most amplifiers have at least a 10 dB spreadbetween OIP3 and P – 1 dB. However, in the case of this particular LNA, linearityhas been sacrificed for noise figure, gain, and bandwidth. In some applications, thismay be a good trade-off; in other applications, more robust linearity is demanded bya difficult multisignal environment. This particular LNA topology is very strong inits wideband gain and noise-figure capabilities but relatively weak in terms of its lin-earity performance. It is very important for the designer to keep these limitations inmind before deciding to use this particular topology.

References

[1] Lee, T., The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge: Cam-bridge University Press, 1998.

[2] Van Der Ziel, Fluctuation Phenomena in Semi-Conductors, London: Butterworth’s Scien-tific Publications, 1959.

[3] Gray, P., et al., Analysis and Design of Analog Integrated Circuits, New York: John Wileyand Sons, 2001.

[4] Matthias, M., Introduction to Modeling HBTs, Norwood, MA: Artech House, 2006.[5] Razavi, B., RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.

132 Low-Noise Amplifier Design

C H A P T E R 9

Power Amplifier Design

Power amplifiers are used in wireless telecommunications systems to boost thepower of transmitted signals to a sufficiently high level for “on-the-air” transmis-sion. This means that power amplifier output power levels must be high enough toovercome antenna path losses such that sufficient signal-to-noise ratio is availableat the receiver’s input to support the desired range. For mobile handheld equipment,power amplifier output is typically in the range of 100 mW to 5W. Base stationpower amplifiers are often required to have power outputs in the range of 10W to50W.

Often, power amplifiers are composed of a cascade of individual power ampli-fier stages, each of which elevates the transmitted power to a yet higher level. Withinfrastructure power amplifiers, as many as ten stages may be necessary to generatethe required full-transmit power.

A very important fundamental trade-off exists with power amplifiers betweentheir dc-to-RF conversion efficiency and their linearity. Both conversion efficiencyand linearity are important performance specifications in many applications. Effi-ciency is inversely related to dc current, so the battery life of a handheld devicedepends critically on conversion efficiency. On the other hand, a power amplifier’slinearity is a principle factor in determining the bit-error rate of the overall radiolink because of the potential for signal distortion inherent in amplifier nonlinearity.Such distortions lead directly to bit errors, which compromises the radio link.

Some modulation types, such as CDMA, are more sensitive to the effects ofnonlinearity than are other modulations (GSM modulation, for example, is quiteinsensitive to PA nonlinearity). Therefore, CDMA systems require that some sacri-fice be made in the conversion efficiency of PAs in order to assure the highest possi-ble PA linearity. For this reason, CDMA handsets are directed by their cellular basestations to use the minimum transmitted power for acceptable signal-to-noise ratioin an effort to improve battery life. However, GSM power amplifiers (in mobileunits) are typically run at high, constant power output (2W to 4W) because the highconversion efficiency of PAs designed for GSM service reduces dc current consump-tion and therefore extends battery life.

These trade-offs between conversion efficiency and linearity are a direct resultof the kind of current and voltage waveforms developed in a particular amplifierdesign. If these waveforms are very nearly sine waves, the amplifier will be highlylinear since no new frequencies are being created within these waveforms. This typeof operation is called “class A” and is characterized by a high level of amplifier lin-earity but not the highest possible conversion efficiency. In class A operation, the

133

perfectly symmetric sinusoidal RF waveforms are incapable of reducing losses dur-ing the “unproductive” portion of the RF cycle. Therefore, in pure class A opera-tion, a power amplifier’s conversion efficiency is limited to a theoretical maximumof 50 percent.

Higher classes of power amplifiers (classes AB, B, C, D, E, and F) make use ofnonsinusoidal RF waveforms to reduce the losses during “unproductive” portionsof the RF cycle. However, these higher amplifier classes pay the price of inherentlyhigher nonlinearity associated with their nonsinusoidal waveforms.

Today, most wireless telecommunications equipment makes use some form ofphase modulation. As discussed in Chapter 3, these various phase modulationsrequire a highly linear power amplifier to minimize distortions and their resultingbit errors. For these reasons, most wireless telecommunications power amplifiersoperate in pure class A, or in those cases where a little more nonlinearity can be tol-erated, in class AB. As a result of the paramount important of class A in most wire-less applications, it will be this class of amplifiers that is discussed in greatest detailin this chapter. However, a brief discussion of class AB amplifiers will be presenteddue to the favorable trade-off they offer between efficiency and linearity.

9.1 Loadline Concepts

In order to achieve maximum RF power, maximum dc-to-RF conversion efficiency,and best linearity at the same time, it is important to make use of an approach to PAdesign that requires the use of an optimum device loadline that determines thedetails of the transistor’s collector matching network [1]. These loadlines may becalculated directly from the device’s static IV curves, or they may be inferred fromthe dynamic behavior of the device’s voltages and currents under large-signal simu-lation. It is by careful application of the loadline concept that an RF power amplifiercan be designed to achieve high power output, high efficiency, and high linearitysimultaneously.

Power amplifiers are often distinguished according to classes. The following is abrief list of the properties of a number of power amplifier classes [2]:

1. Class A: Class A is the most popular class of power amplifiers for wirelesscommunications applications. This is the most linear mode of poweramplifier operation. Class A power amplifiers have a maximum dc-to-RFconversion efficiency of 50 percent.

2. Class AB: Class AB power amplifiers are a hybrid between the highlylinear class A amplifiers and the more efficient, but more nonlinear, classB amplifiers. Class AB power amplifiers can have up to 60 percentefficiency.

3. Class B: Class B power amplifiers are somewhat nonlinear but haveimpressive dc-to-RF conversion efficiencies—up to 75 percent.

4. Class C: Class C amplifiers are very efficient (up to 85 percent) but are highlynonlinear.

134 Power Amplifier Design

5. Class D, E, and F: Class D, E, and F amplifiers are switching-modeamplifiers. These highly efficient amplifiers (85 to 95 percent) are sononlinear that they may not even have a small-signal gain region in theiroperating characteristics.

A widely accepted form for expressing dc-to-RF conversion efficiency in apower amplifier is power-added efficiency (PAE), expressed as

PAE = (Pout – Pin)/Pdc (9.1)

where

Pdc = Vdc × Idc.Vdc and Idc are the total dc voltage and dc current supplied to the amplifier bythe power supply.

As with all amplifiers, maximum gain is obtained with a power amplifier whenits device’s input and output are matched to the external source and load imped-ances (encountered by the amplifier’s connection to its surrounding system).Figure 9.1 gives a simplified circuit diagram showing how the input and outputmatching networks are designed to provide conjugate match to the input of thedevice (S11) and the output of the device (S22). These matches for high gain maynot be the best matches for maximum power and efficiency. At the output, they defi-nitely are not the best match for maximum power and efficiency (see Figure 9.2).Figure 9.2 contains a Smith chart display of the input and output matches with“contours” of constant power output. These impedance contours show how thematch affects power. It turns out that in most cases, the input match has very littleeffect on power output and efficiency. But the opposite is true with the outputmatch. The conjugate match at the output for maximum gain relative to thedevice’s small-signal output impedance (S22) is displaced considerably from theimpedance where maximum power is obtained. Notice that the impedance formaximum power is on the real axis of the Smith chart and has a relatively lowvalue. This is typical of class A power amplifiers. Next, we consider ways toestimate the optimum load impedance of a transistor to achieve maximum powerand efficiency.

9.1 Loadline Concepts 135

Figure 9.1 When matching an amplifier for narrowband operation, networks M1 and M2 providea conjugate match to the transistor’s input and output in order to realize maximum gain at a givenfrequency.

9.2 Maximum Power and Efficiency

Maximum power and efficiency can be obtained only by providing the correct loadto a power amplifier’s transistor. This correct load for obtaining maximum powerand efficiency is called the loadline resistance. A loadline resistance may be calcu-lated directly from the device’s static IV curves. Figure 9.3 gives an example of abipolar transistor’s dc IV characteristic curves. This particular set of curves was gen-erated using a large-signal VBIC device model. Gummel Poon device models canalso be used for this purpose.

Now, we consider the construction of a loadline for maximum power and effi-ciency in class A operation. This graphical construction is shown in Figure 9.4. Theloadline must be centered on the device’s dc operating point, which is at Vce = Vdc

136 Power Amplifier Design

Figure 9.3 The simulated IV curves of a single emitter cell in a InGaP/GaAs transistor based on ageneric VBIC device model.

Figure 9.2 When matching for maximum gain, the conjugate matches (S11* at the input andS22* at the output) must be provided by networks M1 and M2. However, when matching formaximum power output, it is found that maximum power output occurs for an output match thatis considerably different from S22* and is often pure real and quite low in value.

along the collector-to-emitter voltage axis and at Ic=Idc along the collector currentaxis. In order to maintain best-possible power output, efficiency, and linearity, it iscritical that the RF voltage and current swings always stay in the “saturated cur-rent” portion of the device’s IV curves. This means the RF voltage must never swinginto the resistive region that exists below the knee voltage (Vk). At the high-voltage,low-current extreme of the RF signal swing, the instantaneous voltage must neverexceed the device’s collector-to-emitter breakdown voltage (BVceo). If these two con-ditions are met, the device will remain in a very linear portion of its characteristiccurves. The purpose of the output matching circuit is to present an optimumloadline resistance to the device’s collector-to-emitter terminals so that the aboveconditions are always in force. The slope of the loadline resistance is determined byconnecting the highest current that does not fall into the resistive region below theknee voltage, Vk, and the highest possible RF voltage that does not enter the break-down region, BVceo. In order to center this loadline resistance, it is necessary todetermine the dc operating point’s voltage and current. The dc voltage will be deter-mined by the available power-supply voltage in a given application, while the cur-rent will be determined by the maximum safe and reliable collector current based onthe chosen device’s size. If the device has to be resized in order to increase its poweroutput, the loadline resistance must be recalculated. In the same way, if the dc volt-age is changed for any reason, the loadline resistance must be recalculated. Figure9.5 shows the completed loadline construction, including sine wave voltage andcurrent waveforms. It is important that the output waveform always be a sine wavebecause sine waves contain only one frequency, which is the condition for optimumlinearity in the overall amplifier. We are now in a position to develop a set of equa-tions that define a power amplifier’s loadline resistance plus the resulting poweroutput and efficiency. Based on the above graphical constructions, the loadlineresistance is

Rl = (Vdc – Vk)/Idc (9.2)

And the dc power is

Pdc = Vdc × Idc (9.3)

9.2 Maximum Power and Efficiency 137

Figure 9.4 The graphical construction of an output loadline, Rl, for a bipolar transistor operatingin class A.

The output power is equal to

Pout = Vrms × Irms cos(phase angle) (9.4)

Assuming a phase angle of zero (that is a pure real load),

Pout = (Vdc – Vk)2/2Rl (9.5)

And the dc-to-RF conversion efficiency (collector efficiency) is

EFF = Pout/Pdc = (Vdc – Vk)/2Vdc (9.6)

For Vdc much greater than Vk, (9.6) tells us that a class A power amplifier’s effi-ciency approaches 50 percent in the limit. Power amplifiers always benefit from highsupply voltage in terms of both power output and efficiency. If the supply voltage islow, the value of the loadline resistance is reduced accordingly, placing a burden onthe output matching network to perform a higher transformation ratio from theexternal system impedance, which is usually 50 ohms. While a supply voltage of3.0V is often all that is available in battery-powered, handheld wireless equipment,from the viewpoint of power amplifier design, it is a liability that must be overcomewith clever design techniques. For a given power output, such a low-voltage power

138 Power Amplifier Design

Figure 9.5 The voltage and current waveforms associated with the class A loadline at the signalamplitude level where power output reaches its maximum value. Notice that both waveformsremain perfect sine waves up to this point. At higher signal levels, both the voltage and the currentwaveforms will suffer clipping, causing considerable distortion and nonlinearity in the output sig-nal.

amplifier would have to operate at very high current swings to make up for the lowvoltage swings constrained by the low supply voltage. An additional liability withlow supply voltage is lowered dc-to-RF conversion efficiency as a direct result of theconsiderations in (9.6). When operating with low supply voltages, the resistiveregion of the device’s characteristic curves becomes an increasingly higher percent-age of the overall voltage swing, decreasing both power output and efficiency.

The peaking of power output, efficiency, and linearity at the optimum loadlineresistance is shown graphically in Figure 9.6. Since (9.4) tells us that power is maxi-mized for zero phase angle between Vrf and Irf (i.e., cos(phase angle) = 1.0), we see inFigure 9.7 that when Rl is placed on a Smith chart, it is always on the real axis, andin many cases it assumes a low resistive value that is very close to a short circuit.

9.3 Class AB Power Amplifiers

Many applications, such as GSM mobile phones, require power amplifiers withhigher power-added efficiencies normally achievable with class A amplifiers. Theseamplifiers are able to make the corresponding sacrifices in linearity because of therelaxed linearity requirements of their application. Class AB is an excellent compro-mise since it offers realistic efficiencies of up to 60 percent with only minor reduc-tions in linearity.

9.3 Class AB Power Amplifiers 139

Figure 9.6 The maximum power output, maximum power-added efficiency, and best linearity(as measured by OIP3 and ACPR) will occur when the amplifier’s RF amplifier transistor is con-nected to a load resistance of Rlopt.

Figure 9.7 To insure that the product of the voltage and current waveforms generates the maxi-mum possible available power, Rlopt must be pure real (being on the real axis of the Smith chart).

In class A operation [3], the RF transistors are turned on for 100 percent of theRF cycle (i.e., the conduction angle for class A is a full 360°). This high-duty condi-tion leads to high collector current and a correspondingly reduced efficiency. On theother hand, in class AB the collector current is reduced somewhat, and it is antici-pated that the RF transistors will be turned on for less that 360°. This implies that inclass AB, the RF transistors will be turned off for some phase interval, which is typi-cally somewhere between 0° and 180°. The quiescent collector current in class ABoperation lies somewhere between 0 and 0.50 Imax, whereas the quiescent current forclass A operation is always 0.50 Imax (see Section 9.2).

Since the class AB collector current is turned off for some portion of the RFcycle, the RF current waveform is “clipped” during the downward-going part of thecycle. This clipped current waveform approaches a half-wave-rectified sine wave inthe limit of 180° of turned-off angle. In this limit, class AB smoothly approachesclass B operation. At the other extreme, class AB operation smoothly approachesclass A operation in the limit as the turned-off phase angle approaches 0° (seeTable 9.1 for a summary of PA classes of operation).

Since the class AB current waveform is distorted by its current waveform clip-ping, it is necessary to perform a Fourier analysis on the waveform to determine thepeak sinusoidal current at the fundamental frequency. Also, the dc current must bedetermined in a similar way by Fourier analysis. It can be shown that

( ) ( )I I d V V ddc q s= + +

∝

∝

∫∫max / cosπ θ θ θδ

0

(9.7)

where Imax is the transistor’s maximum collector current, and θ is the phase angle.Following S. Cripps [2], is the clipping angle defined as

cos( = (1 – Vq)/Vs

and cos( ) /δ = −V Vq s

Vs is the signal voltage amplitude for maximum “unclipped” operation, andVq = 1 – Vs. is the “turned-on” phase angle.

In a similar way, the fundamental component of the current waveform is

( ) [ ]I I d V V dq s10

2= + +

∝

∝

∫∫max / cos cos cosπ θ θ θ θ θδ

(9.8)

As in the case of class A operation, the dc power, loadline resistance, RF poweroutput, and power-added efficiency of a class AB amplifier are given by

140 Power Amplifier Design

Table 9.1 PA Modes of Operation

ClassConduction Anglein Degrees Quiescent Current

A Exactly 360 0.5 IMAXAB 180–360 0–0.5 IMAXB Exactly 180 0C 0–180 0

Pdc = Vdc Idc (9.9)

Rl = V1/I1 (9.10)

Prf = (Vdc – Vk) I1/2 (9.11)

Efficiency = I1/2 Idc (9.12)

where ( )V V Vdc k1 = −

9.4 Definitions of Nonlinear Performance Metrics

Most RFIC amplifiers for wireless communications applications require a highdegree of linearity to fulfill their architectural role within an advanced digital com-munications system. It is very important that we devise a set of linearity metrics thatspecify the linearity of a power amplifier [4]. Also, it is important when comparingalternative approaches to power amplifier design to have available certain linearitymetrics that can be used to compare design options.

The first linearity metric to be considered is power saturation. As shown inFigure 9.8, a power amplifier’s input power is plotted against its output power. Asthe power level increases, a phenomenon known as saturation occurs. Saturationcauses the output power to no longer to follow the input power in an exact 1:1fashion [5]. Above a certain power, called the N dB compression point, the poweroutput no longer responds to increases in the power input and assumes a nearly con-stant value. While the choice of N is arbitrary, the most popular value for N is 1 dB.Quite often, an amplifier’s saturation is described in terms of its 1 dB compressedpower output and its ultimate saturation power output. In certain applications, itmay be meaningful to use other values for N, such as 3 dB. Another important lin-earity metric is harmonic distortion of the kind shown in Figure 9.9. As the signallevel increases, the amplifier’s transistors are exercised into their nonlinear regions,generating harmonics, sometimes to the fourth or fifth order. These harmonic pow-

9.4 Definitions of Nonlinear Performance Metrics 141

Figure 9.8 A graph of power input versus power output for a typical class A power amplifier,showing the regions of gain compression and power saturation.

ers become increasingly strong as the power input to the amplifier approaches thesaturation level. We clearly see this behavior at work in the plots of the second andthird harmonic shown in Figure 9.9. As a practical matter, harmonics are rarely aproblem in wireless applications because of the inherently narrowband nature ofthese applications. Therefore, any harmonics can easily be eliminated by placing alow-pass filter at the power amplifier’s output. However, in some applications, suchas UWB systems, it may not be so easy to eliminate harmonics by filtering. In thiscase, the amplifier’s power level may need to be reduced to avoid the detrimentaleffects of high harmonic power in the amplifier’s output [6].

We next consider the phenomenon of intermodulation. Intermodulation occurswhen two input signals are amplified simultaneously by a common power amplifier.These signals will mix within the amplifier’s nonlinearity to create new signals at fre-quencies above and below the input frequencies. Figure 9.10 shows an experimentalsetup for measuring two-tone intermodulation. The two input signals (the two“tones”) are of equal power and separated in frequency by a small delta (∆ = F1 – F2).When these two signals are amplified, an output spectrum, as shown in Figure 9.11,is generated that contains the two amplified “tones,” plus third-order, fifth-order,

142 Power Amplifier Design

Figure 9.10 The experimental setup for measuring two-tone intermodulation products and theOIP3 of a power amplifier.

Figure 9.9 Harmonic output power increases as a power amplifier is driven harder in order toapproach its maximum power output. This is one of the symptoms associated with the increasingnonlinearity encountered as the signal levels increase.

and perhaps seventh-order intermodulation sidebands. The intermodulation pro-cess produces only odd-order products in frequency due to their mathematicalorigins in a general power-series description of the device’s nonlinearity. Notice thatin the amplifier’s output spectrum, new frequencies (the intermodulation products)are arranged both above and below the two original tones in frequency. All prod-ucts are spaced in frequency by ∆ = F1 – F2, both above and below the two original“tones.” The amplified two-tones are far stronger than either the third- orfifth-order intermodulation products. As the input power is increased, this ratiodecreases because (due to its nonlinear nature) the intermodulation process pro-duces intermodulation products that increase more quickly than the linear two-tonepower. We can plot power input versus power output for both the two-tones andtheir intermodulation products, as shown in Figure 9.12. In the case of third-orderintermodulation products (which in practice are the highest and most troublesome),the intermodulation increases at a 3:1 rate with increasing input power, whereas thelinear two-tone power increases at a 1:1 rate. This difference in rate of increasemeans that if we project the third-order products to high input powers (using astraight line projection), these projected intermodulation products will, at somepoint, intersect the more slowly increasing two-tone power. This point of intersec-tion, called the intercept point, is shown in Figure 9.12. On the output side of theamplifier, the intercept point is called OIP3 for third-order products, and OIP5 for

9.4 Definitions of Nonlinear Performance Metrics 143

Figure 9.12 A graphical construction often used to calculate a power amplifier’s OIP3.

Figure 9.11 The two-tone intermodulation spectrum at the output of a power amplifier, showingthe third- and fifth-order intermodulation products.

the fifth-order products. Once the intercept point has been determined, the ratiobetween the two-tone output power and the intermodulation product output powercan be calculated from the following equation:

/2 = OIP3 – Pout (9.13a)

where is the ratio in decibels between the third-order intermodulation productsand the two-tone power, and Pout is the power output of the two-tones.

In a similar way, the fifth-order intercept point can be used to determine theratio between the fifth-order products and the two-tone power by using the follow-ing equation:

/4 = OIP5 – Pout (9.13b)

Having determined OIP3 (and/or OIP5) by measurement or simulation, twoadditional important metrics can be defined. These metrics are very useful for com-paring and contrasting power amplifiers of different designs. The first metric iscalled scaled linearity and is defined as

Scaled linearity = (OIP3 – P – 1 dB) (9.14)

Scaled linearity offers a way to specify how linear an amplifier is, independent ofits power output. Therefore, by using the scaled linearity metric, one can comparethe relative linearity of two power amplifiers of greatly different power outputs.This is a very useful technique for projecting the usefulness of a given amplifier cir-cuit to higher or lower powers than were encountered in the original design.

A second important linearity metric is called linear efficiency. Linear efficiencyis defined as

Linear efficiency = 10log(OIP3/Pdc) (9.15)

where OIP3 is the third-order output intercept point given in numbers (watts ormilliwatts), and Pdc is the amplifier’s dc input power expressed in units of watts ormilliwatts.

Linear efficiency is a measure of how effectively the dc power input to a poweramplifier is used for producing linear amplification. Of course, different applica-tions are better characterized by the use of one metric over another, but all areimportant [7]. There is no set of rules governing which set of metrics is best to use ina specific application. This selection will be made by the designer after a carefulreview of the requirements and specifications of a particular application.

It is important to know what level of performance metrics can be expected withdifferent types of bipolar power amplifiers. Amplifiers with input and output match-ing and/or feedback can be expected to deliver efficiencies (PAE) of 40 to 50 percentwhen operating in class A. Darlington (unmatched) amplifiers can deliver 15 to 25percent PAE. Both kinds of amplifiers can be expected to deliver scaled linearity inthe 10–15 dB range (depending on frequency). Matched amplifiers are capable ofhaving linear efficiency in the 5–15 dB range; however, Darlington amplifiers oper-ate with significantly lower linear efficiencies (on the order of 0 to 5 dB). GaAs HBT

144 Power Amplifier Design

and SiGe devices operate in very similar ways except for supply voltage. Because ofthe much lower Vbe associated with SiGe (approximately 0.70V as opposed to1.40V with GaAs HBT), these devices may have significant performance advan-tages at low supply voltages.

9.5 Adjacent Channel Power Ratio

In many kinds of wireless systems, there is a type of linearity metric called adjacentchannel power ratio (ACPR) that is very closely linked to overall system perfor-mance [8]. An ACPR specification must be met if the equipment containing thepower amplifier is to meet the goals of the system as a whole. ACPR is a measure ofhow efficiently a power amplifier (as well as other system components such as mix-ers) can suppress its nonlinear tendency to create intermodulation sidebands fromthe complex modulation spectrums associated with the standard system formatscurrently used in wireless communications. The level of intermodulation is of vitalimportance because, when transmitted, this energy represents noise to the users ofadjacent channels. In order to prevent these noisy sidebands from becoming the lim-iting factor of the system’s overall signal-to-noise ratio, restrictions must be placedon their strength within the various network standards. In particular, the standardsfor CDMA systems contain very challenging ACPR specifications directly affectingthe linearity requirement of the system’s transmitting power amplifiers. This is trueof both base station power amplifiers and mobile (handset) power amplifiers.ACPR has come to be regarded as one of the key system specifications in many wire-less systems and is of paramount concern for power amplifier designers. Figure 9.13shows the spectrum of a power amplifier that is driven by a CDMA source. At lowinput power, the spectrum of output signal has adjacent channel sidebands that arefar below the power contained in the main channel’s spectrum. However, at high

9.5 Adjacent Channel Power Ratio 145

Figure 9.13 The spectrum of CDMA modulation as it appears for small-signal PA operation andfor large-signal PA operation. The power levels in the adjacent channel sidebands increase pro-foundly at large-signal levels.

input (and output) power, the power contained in these adjacent channels increasesquickly relative to the main channel power. In some cases, it may be necessary toturn down the amplifier’s power output (called “back-off”) in order to meet a givenACPR specification. Typical ACPR specifications for CDMA applications are on theorder of –45 dBc for the first adjacent channel and –55 dBc for the second adjacentchannel. Although ACPR is related to two-tone intermodulation, it is only corre-lated with OIP3 in practice and must be measured and simulated in its own right,not inferred from two-tone intermodulation data (see Chapter 10).

9.6 Error Vector Magnitude

Error vector magnitude (EVM) provides a measure of how much phase distortion isoccurring when an I/Q signal containing digital information is passed through acomponent or through a complete system. Within the constellation diagram of aphase-modulated signal (such as BPSK to QPSK), there are a number of phase stateswhose selection encodes the information contained in each symbol. This informa-tion remains undistorted only if the system’s output phase vectors arrive in exactlythe same position on the constellation diagram as did the phase vectors at the inputof the system. If the output signal has “shifted in phase” significantly relative to theinput vectors (as shown in Figure 9.14), an error vector is generated that can causebit errors. Since the error vector is of arbitrary phase, it is specified as a magnitude,which can be thought of as a fixed-length vector sweeping out in a circle centered onthe original phase state locations. EVM is caused by both phase nonlinearity withinthe device or system and phase noise that is added to the output vector. Phase noiseappears as a noise arc surrounding the initial phase state. Both phase nonlinearityand phase noise can cause bit errors. EVM is a very important metric in specifyingthe performance of WiFi and UWB systems. All high-data-rate, phase-modulatedsystems are subject to the limitations posed by the error vector magnitude of the sys-tem’s components.

146 Power Amplifier Design

Figure 9.14 A graphical representation of EVM as a vector whose magnitude represents the dif-ferences between an ideal phase vector at the input of a power amplifier and the actual phase vec-tor that appears at the amplifier’s output.

9.7 Circuit Topologies for PAs

The typical unit of measure for power amplifier output power is the milliwatt.Expressed in decibels, the power output relative to a 1 mW reference is given by

dBm = 10log(power in milliwatts) (9.16)

Most applications specify RF power in dBms. The first step in determining achoice of circuit for a power amplifier is to determine the load resistance that theoutput matching circuit must present to the collector terminals of the amplifier’s RFtransistor. This step requires knowledge of both the supply voltage and the transis-tor’s IV curves. It is also important to know the transistor’s dc current limit, basedon reliability considerations, and its collector-to-emitter breakdown voltage. Giventhis information, the load resistance for the transistor may be determined graphi-cally as shown in Figure 9.15 or by using (9.2). As demonstrated in Figure 9.15, it issometimes useful to calculate the loadline resistance for the unit transistor (just oneemitter), then scale the loadline resistance to larger transistors by simply dividingthe unit cell loadline resistance by the total number of unit cells (number of emitterfingers). Once Rl is determined, the designer is in a position to synthesize an outputmatching network to provide the optimum output match to the transistor forobtaining maximum power output, best linearity, and highest efficiency.

As an example, let us consider the design procedure of a simple power amplifier.We assume an output power of 1W is needed for the application. Let us assume thatour amplifier will be operating in Class A at maximum efficiency for that class,which is 50 percent. This means the dc supply power must be 2W. Let us assume theavailability of a 6.0V dc power source. This implies the amplifier’s dc current (Ic) isequal to 2W divided by 6V, which is 333 mA. If we assume a GaAs HBT processthat has a maximum current per transistor unit cell of 10 mA, we know that ouramplifier must have at least 333/10 = 33 transistor unit cells (emitter fingers) in thefinal amplifier stage. Based on the single-emitter-finger loadline calculation given in

9.7 Circuit Topologies for PAs 147

Figure 9.15 Using IV curves generated by a generic Gummel Poon model for a single unit cellInGaP/GaAs transistor, the loadline resistance is determined to equal 580 ohms per cell for opera-tion at Vcc = 6.0V and Ic = 10 mA. For a larger transistor, consisting of N unit cells in parallel, theloadline resistance is calculated as 580/N ohms.

Figure 9.15, we can calculate the loadline resistance necessary for our amplifier toproduce maximum power and efficiency, as 580/33 = 17.5 ohms.

This simple calculation tells us that based on 6V operation in class A, our ampli-fier must use a transistor with at least thirty-three emitter fingers in the final stage,and the output matching network must transform the 50 ohms external load imped-ance down to 17.5 ohms to be presented to the transistor’s collector-to-emitter ter-minals. The schematic shown in Figure 9.16 may be used to synthesize an outputmatching circuit to provide a loadline resistance of 17.5 ohms. Let us assume a sim-ple series L, shunt C matching network as shown in Figure 9.16. Assuming an oper-ating frequency of 2.5 GHz, it only takes a couple of iterations to home in on thefinal values for this simple matching circuit. The final choices are a series inductor of1.5 nH and a shunt capacitor of 1.7 pF. Figure 9.17 shows a Smith chart display ofthe impedances produced at 2.5 GHz by selecting these matching element values.

148 Power Amplifier Design

Figure 9.16 A schematic diagram useful for synthesizing a matching circuit that provides therequired loadline resistance at the transistor’s collector terminal.

Figure 9.17 The Smith chart display of the simulated loadline resistance provided by the match-ing network shown in Figure 9.16.

9.8 Matching Circuit Options

Although the simple series L, shunt C matching network worked well in the previ-ous example, it is important to be aware of various matching topologies that can bevery useful in a wide variety of power amplifier applications. Roughly speaking,these matching networks are grouped into three types: low-pass-like, high-pass-like,and band pass. Examples of low-pass matching networks are shown in Figure 9.18.Examples of high-pass matching networks are shown in Figure 9.19. Examples ofband-pass matching networks are shown in Figure 9.20. All of these networks maycontain multiple sections with the accompanying increase in complexity. It shouldbe said from the beginning that the best matching circuit is the simplest one. If youcan get full performance with only a series inductor and a shunt capacitor, why notstay with that topology? Increasing the complexity of any circuit greatly increasesthe chance of problems, thereby greatly decreasing the likelihood of success. For thisreason, it is very important to always, as a matter of course, stay with the simplestdesign. Add components or sections only when you have become convinced that thecircuit cannot be made to work in any other way.

9.8 Matching Circuit Options 149

Figure 9.18 Two examples of low-pass output matching networks.

Figure 9.19 Two examples of high-pass output matching networks.

9.9 Stability

Stability (and instability) is a major issue with any kind of amplifier. Positive feed-back paths within an amplifier’s circuitry may cause the amplifier to become unsta-ble at some frequency, possibly far removed from the design frequency. Instability ofany kind is a major problem with amplifiers since these oscillations in effect renderthe amplifier useless for its designated purpose of amplification. Stability is mea-sured by using a metric called the “k” factor (see Chapter 7). An amplifier is said tobe unconditionally stable if its k factor is greater than 1.0 at all frequencies. If theamplifier’s k factor is less than 1.0 but greater than 0, the amplifier is said to be con-ditionally stable (it will not oscillate with 50 ohm source and load impedances, butwith other impedances, it may oscillate). However, if the amplifier’s k factor is lessthan zero (i.e., negative), then the amplifier is said to be unstable and can expected tooscillate spontaneously at some frequency, even with 50 ohm source and loadimpedances. It is very important to test an amplifier for stability over a wide range offrequencies, particularly low frequencies. It is often at frequencies well below thedesign’s operating frequency that oscillations may occur. If oscillations do occur,there are several circuit techniques that can be used to correct the problem. First, ifthere is a problem with low-frequency instability, a series RL network (as shown inFigure 9.21) must be placed in shunt with the amplifier’s input to combatlow-frequency instabilities effectively. If the stability problem is at frequencieshigher than the operating frequency, a series RC network (as shown in Figure 9.22)placed in shunt with the amplifier’s input is very effective in curing high-frequencystability problems. If the stability problem is near the intended operating frequency,a simple technique for increasing stability is to place a low-value resistor in serieswith the transistor’s base. This resistor will reduce overall gain, improving stabilityaccordingly. Other effective stabilizing techniques involve the addition of parallel orseries “negative feedback.” These feedback networks, which are discussed in moredetail in Section 9.12, are highly effective for improving stability, controlling gain,and improving linearity.

9.10 Bias Circuits

In order to provide the necessary dc bias to a power amplifier’s RF transistors, it isnecessary to provide certain circuits that can insert bias voltages and currents with-out disturbing the RF circuit’s basic behavior. The first such circuit, shown in Figure9.23, is very useful for connecting supply voltage and current to the RF transistor’s

150 Power Amplifier Design

Figure 9.20 An example of a band-pass output matching network.

collector. This simple circuit makes use of one inductor, called a choke, and twocapacitors. The series capacitor is called a dc block, and the shunt capacitor is calleda bypass capacitor. It is the purpose of both capacitors to provide very lowreactance at the operating frequency but very high reactance at low frequencies(infinite reactance at dc, of course). It is the purpose of the choke inductor to pro-vide very high reactance at the operating frequency but very low reactance at lowfrequencies (zero reactance at dc, of course). It is important, especially in the case ofRF transistors, which require very high dc currents, to choose a choke inductor withvery low dc resistance so that little or no dc voltage drop develops across the choke.This requirement often means that on-chip spiral inductors are unsuitable forhigh-current choke applications because of their relatively high dc resistance. If thisis the case, the designer must acknowledge the necessity of placing this choke induc-tor off-chip, as undesirable as that may sound. In terms of inductance values, acommon condition for choosing the choke inductor is to be sure its reactance at theoperating frequency is high compared to a 50 ohm load impedance. This require-ment is usually met if the choke’s inductance is greater than 100 ohm at the operat-ing frequency, Fo, which means,

2 FoLc > 100 ohm (9.17)

9.10 Bias Circuits 151

Figure 9.21 An input circuit for stabilizing a bipolar amplifier at low frequencies.

Figure 9.22 An input circuit for stabilizing a bipolar amplifier at high frequencies.

In a similar fashion, the dc-blocking capacitor and the bypass capacitor musthave reactance below about 1 ohm at the operating frequency, Fo, which means,

1/2 FoCb < 1 ohm (9.18)

As in the case of the choke inductor, these capacitors may or may not be locatedon-chip, depending on their size and how much chip area is occupied by a capacitorof this size. The final decision is often purely economic.

Now we consider the circuit requirement for base biasing. Referring toFigure 9.24, we see the simplest of all base-biasing circuits. This circuit is nothingmore than a resistor attached between the transistor’s base and a voltage source. Ifthe voltage source exceeds the transistor’s turn-on voltage, Vbe, current will flow inthe base-to-emitter junction, biasing the transistor with a base current of

Ibase = (Vdc – Vbe)/Rbase (9.19)

where

Ibase is the RF transistor’s base current.Vdc is the base supply voltage.Rbase is the circuit’s resistance.

152 Power Amplifier Design

Figure 9.23 The combination of a choke inductor, a blocking capacitor, and a bypass capacitorsupplies collector bias to a bipolar power amplifier.

Figure 9.24 A simple base-biasing network composed of a resistor, a blocking capacitor, and a dcvoltage supply.

Ibase should be set to produce the desired dc collector current, Ic, according to therelationship

Icollector = × Ibase (9.20)

where

is the transistor’s current gain (about 100 with most RF transistors).Icollector is the transistor’s saturated collector current.

With this circuit, Vdc acts as a direct controlling element for setting Icollector, whichcan be extraordinarily convenient. However, this simple circuit is not very stableover temperature since Vbe shifts at high and low temperatures causing changes inIbase and Icollector. For this reason, more stable base-biasing circuits have been devel-oped with the intention of overcoming these temperature-drift problems. The sim-plest of these alternative base-bias circuits, as shown in Figure 9.25, involves the useof a second resistor, RB1, connected from the base node to ground. In this case, theseries combination of the two resistors forms a voltage divider, which maintains amore constant voltage at the transistor’s base terminals. This circuit stabilization ofthe base voltage will stabilize the base and collector currents over a wide tempera-ture range. In order to make this circuit work effectively, it is necessary that the cur-rent flowing through the resistor divider be somewhat greater than the currentflowing into the transistor’s base. Resistor values must be chosen accordingly toinsure that this condition is met. The trade-off here is that lowering the resistor val-ues improves base voltage stabilization but increases the amplifier’s overall currentconsumption. In handheld, battery-powered applications, where the requirementsare sensitive to all sources of current, base bias current can become a problem foroverall current budgets.

A second method for stabilizing base and collector currents is called currentmirror biasing. The schematic diagram showing a current mirror circuit is presentedin Figure 9.26. In current mirror circuits, a second transistor (area = A2), which issmaller than the RF transistor (area = A1), is configured so that its base-to-emitterjunction is connected from ground to the base-to-emitter junction of the RF transis-

9.10 Bias Circuits 153

Figure 9.25 A slightly more complex base-biasing circuit for stabilizing the transistor’s base cur-rent and collector current over temperature.

tor though an RF choke. Current is supplied to the mirror transistor via a resistor,Rm, and a voltage source, Vmirror. Since the base-to-emitter junctions of the two tran-sistors are hardwired together (at dc), the two devices track each other over temper-ature, and as a result, temperature variations in the RF transistor’s collector currentare cancelled out. However, the absolute level of the RF transistor’s collector currentis controllable with the voltage source, Vmirror. This gives the supply Vmirror the abilityto control Icollector, which can be very useful in certain applications. Power amplifiersrequiring the ability to control their power output can be designed in this way.

The value of the mirror current, Im, is calculated with the following expression:

Im = (Vmirror – Vbe)/Rm (9.21)

where Vbe is the base-to-emitter turn-on voltage for the A2 transistor (1.40V forInGaP/GaAs and 0.70V for SiGe).

Under these conditions, the RF transistor’s collector current may be calculatedfrom

Icollector/Im = A1/A2 (9.22)

Notice that (9.22) does not contain any dependence on temperature but is asimple ratio between collector current and mirror current that depends on just theratio of the area of the RF transistor (A1) and the mirror transistor (A2). Currentmirror biasing is used extensively in many applications and is a straightforwardway to ensure stability of the device’s operating point, while at the same timeoffering the ability to control the amplifier’s dc current from an external voltagesource.

9.11 Design Example 3: Wideband Gain Block Darlington Amplifier

Darlington amplifiers are a unique class of RF amplifier having some very importantproperties, making them well suited for a wide variety of applications. In particular,

154 Power Amplifier Design

Figure 9.26 A current mirror base-biasing circuit that stabilizes an RF transistor’s collector currentagainst temperature and process variations. The ratio of the mirror transistor current, Im, to the RFtransistor’s collector current, Ic, is simply equal to the ratio of the two device areas. The mirror tran-sistor’s control voltage may be used as a collector current adjustment for power-output controlpurposes.

Darlington amplifiers are often found in cellular and PCS infrastructure applica-tions. The most important advantage of the Darlington amplifier circuit is itsextreme simplicity. The basic Darlington amplifier circuit consists of only two tran-sistors, four resistors, no capacitors, and no inductors. A second major advantage ofthe Darlington circuit is its extremely broadband frequency coverage. Darlingtonsare often designed to produce a flat gain response from dc to well over 10 GHz.However, P – 1 dB and OIP3 may roll-off over the amplifier’s useful bandwidth,making Darlington amplifiers less suitable for operation at high frequencies than atlow frequencies. The gain of a Darlington is controlled to the first order by a singleresistor R1, which controls the amount of negative feedback at work within theamplifier. By selecting R1 to be 1,000 ohms or more, a Darlington amplifier work-ing into 50 ohms source and load impedances will have a flat gain of 20 dB or more.However, this high gain trades off with linearity (OIP3), which is degraded from itsoptimum value if the feedback resistor is set for high gain. If the value of R1 is lessthan 500 ohms, the gain is reduced to 12 to 15 dB; however, linearity (OIP3) mayimprove by as much as 3 to 4 dB. The designer needs to be aware of this trade-off toproperly tailor a Darlington amplifier’s design for the requirements of a given appli-cation.

Depending on transistor size, the power output of a Darlington (operating atlow frequencies) may be as high as +25 dBm, and its OIP3 may be as high as +40dBm. These performances trade off with the maximum frequency for flat gainthrough the sizing of the transistors. The transistors in a Darlington amplifier usu-ally have a 1:3 area ratio between the first and the second transistor. However, thisrule is not hard and fast, and many Darlington amplifiers are successfully designedwith area ratios from 1:2 to 1:5.

Figure 9.27 shows the schematic of a basic Darlington amplifier circuit. Resis-tor R3 is used to create a voltage drop, which biases the base of the second transistorup to Vbe in order to turn it on. It is straightforward to calculate the value of R3

based on Vbe of the technology choice (about 1.4V for GaAs HBT and 0.70V forSiGe) and the maximum allowable dc current in the first transistor (Iq1max).

R3 = Vbe/Iq1max (9.23)

R2 is calculated from the condition that the base of the first device (Q1) must bebiased to at least 2Vbe above ground (since its emitter is attached to R3, which isalready above ground by Vbe), and the current that flows through R1 is approxi-mately the same as the current that flows through R2. This condition takes the formof the following equation:

R2 = 2VbeR1/(Vcc – 2Vbe) (9.24)

where Vcc is the dc supply voltage.The value of R4 should be in the range of 5 ohms to 10 ohms, and its final selec-

tion will depend on obtaining a minimum value for S22 during simulation.A first estimate of the amplifier’s gain in its flat region can be made by treating

the Darlington amplifier just like any other amplifier with internal negative feed-back. Assuming the source impedance is 50 ohms, the feedback resistor, R1, willdetermine the amplifier’s gain according to

9.11 Design Example 3: Wideband Gain Block Darlington Amplifier 155

G = 20log(R1/50) (9.25)

If R1 assumes a value of 1,000 ohms, (9.25) predicts a gain of 26 dB, which canbe approached in certain very ideal situations. Device sizing is more of an exercise indetermining what frequency range the application requires and what its power andOIP3 requirements are. Darlington amplifiers typically have a PAE of 15 to 25 per-cent, which means that in order to increase the power output to some desired level,the devices must be sized accordingly. Assuming a 1:3 area ratio between the firstand the second device, it will be necessary to increase device current sufficiently sothat the device’s overall power consumption is greater than Pout/PAE, where we canestimate that PAE is about 20 percent. The trade-off here is that for higher poweroutput, the larger devices needed to supply the power will have much larger parasiticelements than the smaller, lower-power devices. The larger device size will accord-ingly limit the highest useful frequency of the amplifier as a result of the parasiticeffects. Therefore, we recognize that another basic trade-off with Darlington ampli-fiers exists between power (and OIP3) and upper useful frequency. For practicalexperience it appears that about +25dbm is an upper limit on a Darlington’s poweroutput, if wideband operation is to be maintained.

As an example of a Darlington amplifier design, consider the schematic diagramfor the transistor-level circuit (including all element values) of a simple Darlingtonamplifier shown in Figure 9.28. This amplifier will operate from a supply voltage of5.0V. The element values are based on choosing R1 to be 1,000 ohms (for high gain),a first transistor area of one emitter finger, and a second-transistor area of threeemitter fingers. Additionally, we assume the maximum dc current is 10 mA per tran-sistor emitter finger, and Vbe = 1.4V (GaAs HBT). R2 is calculated from (9.24) to be1,500 ohms. R3 is calculated from (9.23) to be 140 ohms. Based on these circuitchoices (plus choosing R4 to be 1 ohm), we obtain simulated small-signalS-parameters in the purely lumped-element case, as shown in Figure 9.29. Noticethat the gain at 2 GHz is slightly over 20 dB, which is an excellent gain for such asimple amplifier circuit. However, the noise figure at 2 GHz is 4.4 dB, which is onlya fair noise-figure performance at this frequency. The reason for the fair noise-figureperformance is the placement of resistors R1 and R2, which are directly connectedthe amplifier’s input. These two resistors function as an attenuator, directly adding

156 Power Amplifier Design

Figure 9.27 The basic schematic diagram of a wideband Darlington amplifier using InGaP/GaAstechnology.

to the amplifier’s noise figure. For this reason, Darlington amplifiers are not recom-mended for low-noise amplifier applications. In a similar fashion, the Darlingtonamplifier’s power output and OIP3 can be simulated based on the lumped-elementschematic shown in Figure 9.28. These simulations are shown in Figures 9.30 (Pin

versus Pout) and 9.31 (OIP3). The next step in the process of designing this Darling-ton amplifier is to perform an IC layout for its circuit using the design rules for thefoundry that has been chosen to perform the wafer fabrication. We will do this lay-out based on the InGaP/GaAs HBT process design rules outlined in Chapter 4.Figures 9.32 and 9.33 show the layout of one such amplifier, including “blow-ups”of critical areas.

9.11 Design Example 3: Wideband Gain Block Darlington Amplifier 157

Figure 9.28 The schematic diagram of a wideband lumped-element Darlington amplifier.

Figure 9.29 The simulated S-parameters and noise figure for the lumped-element Darlingtonamplifier shown in Figure 9.28.

As a result of performing the layout, the designer becomes aware of certain areasof the circuit that have become subject to parasitic effects. For instance, the bondingpads at the amplifier’s input and output are in fact short microstrip transmissionlines. Also, the resistors have physical length in the layout, and this length must alsobe modeled, indicating a microstrip transmission line parasitic elements in serieswith each resistor. For this amplifier, we stop the parasitic element identificationprocess at this point, but in reality we could also add transmission line associatedwith some of the interconnecting metal lines, such as the line connecting the emitterof the first transistor to the base of the second transistor. Figure 9.34 shows theamplifier’s transistor-level schematic diagram, including parasitic elements. Afterrerunning the simulations (i.e., postlayout simulations), the resulting simulations forsmall-signal S-parameters, power output, and OIP3 are shown in Figures 9.35 to9.37, respectively.

158 Power Amplifier Design

Figure 9.30 The simulated power input versus power output for the lumped-element Darlingtonamplifier shown in Figure 9.28.

Figure 9.31 The simulated third-order intermodulation intercept point for the lumped-elementDarlington amplifier shown in Figure 9.28.

In fact, in this particular case there is not much change in performance associ-ated with the introduction of the parasitic elements created by performing the lay-out, as compared to the purely lumped-element case. In Figure 9.35, there is sometendency toward increased high-frequency gain roll-off, but at 2 GHz (we assume 2GHz is the application’s frequency of primary interest), the gain remains about 20dB, the power output at 1 dB gain compression remains about +15 dBm, and OIP3remains about +27 dBm.

Next, consider an alternative approach for this amplifier. The previous Darling-ton amplifier layout used an approach with all transistor emitter fingers arranged ina vertical orientation (as shown semischematically in Figure 9.38). An example lay-out using a vertical emitter finger orientation is shown in Figure 9.39. As an alterna-tive, consider a layout with horizontally arranged transistor emitter fingers, shownsemischematically in Figure 9.40. An example layout using a horizontal emitter ori-

9.11 Design Example 3: Wideband Gain Block Darlington Amplifier 159

Figure 9.32 The layout of the Darlington amplifier whose lumped-element schematic diagram isshown in Figure 9.28. Input is on the left.

Figure 9.33 A blow-up of a portion of the Darlington amplifier’s layout.

entation is shown in Figure 9.41. The advantage of this approach is its ability todecrease the overall distance between the individual transistor unit cells, potentiallyreducing parasitic effects. However, in some cases, these parasitic effects are usefulfor enhancing certain performance parameters. For instance, the metal line betweenthe first transistor’s emitter and the second transistor’s base can be optimized to cre-ate a gain peaking effect, which may be useful for increasing the amplifier’s overallbandwidth. As shown in Figure 9.42, for the zero parasitic case, the amplifier’s gainas a function of frequency is very flat until a certain critical frequency is reached(about 5GHz), above which the gain rolls off smoothly. However, if the length of the

160 Power Amplifier Design

Figure 9.34 The schematic diagram of the Darlington amplifier in Figure 9.28, including layoutparasitic elements.

Figure 9.35 The simulated S-parameters and noise figure for the Darlington amplifier shown inFigure 9.34 (including layout parasitic elements). Notice the high-end gain reduction.

line from emitter 1 to base 2 is increased and optimized, the amplifier’s gain may bepeaked at the critical frequency in such a way that the overall bandwidth isincreased by as much as 30 percent.

In this case, we say the Darlington amplifier is experiencing “para-sitic-enhanced” performance. Another example of parasitic-enhanced performanceis the optimization of the inductive line length associated with the connectionbetween the second transistor’s emitter and ground (through resistor R4). If thisinductive line length parasitic is optimized, the amplifier’s S11 and S22 may bereduced in magnitude by as much as 6 dB relative to the lumped-element case, asshown in Figure 9.43. This inductance may be created in one of three possible ways(or a combination of all three). The first is the natural transmission line behavior ofthe layout of R4. The second is a metal line connecting the emitter of the secondtransistor to R4, then connecting R4 to ground. The third method of increasing this

9.11 Design Example 3: Wideband Gain Block Darlington Amplifier 161

Figure 9.37 The simulated OIP3 as a function of frequency for the Darlington amplifier shown inFigure 9.34 (including layout parasitic elements).

Figure 9.36 The simulated power input versus power output for the Darlington amplifier shownin Figure 9.34 (including layout parasitic elements).

emitter-to-ground inductance is to use a spiral inductance (as shown in Figure 9.39),whose value is optimized to provide the lowest value of the magnitude of S11 and

162 Power Amplifier Design

Figure 9.38 A semischematic layout of a Darlington amplifier with its transistor emitter fingersaligned in a vertical direction. This layout is intended to reduce performance-limiting layoutparasitic elements.

Figure 9.39 A layout example of a Darlington amplifier with vertically aligned emitter fingers.The spiral inductor in the emitter of Q2 is a series feedback element for improving the input andoutput match. Input is on the left.

Figure 9.40 Semischematic layout of a Darlington amplifier with its transistor emitter fingersaligned in a horizontal direction. This layout is intended to reduce performance-limiting layout par-asitic elements.

S22. This inductance is also helpful in terms of enhancing the amplifier’s stability, asshown in Figure 9.44. The right amount of this inductive parasitic element helps theperformance of the amplifier in more than one way and should definitely be consid-ered when performing the amplifier’s layout. A parasitic element that degrades sta-bility and should be avoided is the parasitic shunt capacitance to ground at thesecond transistor’s emitter. This element may be a natural result of the physical areaof the resistor R4 and its connecting metal. Unfortunately, stability is compromisedby the presence of this parasitic shunt capacitance. In order to keep this element to aminimum and to keep stability high, it is very important to keep the width of R4 to aminimum and avoid any wide metal interconnects between the transistor’s emitterand R4 and/or the connection of R4 to ground. All of these parasitic elements mustbe carefully modeled as part of the postlayout simulation process to ensure that theparasitic elements are of such dimensions that they work in favor of enhanced per-formance and do not degrade overall performance.

9.11 Design Example 3: Wideband Gain Block Darlington Amplifier 163

Figure 9.41 A layout example of a Darlington amplifier with horizontally aligned emitter fingers.Metal emitter extension lines provide inductive series feedback to improve match. Input is on theleft.

Figure 9.42 The simulated S-parameter performance of a typical Darlington amplifier withoutlayout parasitic elements. Notice that the input and output matches degrade at high frequenciesas a result of parasitic elements in the transistor’s model.

9.12 Design Example 4: Feedback Power Amplifier Design

Feedback amplifier circuits are very popular topologies for RF power amplifiers [9].Feedback amplifiers offer the best overall power, efficiency, stability, and linearityamong all power amplifier topologies. They also have the ability to suppress har-monics and other spurious products. However, they are often inherentlynarrowband and are typically suitable only for single-frequency operation. Feed-back amplifiers can achieve nearly 50 percent efficiency in class A operation. Poweroutput with a feedback amplifier can easily exceed +33 dBm, and OIP3 can be over+50 dBm.

Feedback can be applied in one of two ways [10]. Parallel feedback is usuallyapplied as a series resistor-capacitor combination that connects the RF transistor’sbase to its collector. The main purpose of the capacitor is to provide a dc block sothat the high voltage at the collector does not disturb the base-biasing circuit. The

164 Power Amplifier Design

Figure 9.43 The simulated S-parameter performance of the same Darlington amplifier, includingthe effect of parasitic inductance resulting from Q2’s emitter resistor’s length (le2x). As the emitterresistor is made longer (raising the inductance), the input and output match improve at high fre-quencies because of the presence of inductive series feedback.

Figure 9.44 The simulated stability (k factor) performance of the Darlington amplifier associatedwith Figure 9.42. This simulation demonstrates how parasitic inductance associated with emitterresistor length (lng) can improve an amplifier’s stability.

value of the resistor in a feedback network controls the amount of feedback that isapplied. This feedback resistor plays a very similar role as R1 in the Darlingtonamplifier. If the feedback resistor is high in value, the gain of the amplifier will behigh, but the linearity (i.e., OIP3) will suffer. If the feedback resistor’s value islower, more feedback will be applied, and the amplifier’s linearity (OIP3) willincrease; however, this reduction in the feedback resistor’s value will cause theamplifier’s gain to suffer. This gain-versus-OIP3 trade-off is very fundamental andcannot be significantly altered.

A second form of feedback is called series feedback, which often consists ofplacing an inductor between the RF transistor’s emitter and ground. This form ofseries feedback is highly effective in providing enhanced stability for an amplifierthat is marginal in this respect. However, a major drawback to this kind of feedbackis that the inductor placed between the RF transistor and ground is required to carrythe amplifier’s full dc collector current, which can be over 1A in the case of trans-mitting amplifiers in wireless applications. This high dc collector current willrequire a very wide metal trace if an on-chip spiral inductor structure is to be used.For this reason alone, it is best not to use series feedback in amplifiers whose poweroutput is higher than about +25 dBm.

The basic feedback amplifier circuit schematic diagram, containing both typesof feedback, is shown in Figure 9.45. This circuit contains only feedback and biaselements; no matching elements are included. Such a circuit is often too simple to beuseful. In particular, the output circuit needs to contain matching capabilities inorder to provide the proper Rl for maximum power and maximum efficiency at theRF device’s collector-to-emitter terminals. The matching circuit topologies of afeedback amplifier are often the same topologies that have already been developedin Section 9.8. With little or no feedback applied to the circuit, the design processshould begin with proper matching elements attached to the collector terminals inorder to provide the correct Rl without the presence of feedback. As feedback isapplied, these element values may have to be modified to achieve peak performance.However, most successful feedback amplifier designs begin as a simple matchedamplifier design.

Feedback amplifiers often use RF transistors that are quite large. This is espe-cially true in power amplifiers required to operate from low-voltage supplies, suchas power amplifiers for handheld, battery-operated applications where the supplyvoltage is 3.3V. These transistors must be large because they provide the high RFcurrent swings required to generate high power output at such low supply voltage(low RF voltage swings are associated with low dc supply voltage). Such RF transis-tors may contain between fifty and one hundred emitter fingers. It is very importantthat such transistors be laid out in a careful way in order to avoid a kind of internalinstability within the transistor’s own structure. This instability, which is oftencalled the even-odd mode instability, is associated with the transmission line prop-erties of the metal lines that interconnect the transistor unit cells. In particular, invery large transistors, the unit cells farthest away from each other in the layout mayoperate at different RF voltage potentials.

Such behavior will lead to a kind of signal teeter-totter behavior that causesoscillations to occur at frequencies significantly higher than the design’s operatingfrequency (5 to 8 GHz is the usual range for these oscillations). The best way to

9.12 Design Example 4: Feedback Power Amplifier Design 165

avoid these problems is to place a limit on the number of transistor unit cells con-nected together in a row to less than fifteen. For instance, in a typical large transis-tor, only twelve unit cells are connected together in a single row. The transistor’semitter contacts are all connected together via a first-metal contact, which isgrounded directly to a substrate via. In order to increase the overall count of unitcells to that required by the design, it is good practice to have many rows of unit cellsthat are connected in parallel. In this example, we have only two rows; however, thiscould be easily increased to four rows simply by copying the initial two rows andreproducing this pattern as many times as necessary. It is good practice that all thecollector contacts from both rows are connected together at common collector“manifold.” It is very important for stability reasons that these collector manifoldselectrically close around the entire transistor in order to prevent even-odd modeoscillations from developing between opposite ends of the transistor. The collectormanifold can be “closed” on the left-hand side of the transistor if the closing connec-tion uses metal 1 (using two M1-to-M2 vias). In any event, the key to avoiding thekind of instabilities associated with the transistor’s layout is to be sure there are nomore than fifteen unit cells in any row and that all collector connections are madedirectly to a common “manifold” that always electrically closes on itself, ensuringthat all unit cell collectors are at the same potential.

Another important issue to consider in the design of large transistors for poweramplifier service is ballasting. Conceptually, ballasting is closely related to therequirement that a heavy lead weight be built into sailboats’ keels to prevent theboat from tipping too far one way or another in heavy wind or high seas. Considerthe schematic diagram of a large RF transistor shown in Figure 9.46. If the most dis-tant unit cells within the transistor’s layout are operating at slightly different tem-peratures, there will be small differences between these cell ’s by virtue of theirtemperature differences. Now if increases with increasing temperature, the unitcell with a slightly higher temperature than the other cell transistors will experienceslightly higher collector current.

Higher collector current will mean a still further increase in temperature withinthis “hot” unit cell, leading to a situation called thermal runaway. It is also calledcurrent hogging because, ultimately, one of the unit cells (the one that was initiallyslightly hotter than the others) will carry most of the current, becoming very hot,and will surely fail. To avoid failures of this kind, it is necessary to include what arecalled ballasting resistors between the emitter and ground of each unit cell. Whenthe current in a particular cell increases due to current hogging, the voltage drop

166 Power Amplifier Design

Figure 9.45 The schematic diagram of a power amplifier that makes use of both parallel andseries feedback.

across the ballasting resistor will reduce the cell’s Vbe, reducing its current andreturning the transistor to thermal stability. Ballasting resistors are usually designedto provide about twice the thermal voltage (i.e., thermal voltage = kT/q = 25 mV atroom temperature, where k is Boltzmann’s constant, and q is the charge on an elec-tron). This means the value of the ballast resistor associated with each unit cell (forInGaP/GaAs) is

Runitcell = 50 mV/10 mA = 5 ohms (9.26)

The total ballasting resistance, Rballast, that must be placed in the simulationschematic will be the ballasting resistance per unit cell calculated from (9.26)divided by N, the total number of unit cells that make up the transistor (since theyare all connected in parallel).

Rballast = Runitcell/N (9.27)

It is only necessary to include ballasting resistors if the number of unit cells in anRF power transistor exceeds ten. For transistors with fewer than ten unit cells, thetemperature difference between unit cells is too small to create thermal instabilityproblems.

In practice, ballasting resistor layouts are often configured in the form ofinterdigitated resistors, as shown in Figure 9.47. With this technique, each emitterM1 contact is interdigitated with an equal number of M1 ground fingers. A line ofTFR material is drawn across this array of emitter and ground contacts to form anarray of ballasting resistors. Each resistor has a value of

Runit = (L/W) 50 ohms (9.28)

where

L is the spacing between the emitter fingers and the ground fingers.W is the width of the TFR material.

9.12 Design Example 4: Feedback Power Amplifier Design 167

Figure 9.46 The schematic diagram of a large transistor, including ballasting resistors that con-nect each unit cell’s emitter contact to ground. These ballast resistors prevent a dc instability calledcurrent hogging and thermal run away.

Since each transistor unit cell has two of these interdigitated resistors associatedwith it, the total ballast resistance associated with each transistor is Runit/2. Thismeans that if Runit is 10 ohms, then Runitcell = 5 ohms.

An example of a feedback power amplifier design is shown in the transistor-levelschematic of Figure 9.48. This amplifier makes use of parallel negative feedback,which is provided by a series combination of a 1,000 ohms resistor and a 10 pFcapacitor connected between the amplifier’s base and its collector. The amplifier hasbeen uniquely designed to have a loadline resistance of 50 ohms under 5V operation,which means that no output matching (i.e., transformation of the 50 ohms load) isrequired to produce the maximum output power, which is about +24 dBm.

The amplifier has been designed to operate at 2.45 GHz for WiFi b and g appli-cations. The only matching elements in this amplifier are in the input circuit andconsist of a single-section low-pass circuit. This amplifier can immediately be con-verted to a layout-ready schematic using spiral inductors, as shown in Figure 9.49.The amplifier’s layout is given in Figure 9.50. The major parasitic elements associ-ated with this layout is the conversion from the lumped inductors in the inputmatching circuit to physical spiral inductors. The ADS MRIND element is used tomodel the spiral inductor. By using simulations to associate ideal lumped inductorswith spiral inductors (see Chapter 6), the element values in MRIND are adjusted toproduce exactly the impedance value of the lumped-element inductor at the operat-ing frequency. It is good practice to design the width of the inductor’s metal trace(W) to be consistent with the maximum dc current that could flow in the inductor.The inductor may be either metal 1 or metal 2. The only difference is that if theinductor is metal 1, it will require a metal 2 “overpass” to complete the path (asshown in Figure 9.50), and if it is metal 2, it will require a metal 1 “underpass” tocomplete the path. Usual practice is to use a trace spacing (S) equal to the metalwidth (W). However, if S is made less than W, some additional inductance can beachieved for a given spiral area by increasing the mutual inductance between thewindings.

168 Power Amplifier Design

Figure 9.47 A ballast resistor layout example showing how the M1 and TFR configurations worktogether to create a series of interdigitated ballast resistors for use in large multi-emitter-fingertransistors.

The post layout simulated S-parameters are given in Figure 9.51. It turns outthat the input match and the gain have all improved relative to the lumped-elementcase. This is because in the lumped-element case, a 10 ohms series resistor was asso-ciated with each lumped-element inductor in order to create acceptable stability andinput match (S11). However, by switching to spiral inductors for the layout phase,the natural loss associated with the spiral inductors is just sufficient to provideacceptable stability and S11 without degrading gain as much as was done by the10 ohms resistors in the lumped-element case. This is another example of howlayout parasitics can improve, and do not always degrade, performance.

Figures 9.52 and 9.53 show the post layout Pin versus Pout and OIP3. About 1 dBof performance was lost in both P – 1 dB and OIP3 due the presence of the spiralinductors in the layout. This can only be understood by recalling that in a feedbackamplifier design, a significant amount of the amplifier’s output power isrecirculated to the amplifier’s input as part of the negative feedback process. Thisloss of about 1 dB in power output performance between the lumped-element caseand the post layout simulations is not unusual, and in fact, it is best to plan on thislevel of performance degradation.

9.12 Design Example 4: Feedback Power Amplifier Design 169

Figure 9.48 A lumped-element circuit schematic for a feedback power amplifier example, whichcontains low-pass input matching and parallel feedback. Since the optimum loadline resistance forthis amplifier is 50 ohms, no output matching elements are required to achieve maximum powerand efficiency. The inductors associated with the input matching circuit each have an internalresistance of 10 ohms.

Figure 9.49 The schematic diagram for the circuit shown in Figure 9.48 after modification toinclude spiral inductors in the input matching network to model the parasitic effects of layout.

170 Power Amplifier Design

Figure 9.50 The layout of the feedback power amplifier circuit shown in Figure 9.49.

Figure 9.51 The simulated S-parameters of the modified feedback power amplifier, including lay-out parasitic elements (i.e., spiral inductors in this case).

References

[1] Sweet, A., MIC and MMIC Amplifier and Oscillator Circuit Design, Norwood, MA:Artech House, 1990.

[2] Cripps, S., RF Power Amplifiers for Wireless Communication, Second Edition, Norwood,MA: Artech House, 2006.

[3] Cripps, S., Advanced Techniques in RF Power Amplifier Design, Norwood, MA: ArtechHouse, 2002.

[4] Kenington, P., High Linearity RF Amplifier Design, Norwood, MA: Artech House, 2000.[5] Maas, S., Nonlinear Microwave Circuits, Norwood, MA: Artech House, 1998.[6] Niclas, K., “Reflective Match, Lossy Match, Feedback and Distributed Amplifiers: A Com-

parison of Multi-Octave Performance Characteristics,” IEEE MTT-S Symp. Digest, 1984,pp. 215–217.

9.12 Design Example 4: Feedback Power Amplifier Design 171

Figure 9.52 The simulated power input versus power output and 1 dB gain-compression pointfor the feedback power amplifier, including layout parasitic elements.

Figure 9.53 The simulated OIP3 versus frequency for the feedback power amplifier, includinglayout parasitic elements.

[7] Cripps, S., “A Method for the Prediction of Load-Pull Power Contours in GaAs MESFETs,”Proc. IEEE Intl. Microwave Symp., MTT-S, 1983, pp. 221–223.

[8] Kenney, J., and Lake, A., “Simulation of Spectral Regrowth, Adjacent Channel Power, andError Vector Magnitude in Digital Cellular and PCS Amplifier Design,” Microwave J.,October 1995.

[9] Gupta, M., “Power Gain in Feedback Amplifiers, a Classic Revisited,” IEEE Transactionson MTT, MTT-40, May 1992, pp. 864–879.

[10] Vendelin, G., et al., Microwave Circuit Design Using Linear and Nonlinear Techniques,New York: John Wiley and Sons, 1990.

172 Power Amplifier Design

C H A P T E R 1 0

Designing Multistage Amplifiers

10.1 Multistage LNAs

Multistage amplifiers hold unique challenges in making sure that each stage in a cas-cade is designed just right to provide sufficient power output and OIP3 in order todrive the following stage to its full output capabilities. However, it is very importantthat no stage be overdesigned so that its power output and OIP3 capabilities go towaste, degrading overall efficiency by draining more dc current than is absolutelynecessary for achieving full performance.

In particular, LNA’s require that multistaging achieve certain important spe-cialized goals. The first stage of any multistage LNA is of critical importance fordetermining the LNA’s overall performance. The first stage is the primary deter-miner of overall LNA noise figure. Also, second-stage noise-figure contributions areinversely proportional to the gain of the first stage. Therefore, it is of paramountimportance to make the noise figure of the first stage as low as possible, while at thesame time making the gain of the first stage as high as possible [1]. If the first-stagegain is very high (above 12 dB), the second stage will make only a minimal contribu-tion to the overall noise figure of the cascaded LNA, providing its noise figure is notexcessively high. All low-noise amplifiers have an input match, called Γopt, whichrepresents the impedance that must be presented to the device’s input terminals inorder to realize that device’s minimum noise figure. In an ideal low-noise amplifier,the Γopt of each stage would be presented to the input of that stage’s device, as shownin Figure 10.1. In order to do this, it will be necessary to configure the output match-ing of each stage so that it provides just the right impedance at its output terminal,enabling the following stage to experience the right Γopt at its input. Figure 10.2shows how this requirement is played out at the transistor level. M1 is the LNA’sinput matching circuit providing Γopt1 to the first stage. The interstage matching net-work between stages one and two is M2. At its output, M2 provides Γopt2 for the sec-ond-stage device. The same process is repeated at the third and any subsequentfollowing stages. As shown in Figure 10.3, the matching process for an LNA alwaysstarts at the input and works towards the output. First, M1 is designed to apply thebest match for both noise figure (Γopt1) and gain to transistor Q1. Next, M2 is syn-thesized to provide both the best output match for gain at Q1 and also to presentΓopt2 to the input of Q2 to optimize the noise figure and gain of transistor Q2. Thesame process can be repeated for any number of following stages, but in practice,most multistage LNA noise-figure contributions come from the first and secondstage (primarily from the first stage), so it is very rare to need to continue this design

173

procedure past the second stage. In most cases, an LNA with more than two stageswould have stages three, four, and so on, designed strictly for maximum gain.

A software tool that is most valuable in designing multistage LNA’s is AppCADfrom Agilent, Inc. This downloadable program allows the user to fill in the noise fig-ure, gain, and OIP3 of each stage, and the program calculates the total performanceof the cascade. While AppCAD will not provide impedance matching information, itwill allow the designer to determine quickly if a given architectural lineup of stagescan meet a given set of top-level specifications for a particular application. An exam-ple of an AppCAD calculation is shown in Figure 10.4. In AppCAD, filters and otherpassive devices are treated as amplifiers with negative gains equal to their loss anda noise figure also equal to their loss. In most cases, passive devices will be repre-sented by a very high value of OIP3 (above +50 dBm), unless there is reason to thinka particular passive device will have a lower OIP3 for unique reasons.

174 Designing Multistage Amplifiers

Figure 10.1 To achieve the minimum noise figure with a cascaded low-noise amplifier, it is nec-essary to provide the correct Γopt at the input of each stage’s transistor.

Figure 10.2 Interstage matching networks M2 and M3 provide the correct Γopt to the input of thetransistors in stages 2 and 3. Network M1 provides the correct Γopt to the transistor in stage 1.

Figure 10.3 The matching process in a multistage LNA starts at the input and proceeds to theoutput. Because of second-stage contribution effects, for most LNAs it is only necessary to provideΓopt to stage 1 (and possibly stage 2), provided that the gain of stage 1 is high.

10.2 Multistage Power Amplifiers

In the case of multistage power amplifiers, it is very important to predetermine theexact value for the loadline resistance for maximum power output associated witheach stage. It is this knowledge of the stage-by-stage loadline resistance that allows adesigner to tailor each stage of a multistage power amplifier so that every stage isrunning at its correct maximum power output and efficiency for its particular placein the cascade. To facilitate this process, it is always a good practice to start a multi-stage power amplifier’s design at the output and work toward the input. The firststep is to calculate the loadline resistance of a single-emitter-finger unit cell transis-tor operating at the supply voltage, as shown in Figure 10.5. Once this is accom-plished, it is relatively easy to size the loadline resistance for the various stages of theamplifier by simply dividing the unit cell loadline resistance by the number of unitcells needed to achieve the required power level at a given stage. As shown in Figure10.6, each stage must have its proper loadline resistance presented to the collectorterminals of its transistor, starting with the final stage (the Nth stage) and progress-ing backwards to the first stage. As seen in Figure 10.7, each stage’s input imped-ance is transformed through an interstage matching network in order to present therequired loadline resistance to the preceding stage. This process starts with thematching elements that transform the ultimate 50 ohms output load impedance tothe correct loadline resistance for the last stage, then proceeds back through theentire amplifier chain, ensuring that the RF transistor in each stage will be termi-nated into its optimum loadline resistance based on its size. The next step in the

10.2 Multistage Power Amplifiers 175

Figure 10.4 An AppCAD calculation of the gain, noise figure, and intermodulation interceptpoint of a single-conversion superheterodyne receiver.

design process will be to determine the sizing rules for scaling the transistors on astage-by-stage basis.

176 Designing Multistage Amplifiers

Figure 10.5 Using the generic Gummel Poon device model for an InGaP/GaAs unit cell transistor,the class A loadline resistance for the unit cell operating at Vcc = 3.0V and Ic = 10 mA is calculatedto be 225 ohms. Under these bias conditions, the parallel combination of N such unit cells wouldhave a class A loadline resistance of 225/N.

Figure 10.6 In order for a multistage power amplifier to generate its maximum possible poweroutput, it is necessary that the correct loadline resistances (RL3, RL2, and RL1) be presented to the

Figure 10.7 In a three-stage power amplifier example, an interstage matching network trans-forms the base impedance of the third stage’s transistor into the correct loadline resistance for thecollector of the second-stage transistor (to maximize the power output from the second stage).The same procedure is followed for the first stage.

10.3 Gain and Power Allocations

In order to size each stage’s device properly in a multistage power amplifier, it isnecessary to create a gain/power allocation budget for the overall amplifier [2]. Thisallocation process is determined by the relationship between the gain and power ofeach stage and the power output of the stage immediately preceding this stage. Asshown in Figure 10.8, the power output and OIP3 requirement of any stage is deter-mined (to the first order) by taking the next stage’s power and OIP3 requirements,then subtracting from them that stage’s gain. For instance, if a final stage with 10 dBgain is designed to deliver +30 dBm to the load with an OIP3 of +45 dBm, then theimmediately preceding stage must have the ability to deliver +30 dBm – 10 dB = +20dBm to the input of the final stage with an OIP3 of at least +45 dBm – 10 dB = +35dBm. Figure 10.9 shows how the input impedance of each stage must be trans-formed into the ideal loadline resistance for the stage immediately preceding it. Byusing a set of interstage matching networks based on the calculated ideal loadlineresistances for each stage, it is possible to create an overall amplifier schematicdiagram that allows each stage to function to its full capabilities and design acascaded amplifier that produces the desired overall performance without anyof the stages’ acting as weak links in the process. All of these calculations are doneon a “best-first-guess” basis. In reality, OIP3 is determined by spuriousintermodulation products that are created independently in each stage and mayphase together in ways that are hard to predict. The method presented here assumesthat the third-order intermodulation products are added together simply as powersand not as interfering waves. In fact, they are almost certain to add as interferingwaves, meaning that at least in the case of OIP3, what we are calculating with thismethod is only a rough first guess.

10.4 Active Device Sizing

Given the cautions and caveats discussed above, we begin the device-sizing processrealizing that this is not an exact science. Nevertheless, useful results are expected

10.3 Gain and Power Allocations 177

Figure 10.8 Starting from the output of a cascade power amplifier, the power output and OIP3requirements for each stage are calculated by subtracting the gain of all stages from the stage ofinterest to the output from the ultimate power output requirement and the ultimate OIP3 require-ment.

from this process, so we will proceed. Figure 10.10(a) shows the partitioning of RFpower, dc current, and device size within a multistage power amplifier. Figures10.10(b, c) show simulator plots that are useful in determining the load resistancepresented to the transistor’s collector by a matching network. It is useful to make upspreadsheets (as shown in Figures 10.10(c, d) containing the gain, 1 dB compressedpower output, OIP3, loadline resistance, and dc current associated with each stageof the multistage amplifier. The final item in the spreadsheet will be the size of thedevice. Device size is determined by the need for the device to generate that amountof power sufficient to drive the next stage in the chain to its full power output. If weoverdesign a given stage, that stage is never called upon to deliver its maximumpower; therefore, dc power is wasted. However, if a given stage is underdesigned,there will not be enough power to drive the following stage to its full power capabili-

178 Designing Multistage Amplifiers

Figure 10.9 A multistage power amplifier is broken down into a cascade of interstage matchingnetworks that insure the input resistance of a given stage is transformed into the correct Rlopt for thepreceding stage.

Figure 10.10(a) The dc current requirement for each stage is determined from its RF power out-put requirements and its estimated PAE. Based on this calculated value of Ic, the size of each stage’stransistor, Ni, is calculated. This analysis allows the determination of Pout, OIP3, Pdc, Ic, and Ni foreach stage.

ties. This will cause a lowering of the overall power of the amplifier, making a par-ticular stage the weak link in the amplifier chain.

10.4 Active Device Sizing 179

Figure 10.10(b) A possible matching network for using a simulator to set the element value thatprovides the correct Rlopt for each stage of a cascaded power amplifier.

Figure 10.10(c) A Smith chart showing the loadline impedance (pure real at 2.5 GHz) presentedat the transistor’s collector terminals by the matching network shown in Figure 10.10(b).

Figure 10.10(d) An example of a spreadsheet for keeping track of the power output and OIP3requirements for each stage in a multistage cascaded power amplifier.

In order to avoid the extremes of both overdesign and underdesign at any givenstage, it is very important to achieve the target values accurately for each stage interms of its power, OIP3, and gain. This is best accomplished by sizing each stage’sdevice according to the following rules. First, upon determining the power require-ments of a given stage based on the considerations discussed above, the device’s col-lector current may be calculated according to

Ic = Po/(Vcc × PAE) (10.1)

Second, it is now necessary to make an estimate of PAE for a given amplifiertype. If the amplifier is a feedback type, operating with high voltage (i.e., above5.0V), the resulting PAE can be expected to exceed 40 percent. If the amplifier is aDarlington type or operating from a low-voltage power source, the value of PAEmay be in the range of 20 to 30 percent (see Chapter 9). The designer needs to makesome judgments at this point. To be safe, it is generally best to estimate PAE on thelow side.

Third, once PAE is estimated, the number of unit cells required for each stage iscalculated as

N = Ic/Imax (unit cell) (10.2)

where

Ic is the collector current.Imax is the maximum safe unit cell collector current.

In summary, the complete design procedure for distributing performance anddevice size within a multistage power amplifier is as follows:

1. From the estimated gain for each stage, calculate the required power outputand OIP3 of each stage, based on the overall output power and OIP3 of thecascaded amplifier, referenced to each stage (based on the preceding stage’sgain.)

180 Designing Multistage Amplifiers

Figure 10.10(e) An example of a spreadsheet useful for systematically calculating the dc powerrequirements, class A loadline resistance, and transistor size for each stage in a multistage poweramplifier.

2. Based on estimated PAE efficiency (remember that 50 percent is the absolutemaximum PAE for class A amplifiers), calculate the dc current requirementsfor each stage.

3. Determine the maximum dc current for a unit cell device based on reliabilitydata obtained from the foundry.

4. Size the RF transistor device in each stage based on its dc current and themaximum dc current of the unit cell. Size is expressed as a number N of unitcell emitter fingers.

5. Use the loadline resistance of a unit cell (a single-emitter-finger transistor) todetermine the overall loadline resistance for each stage (i.e., RL (per stage) =RL (unit cell)/N.

6. Synthesize interstage matching networks between stages to ensure that theexact loadline resistance required by each stage is presented to the collectorterminals of the RF transistor in a given stage.

As an example, consider the design of a two-stage amplifier that must meet arequirement to produce 0.50W of power output at 50 percent efficiency with 20 dBoverall gain. Based on 10 dB gain per stage, the output power of the first stage mustbe 0.05W. Assuming a supply voltage of 3.0V, the second stage must have a collec-tor current of 0.50W/3(50 percent) = 330 mA. Assuming 10 mA is the maximumsafe dc current for each unit cell, the size of the second-stage device is calculated as330/10 = 33 unit cells (emitter fingers). The first stage is handled in the same way.The first-stage collector current is 0.05W/3(50 percent) = 33 mA. Again, assuming10 mA maximum dc current in each unit cell, the size of the first stage’s device is33/10 = 3.3 (always round up to the larger number of unit cells, which is four in thiscase). Assuming a unit cell loadline resistance of 225 ohms (based on 3V operation),the second stage’s loadline resistance is 225/33 = 6.8 ohms (pure real). The firststage’s loadline resistance is 225/4 = 56.3 ohms (pure real). The next step in thedesign procedure is to synthesize an output matching network that provides the6.8 ohms loadline resistance to the collector terminals of the second-stage deviceand an interstage matching network that provides a 56.3 ohms loadline resistanceto the collector terminals of the first-stage device. See Chapter 9 for suggestedmatching networks for providing these impedances.

10.5 Design Example 5: A Differential PCS PA

We next consider the design of a two-stage differential power amplifier for servicein GSM and CDMA handsets1. The fabrication technology will be InGaP/GaAsHBT in order to ensure a high breakdown voltage. Handset power amplifiers oper-ate at +3.0V dc; however, the RF voltage swings can often exceed 8V, making thisclass of amplifiers unsuitable for fabrication in SiGe technology. Important advan-tages can be realized by using a differential topology for high-power amplifiers inbattery-powered mobile applications. The most important advantage is the abilityto divide the power transistors in two by splitting them between the two sides of adifferential pair. This factor-of-two size reduction will make each power transistormore manageable both in terms of ease of layout and reduction in layout parasitic

10.5 Design Example 5: A Differential PCS PA 181

effects. Consider the design of a differential 2W power amplifier for mobile GSMapplications.

Because this amplifier is used in a handheld mobile unit, the battery voltage willbe confined to 3.0V, forcing the size of the transistors to be very large, resulting invery low load impedance. Designing matching networks to provide such low imped-ances is a significant challenge. This is an area in which an all-differential design hassignificant advantages. Since the two amplifiers’ 180 phase-shifted outputs must becombined at an off-chip balun, the high collector bias current may conveniently beinserted at this balun. This is of great advantage because it eliminates the need todesign on-chip bias chokes, which may not be able to handle safely the high dc col-lector currents needed to generate this high level of RF power output. Also, a differ-ential amplifier naturally suppresses all even harmonics at its output.

The first step in the design process is to calculate the size of the output stage’s(stage 2) transistors and their optimum loadline resistance. For 3V operation, theloadline impedance for a single emitter finger is 225 ohms. We first calculate the col-lector current of the second-stage (output) device, recognizing that in the differentialform, there are two output transistors, each of identical size and current level. Tocalculate collector current, simply divide the required power in half (1W), thendivide it by the dc voltage (3V) times the anticipated PAE. In this case, we estimatePAE to be 40 percent; therefore, Icollector = 1W/(3.0V)(40 percent) = 800 mA. Thenumber of emitter fingers in each second-stage transistor is equal to 800 mA dividedby 10 mA maximum current in each emitter finger, which is equal to eighty emitterfingers for the second-stage device. The loadline resistance of the second stage isequal to 225 ohms per emitter finger divided by eighty fingers, which is 2.8 ohms.An output impedance matching network must be designed to provide a transforma-tion from the customary 50 ohms output impedance to the required 2.8 ohmsloadline resistance. This transformation could be accomplished in the output balun,or it can be performed with a simple low-pass matching network where the shuntcapacitors from each side of the amplifier are connected together at the virtualground point at the electrical center of the circuit (see Chapter 6).

Next, we perform a similar calculation for the amplifier’s first stage based on anassumed second-stage gain of 10 dB. The required output power of the first stage is1W (i.e., +30 dBm) minus 10 dB, which is 100 mW (i.e., +20 dBm). This power isdivided by a factor of two to account for the two differential transistors used in stage1. Therefore, the collector current of the first stage is equal to 0.05W/(3.0V)(40 per-cent) = 40 mA. The number of emitter fingers in each of the first-stage transistors isequal to 40 mA divided by 10 mA (the maximum safe dc current per emitter finger),which equals four fingers. The loadline resistance of the first stage is equal to225 ohms per emitter finger divided by four emitter fingers, which is equal to56 ohms. A low-pass matching network similar to that used in the second stage canbe used here. However, in the simulations, the base of the second-stage transistormust serve as the output impedance for the matching network of the first stage. Basebias is provided to the first and second stages by current mirror circuits. Collectorbias is supplied to the first-stage transistors by RF chokes and to the second-stagetransistors by an off-chip balun. The input signal is supplied to the first stage by abalun, which can serve as an input matching network from 50 ohms to the desiredinput impedance (for maximum gain) at the base of the first-stage transistors. The

182 Designing Multistage Amplifiers

block diagram of the amplifier is given in Figure 10.11, and the schematic diagramsfor the first and second stages are shown in Figures 10.12 and 10.13, respectively.

The simulated small-signal S-parameter for the two-stage PCS amplifier isshown in Figure 10.14. Notice that the amplifier’s small-signal gain (S21) is about40 dB, flat from 700 to 1,000 MHz. The input and output match is good from 800to 1,000 MHz. The stability factor k is above 1.0 (indicating unconditional stabil-ity) over most of the frequency range, only dipping slightly at about 650 MHz. Thisdip in the k factor can be easily cured by including some stabilizing RL circuits in theinput circuit of one or both stages. Notice that the simulated total dc current in thefirst stage is 100 mA and 2.0A in the second stage, which is consistent with the ini-tial hand calculation.

A graph of the simulated power output versus power input is shown in Figure10.15. The 1 dB compression point is above +33 dBm, indicating that a total poweroutput of 2W is being achieved in the amplifier’s linear region. Figure 10.16 showsthe simulated fundamental and harmonic power outputs as a function of powerinput. Notice that the second-harmonic output is very low, which is a direct result ofthe amplifier’s differential design (second-harmonic energy is cancelled out at thebalun combined output port). However, the third harmonic, which is not naturallycancelled at the amplifier’s output, is still down by 55 dB relative to the fundamen-

10.5 Design Example 5: A Differential PCS PA 183

Figure 10.12 The schematic diagram of the first stage of a two-stage differential PCS poweramplifier.

Figure 10.11 The block diagram of a two-stage PCS power amplifier using InGaP/GaAs technol-ogy and operating at a supply voltage of 3.0V. This two-stage differential PCS power amplifieroperates at 900 MHz with a power output of +33 dBm.

tal power at the amplifier’s 1 dB compression point. Again these extremely low har-monic levels indicate the operation of a very linear power amplifier.

To gain insight into the fine-grained linearity of the output transistors, it is pos-sible to insert an RF current probe into the collector circuit of the second-stagetransistors and to use this probe, along with a named collector node voltage, to sim-ulate the large-signal collector voltage and collector current in stage 2. The sche-

184 Designing Multistage Amplifiers

Figure 10.14 The simulated S-parameters of the cascaded two-stage differential PCS amplifier.

Figure 10.13 The schematic diagram of the second stage of a two-stage differential PCS poweramplifier.

matic showing the insertion of the RF current probe is shown in Figure 10.17. Thesimulated voltage and current waveforms are shown in Figure 10.18. Notice thatthe RF voltage has some tendency to “clip” at the bottom of the cycle, indicatingthe presence of second-harmonic energy in the transistor’s output voltage. How-ever, as a direct result of the amplifier’s differential configuration, these sec-ond-harmonic signals are cancelled at the balun’s output and never “escape” fromthe amplifier.

The simulated RF collector voltage and collector current may be plotted againsteach other to form what is called a dynamic loadline, as shown in Figure 10.19. Thedynamic loadline is very interesting because it shows the full extent of the voltageand current excursions experienced by the transistor in each RF cycle at a givenpower level. The slight “looping” behavior of the dynamic loadline indicates thepresence of unresonated reactance within the transistor’s large-signal model. Thisreactance may be resonated by the output matching elements that follow the transis-tors. Notice that a straight line drawn through the set of dynamic loadlines is nearly

10.5 Design Example 5: A Differential PCS PA 185

Figure 10.15 The simulated power input versus power output of the two-stage differential PCSamplifier.

Figure 10.16 The simulated third-harmonic output from the two-stage differential PCS amplifier.At full power output, the simulated third harmonic is more than 50 dB below the fundamentalsignal.

equal to the calculated loadline resistance for the transistor (5 ohms dynamic versus2.8 ohms calculated).

Figure 10.20 shows the amplifier’s simulated OIP3 as a function of frequency.Figure 10.21 also shows the ADS schematic for the n-tone source and har-

186 Designing Multistage Amplifiers

Figure 10.17 A schematic diagram of the output transistor showing the placement of an RF cur-rent probe, making possible the simulation of both the voltage waveform and the current wave-form of the output transistor.

Figure 10.18 The simulated voltage and current waveforms of the PCS amplifier’s output transis-tors at a number of progressively increasing power inputs.

monic-balance controller for simulating OIP3. The amplifier’s value of OIP3 isnearly flat at +47 dBm from 800 to 1,000 MHz. This value of OIP3 indicates ascaled linearity metric of 47 dBm – 33 dBm = +14 dB, which is a really excellent lin-earity performance indicator. The linear efficiency of the entire amplifier may becalculated by first calculating the dc power consumption (3V × 2.1A = 6.3W or +37dBm), then subtracting the dc power consumption from the amplifier’s OIP3 (+47dBm – 37 dBm = 10 dB), which is also an excellent number, especially for a multi-stage amplifier, which suffers from the inefficiency of a first stage that consumes dcpower in order to raise the overall gain but contributes nothing to raising the overallOIP3 of the amplifier.

Next, we simulate the amplifier’s response to various types of modulation usedin cellular/PCS systems. The first modulation type tested is GSM [3]. GSM is a con-

10.5 Design Example 5: A Differential PCS PA 187

Figure 10.19 The simulated dynamic loadline for the PCS amplifier’s output transistors with a5 ohm “static” loadline superimposed on the dynamic curves. Looping is due to unresonatedreactance within the transistors. Notice that the primary axis of the dynamic loadline fits closely tothe calculated 5 ohm static loadline.

Figure 10.20 The simulated OIP3 versus frequency for the two-stage differential PCS amplifier.

stant envelope phase modulation and has no zero crossings in its constellation dia-gram. As a result, GSM modulation is more tolerant of nonlinearity in poweramplifiers than other types of modulations used in cellular/PCS systems. Figure10.22 shows the use of an ADS GSM source and the associated envelope-simulationcontroller. Envelope simulation is a very useful technique in the case of modulatedsignals because envelope simulations run much faster than standard harmonic-balance simulations. This is because, in effect, the simulator subtracts out the sinewave associated with the carrier and concentrates its attention entirely on the modu-lation envelope associated with the output signal. Figure 10.23 shows the envelopesimulation of the GSM source driving the two-stage PCS amplifier to its full +33dBm output power. Notice that the constellation diagram is a circle with no zerocrossings. This type of modulation is relatively tolerant of the nonlinearity of theamplifier when it is driven to full power output. Notice that most of the signal’sspectrum is located within +/–150 KHz of the center frequency, and the adjacentchannel power ratio (ACPR) is about –25 dBC in both the upper and lower firstadjacent channels. These ACPR numbers are acceptable for GSM operation. Next,the output power is backed off by 10 dB to +23 dBm, and the envelope simulationsat this power output are shown in Figure 10.24. Notice that neither the constellationdiagram nor the first adjacent channel ACPR changes significantly at reduced poweroutput. This is very consistent with the nature of GSM modulation and, in fact, isone of the advantages of this form of modulation (as opposed to CDMA modula-tion, whose ACPR is very sensitive to power amplifier output level).

Figure 10.25 shows the envelope source parameters for CDMA modulations.We now repeat the envelope-simulation process using CDMA modulation. In thecase of CDMA, the amplifier’s power output will be increased gradually to observe

188 Designing Multistage Amplifiers

Figure 10.21 An ADS harmonic-balance controller and the n-tone signal source, which are usedto simulate both the two-tone intermodulation and OIP3.

the effect on ACPR and the constellation diagram at each power output level.Figure 10.26 shows the simulations of signal spectrum and constellation using aCDMA-modulated source driving the PCS amplifier to an output of +17 dBm.

10.5 Design Example 5: A Differential PCS PA 189

Figure 10.23 The simulated GSM spectrum, constellation diagram, and ACPR for the two-stagedifferential PCS power amplifier driven by a GSM input signal to an output power of +33 dBm at900 MHz.

Figure 10.22 A schematic diagram showing the ADS GSM signal source and an enve-lope-simulation controller, which are used together to simulate a power amplifier’s performance inGSM service.

ACPR is about –60 dBC for both upper and lower first adjacent channels. These areexcellent numbers and exceed the IS-95 CDMA standard specification by a widemargin. The constellation diagram indicates multiple zero crossings, meaning

190 Designing Multistage Amplifiers

Figure 10.25 A schematic diagram showing the ADS CDMA (IS-95) signal source and enve-lope-simulation controller, which are used to simulate a power amplifier’s performance in this formof CDMA service.

Figure 10.24 The simulated GSM spectrum, constellation diagram, and ACPR for the two-stagedifferential PCS power amplifier driven by a GSM input signal to an output power of +23 dBm at900 MHz. Notice that in GSM service, the amplifier’s ACPR performance does not change signifi-cantly as its power output is backed off from +33 dBm to +23 dBm.

CDMA-modulated signals are expected to be very sensitive to power amplifiernonlinearity. However, the price paid for outstanding linearity is very low poweroutput relative to the amplifier’s full capabilities. Figure 10.27 shows a blow-up ofthe constellation diagram with the amplifier operating with a CDMA-modulatedsignal. It is clear from this diagram that CDMA signals have a basic QPSK formwith many zero crossings, making them unsuitable for use with very nonlinearamplifiers. Consider next what happens as the amplifier’s power output isincreased. Figure 10.28 shows the spectrum and constellation diagram for theCDMA output signal at a power of +31 dBm. The ACPR for the upper and lowerfirst adjacent channels is –48 dBC, which approaches the IS-95 standard specifica-

10.5 Design Example 5: A Differential PCS PA 191

Figure 10.26 The simulated CDMA spectrum, constellation diagram, and ACPR for the two-stagedifferential PCS power amplifier driven by a CDMA input signal to an output power of +17 dBm at900 MHz.

Figure 10.27 The simulated constellation diagram of CDMA modulation showing a basic QPSKmodulation structure with multiple zero crossings.

tion of –45 dBC. Figure 10.29 shows the simulations of the CDMA signal at theamplifier’s full output power of +33 dBm. At its full 2W power output, the ampli-fier’s ACPR has dropped to –40 dBC in both first adjacent channels, as expected.Therefore, clearly, CDMA service, unlike GSM service, requires that the amplifier’soutput power be backed off from its full power capability by 2 to 5 dB in order tomeet the ACPR specification. This amount of back-off significantly reduces the PAEof the amplifier. Most handset power amplifiers in CDMA service operate at effi-ciencies less than 30 percent. In order to conserve battery life, CDMA power ampli-fiers in handset applications are only required to operate at a power output of +28dBm, as opposed to GSM power amplifiers, which must operate at +33 dBm orhigher.

The layout for the two-stage PCS amplifier’s layout is shown in Figure 10.30.Optimizations and simulations of this design example were performed by CalvinChien in partial fulfillment of the requirements of the course ELEN 359A(“Advanced RFIC Design”) at Santa Clara University, Santa Clara, California. Theonly off-chip components required for operation are the input and the outputbaluns. An important challenge with this amplifier is ensuring that all metal tracescarrying the dc collector current associated with the final stage transistors are suffi-ciently wide to be safe, relative to the process design rules (based on metal migrationconsiderations). An excellent way to ensure compliance is simply to connect the finaltransistor’s collector contacts to a pair of bonding pads, which will in turn be con-

192 Designing Multistage Amplifiers

Figure 10.28 The simulated CDMA spectrum, constellation diagram, and ACPR for the two-stagedifferential PCS power amplifier driven by a CDMA input signal to an output power of +31 dBm at900 MHz. Notice that ACPR degrades by 12 dB as the power output is increased to +31 dBm rela-tive to the ACPR at +17 dBm power output. This level of ACPR is barely acceptable in most cellularapplications.

nected (via the package) to an off-chip balun. The balun can be used as an imped-ance matching device and a bias insertion point at its secondary’s center tap.

10.5 Design Example 5: A Differential PCS PA 193

Figure 10.29 The simulated CDMA spectrum, constellation diagram, and ACPR for the two-stagedifferential PCS power amplifier driven by a CDMA input signal to an output power of +33 dBm at900 MHz. Notice that ACPR degrades by 7 dB as the power output is increased to +33 dBm(which is the amplifier’s 1 dB compressed power output) relative to the ACPR at +31 dBm poweroutput. This level of ACPR is no longer acceptable in most cellular applications.

Figure 10.30 The layout of the two-stage differential PCS power amplifier for +33 dBm poweroutput at 900 MHz. The two differential input pads are on the left, and the six (two sets of threeeach) differential output pads are on the right. The bias circuit for stage 1 is in the lower left-handcorner of the die. The bias circuit for stage 2 is in the lower center portion of the die. Overall diesize is 3.0 × 3.5 mm.

Endnote

1. The original concept for this design example came out of a collaboration between theauthor and Taka Shinomiya of MCT, Inc.

References

[1] Vendelin, G., et al., Microwave Circuit Design Using Linear and Nonlinear Techniques,New York: John Wiley and Sons, 1990.

[2] Wilson, S., “Evaluate the Distortion of Modular Cascades,” Microwaves, Vol. 20, No. 3,1981, p. 67.

[3] Dixon, R., Spread Spectrum Systems with Commercial Application, New York: John Wileyand Sons, 1994.

194 Designing Multistage Amplifiers

C H A P T E R 1 1

Mixer/Modulator Design

11.1 Mixer Basics

Mixers are inherently nonlinear devices [1]. Mixers use the nonlinearity of theirdevices to convert input frequencies to new output frequencies. Most mixers areeither downconverting mixers that produce, at their output, a difference frequencybetween two input frequencies, or they are upconverting mixers, which produce attheir output a sum (or difference frequency) of their two inputs, raising thefrequency of the output, which is regarded as the signal. In general, the outputfrequency of a mixer is

Fout = Fr +/– Fl (11.1)

where Fr is the RF input frequency, and Fl is the LO input frequency.A basic mixer is shown symbolically in Figure 11.1. By virtue of their inherent

nonlinearity, mixers internally produce harmonics of their Fr and Fl input frequen-cies. These internally generated harmonic frequencies mix with each other to pro-duce unwanted output frequencies called N × M spurs [2]. A general expression ofthe N × M spur frequencies is

Fout (N × M) = NFR +/– MFL (11.2)

Since a mixer is a frequency-conversion device, its primary electrical specifica-tion is called conversion gain (or loss). Since the input Fr and Fl frequencies areunwanted at the output port (and at each other’s input ports), isolation specifica-tions are important for understanding the degree to which unconverted signals aresuppressed at the mixer’s various inputs and outputs. The three most importantisolations are L-to-R isolation, L-to-I (where I is the output port), and R-to-I isola-

195

Figure 11.1 The basic schematic symbol for a mixer function.

tion. It is important that these isolations be high enough to assure that the fre-quency-converted output signal is much stronger than non-frequency-convertedsignals from the mixer’s inputs. Noise figure is also an important specification for amixer. In the case of passive mixers (mixers that use diodes rather than transistorsand inherently exhibit conversion loss), the mixer’s noise figure is always equal to itsconversion loss [3]. In the case of active mixers (mixers using transistor devices),their noise figure may assume a value similar to, or higher than, that of an amplifierusing the same transistor and operating at the Fr frequency (downconverted noisefrom the image frequency may increase overall NF.) As with amplifiers, mixersgenerate two-tone intermodulation spurs. Like amplifiers, two-tone inter-modulation spurs represent an important performance parameter. In the case ofmixers, two-tone intermodulation performance is specified in terms of an inputintermodulation intercept point called IIP3. IIP3 is closely related to the concept ofOIP3 in an amplifier. The relationship between IIP3 and OIP3 is simply

IIP3 = OIP3 – Gconv (11.3)

LO power level for proper operation is also an important mixer specification. Asmentioned above, it is necessary to specify the N × M spurs of a mixer. Any mixercan be understood by performing a mathematical power-series analysis on its non-linear device in the presence of two input signals of different frequencies.

The power-series expression of the nonlinear behavior of a generalized activedevice may be written as

I(t) = I0 + K1V + K2V2 + K3V

3 + … (11.4)

Assuming that

V = V1cos 1t + V2cos 2t (11.5)

where

V1cos 1t is the R port signal.V2cos 2t is the L port signal.

Applying (11.4) to (11.5), we obtain an expanded expression for the sec-ond-order term as

I(t) = K2[(V1cos 1t)2 + (V1cos 1t)(V2cos 2t) + (V1cos 1t)

2] (11.6)

where the first and the third term are responsible for generating the second har-monic of the R and the L signals respectively. It is the center term that is responsiblefor mixer action.

By using a well-known trigonometric identity [4], it can be shown that the centerterm can be expanded as

I(t) = K2[(V1V2)/2]([cos( 1 – 2)t] + [cos( 1 + 2)t]) (11.7)

196 Mixer/Modulator Design

where

The first term is associated with the difference mixing frequency.The second term is associated with the sum mixing frequency.

Both sum and difference frequencies are always present at a mixer’s outputport. To eliminate one or the other, it will be necessary to filter out the undesirableoutput. An example of output filtering applied to downconverting andupconverting mixers is shown in Figures 11.2 and 11.3, respectively. This filteringprocess is most often accomplished by connecting a low-pass filter to the mixer’soutput to suppress the sum frequency output or by connecting a high-pass filter tothe mixer’s output to suppress the difference frequency output. See Chapter 6 formore detailed informatio on filter design.

11.2 Diode Mixers

Diode mixers having conversion loss rather than conversion gain are known as pas-sive mixers. Passive mixers use diodes as their nonlinear mixing devices. There areseveral kinds of diode mixers, depending on configuration and complexity. Thesimplest is called the single-ended diode mixer. The basic circuit schematic for a sin-gle- ended diode mixer is shown in Figure 11.4. The diode is shunted to groundacross a transmission line that delivers both the R and L signal to the diode. An RFchoke connecting the ungrounded terminal of the diode to dc ground provides aconduction path so that dc current may flow within the diode in response to R and L

11.2 Diode Mixers 197

Figure 11.2 The block diagram and spectrum of a downconverting mixer.

Figure 11.3 The block diagram and spectrum of an upconverting mixer.

input signal powers. By controlling the flow of dc current (using L power) to just theright current (where the diode’s operating point provides the maximumnonlinearity) it is possible to keep the mixer’s conversion loss to a minimum. Inwell-performing mixers of this class, conversion loss is expected to be in the 5–10 dBrange. High isolation is difficult to achieve with this type of mixer. Since the R and Lports are essentially hardwired, the L-to-R isolation is nearly zero, unless a diplexerdevice is provided at one or both ports. In practice, such a diplexer will be effectiveonly if the frequency separation between Fr and Fl is fairly large, which is not alwaysthe case. The L-to-I and the R-to-I isolations can be quite good, depending on thequality of the output port’s low pass filter. Since this mixer always experiences con-version loss, its noise figure is equal to the conversion loss (as described in Section8.3). The L power requirement is approximately 3 mW per diode. IIP3 for this classof mixer is approximately equal to the L power. To increase its IIP3, the mixer’s Lpower can be increased accompanied by adding two or more diodes in series,increasing the total forward voltage, Vf , which appears across the diode when it isstimulated into forward conduction, by the L power.

An important variation on the single-ended diode mixer is the single-balancedmixer, whose schematic diagram is shown in Figure 11.5. This type of mixerachieves a naturally high amount of L-to-I and L-to-R isolation by making use of atechnique called a virtual ground. When using a virtual ground, the L signal is splitinto two paths with a 180° phase difference, using a transformer (or a balun). Theout-of-phase secondary ports of the transformer are connected to the top andbottom of a series combination of two identical diodes. If the transformer has agrounded center tap, the center point of the diode pair is fixed at ground potential

198 Mixer/Modulator Design

Figure 11.4 The schematic diagram of a simple single-diode mixer.

Figure 11.5 The schematic diagram of a single-balanced two-diode mixer.

for the L signal by the virtual ground process. By connecting the R and I ports to thispoint in the circuit, the mixer achieves a naturally high amount of L-to-R and L-to-Iisolation as a direct result of the transformer’s virtual ground. The mixer’s R-to-Iisolation may be increased with the proper use of a low-pass (or a high-pass in thecase of upconversion) filter connected between the mixer’s R and I ports. Becausethere are two diodes in this mixer, the LO power and IIP3 are raised by 3 dB relativeto those in the single-diode mixer previously discussed.

The final type of passive diode mixer we shall discuss is the double-balanceddiode mixer, whose schematic diagram is shown in Figure 11.6. In this mixer, as inthe single-balanced mixer, virtual ground techniques are used to achieve high isola-tion by canceling the R and I signals at output ports from which we don’t wish themto escape. In the double-balanced case, two transformers (baluns) are used toachieve this goal. One transformer is connected to the R port, and the second one isconnected to the L port. By arranging four diodes in a ring configuration and con-necting two transformers to the diode ring, we create a situation where the L portenergy is cancelled by virtual ground effects before it can reach either the R or Iports. Likewise, the R power is cancelled by its transformer before it can reacheither the L or I port. The double-balanced mixer naturally achieves high L-to-Rand L-to-I isolations without the need for filters. Another benefit of this kind ofmixer is that by using a four-diode architecture, L power and IIP3 are increased by afactor of four relative to the single-diode case. The double-balanced diode mixer isabout as good as a passive mixer can get. For RFICs transistors can be easily config-ured to operate as diodes, as shown in Figure 11.7. By connecting the base and

11.2 Diode Mixers 199

Figure 11.6 The schematic diagram of a double-balanced four-diode mixer.

Figure 11.7 The collector and base terminals of a transistor are connected together in order tomake the transistor operate as a diode based on its emitter-base junction.

collector terminals together, the transistor’s base-to-emitter junction acts as a diode,which may be used in a wide range of mixer applications.

11.3 Single-Balanced Active Multiplying Mixers

Active mixers use transistors as mixing devices to simultaneously achievenonlinearity for the mixing process and gain to create conversion gain. As with thepassive mixers we have already discussed, active mixers can make use of differentialbalancing techniques to obtain excellent isolation.

Following T. Lee [5], the conversion gain of a single bipolar transistor may beanalyzed as follows. Using the exponential law for a bipolar transistor, expressing Ic

in terms of Vbe results in

Ic = Is exp(Vbe/VT) (11.8)

where

Is is the transistor’s saturation current.VT is the thermal voltage (25 mV at 25 C).

Expanding (11.8) to yield up to the second-order term for analyzing a mixergives

Ic = Idc [1 + Vin/VT + 1/2 (Vin/VT)2] (11.9)

The coefficient of the second-order term is given by

C2 = Gm1/2VT (11.10)

where Gm1 = ( Ic/ Vbe).Comparing with (11.7), we see that the voltage conversion gain is then given by

CGC V V

V= 2 in Lo

in

= C2 Vlo = Gm1 (Vlo/2VT) (11.11)

Equation (11.11) indicates that for a single bipolar transistor, mixer conversiongain is proportional to both Gm and Vlo. This conclusion indicates that conversiongain may be increased by increasing either the transistor’s size (to increase Gm) or byincreasing Vlo, or some combination of size and Vlo.

Although there is a variety of active mixer topologies, the most popular versiontoday is the so-called multiplying mixer. This simple mixer consists of a pair of dif-ferential amplifier transistors (see Chapter 7) whose current is controlled by a single“tail” transistor. The tail transistor acts as a gain control for the differential pair,and in so doing, it serves as a port whose inputsignal is multiplied mathematically bythe signal being amplified by the differential pair. If the tail transistor is controlledby a dc base current, this dc signal will simply act as a gain control since the signalbeing amplified by the differential pair will be multiplied by a constant (i.e. dc).However, if the input to the tail transistor is an ac signal, then the signal input to the

200 Mixer/Modulator Design

tail transistor will be mathematically multiplied by the signal amplified by the dif-ferential pair. This condition is exactly what is needed to construct a perfect mixer.

Next, we consider an analysis of the single-balanced bipolar mixer shown inFigure 11.8. Rs is the input source resistance, and Re is the emitter degenerationresistor connected to the “bottom” (tail like) transistor.

The small-signal collector current of Q1 can be calculated as

Ic1 = Vrf/(Rs + Re + 1/Gm1) (11.12)

Following B. Razavi [6], if the LO waveform has a 50 percent duty cycle (thetop transistors act as switches), Ic2 – Ic3 is equal to the product of Ic1 and asquare-wave toggling between +1 and –1, giving

Vout = (Vrf Rc) (4/ )(cosωLot)/(Rs + RE + 1/GM1) (11.13)

where Rc is the collector resistor of the “top” transistors.Multiplying Vrf by cos lot is equivalent to shifting Vrf in frequency by lo and

dividing Vout by a factor of two. By calling the output voltage Vif, we obtain

Vif = (2VrfRc/ )(Rs + Re + 1/Gm1) (11.14)

It follows that the voltage conversion gain is obtained by dividing Vif by Vrf,which is

CGv = (2Rc/ )(Rs + Re + 1/Gm1)/(Re + 1/Gm1) (Rs + Re + 1/Gm1) (11.15)

and with some simplification,

CGv = (2Rc/ )/(Re + 1/Gm1) (11.16)

For a matched input, Rs = Re + 1/Gm1.Therefore, with a matched input, the voltage conversion gain becomes

11.3 Single-Balanced Active Multiplying Mixers 201

Figure 11.8 The schematic diagram of a single-balanced active transistor mixer.

CGv = 2Rc/ Rs (11.17)

The power conversion gain can be calculated by expressing the IF power basedon Vif rms appearing across 2Rc as

Pif = V2rfrmsRc(2/ 2)/(Rs + Re + 1/Gm1)

2 (11.18)

The input power is given as

Pin = V Rrfrms s2 4/ (11.19)

Therefore, the power conversion gain is

CGp = Pif/Pin = 8RsRc/2(Rs + Re + 1/Gm1)

2 (11.20)

If the input is matched (i.e., Rs = Re + 1/Gm1), the power conversion gain simpli-fies to

CGp = 2Rc/2Rs (11.21)

The power conversion gain may be related to the voltage conversion gain as

CGp = (CGv)2 (Rs/Rl) (11.22)

where Rl = 2Rc.Therefore, the gain-control function of a differential pair forms the functional

basis of an ideal multiplying mixer. The schematic diagrams of a single-balancedmultiplying mixer are shown in Figures 11.7 and 11.9 (the mixer’s bias circuit,which uses a “totem pole” of three diodes). Notice that this mixer is single-endedonly in the R port, with the L and output (I) ports being differential. This means themixer’s L-to-R isolation and R-to-I isolation will be excellent. However, its L-to-Iisolation will be poor since the differential pair of transistors naturally amplifies theL signal, with the L port acting as an input and the I port acting as an output. There

202 Mixer/Modulator Design

Figure 11.9 “Totem pole” bias supply for the single-balanced transitor mixer.

is no virtual ground effect at work with these two ports, so the L signal appears atthe output (I port) unsuppressed. In the next section, we will discuss a fully differen-tial multiplying mixer (Gilbert cell), which solves this problem, but for now we mustlive with the poor L-to-I isolation. In downconverting mixer applications, the L sig-nal appearing at the output (I port) can be suppressed by a low-pass filter followingthe mixer. In upconverting mixer applications, the L signal can be suppressed with aband-pass filter, but the effectiveness of this technique depends heavily on how highin frequency the R signal is. If the R signal is very low in frequency, a filter of a verynarrow bandwidth will be needed in order to suppress the L signal at the output.The mixer’s layout (using InGaP/GaAs technology) is shown in Figures 11.10 to11.12. The layout of the mixer’s bias circuit is shown in Figure 11.12.

11.3 Single-Balanced Active Multiplying Mixers 203

Figure 11.10 The layout of the single-balanced transistor mixer.

Figure 11.11 Close-up of the transistor layout in the single-balanced transistor mixer.

Figure 11.13 shows the simulated output spectrum of the single-endeddownconverting multiplying mixer using a Gummel Poon InGaP/GaAs HBT device

204 Mixer/Modulator Design

Figure 11.12 The layout of the mixer’s bias tree. LO+, LO–, and RF pads correspond to connect-ing points within the mixer’s layout.

Figure 11.13 The simulated output spectrum, conversion loss, isolations, and waveform of adownconverting single-balanced transistor mixer.

model. The conversion gain of the mixer is about 5 dB for R and L signals ofapproximately 2.0 GHz. The number of N × M spurs depends on the harmonicorder used by the simulator. In this case, an order of seven was applied to the L sig-nal, and an order of three was applied to the R signal. Notice that the L-to-R isola-tion and the R-to-I isolation are excellent. However, as mentioned above, the L-to-Iisolation is nonexistent (there is gain). This mixer also works well as an upconverterwith approximately the same 5 dB conversion gain and isolations similar tothose experienced with downconversion. In the next section, we will discuss theextension of the multiplying mixer concept to a fully (three-port) differential mixerconfiguration.

11.4 Fully Balanced Active Multiplying Mixers (Gilbert cell)

A natural extension of the multiplying mixer discussed in Section 11.3 is a fully dif-ferential multiplying mixer, normally called a Gilbert cell mixer. A Gilbert cellmixer uses two of the single-ended mixers whose outputs are combined, as shown inthe block diagram given in Figure 11.14, to cancel out the L signal at the mixer’scombined output. This technique makes the Gilbert cell mixer fully differential inall three ports. Therefore, using this special mixer topology, we achieve extremelyhigh L-to-R isolation, L-to-I isolation, and R-to-I isolation simultaneously. TheGilbert cell mixer has become the mixer topology of choice for most RFIC designsintended for wireless communications due to its small size, high conversion gain,high natural isolations, and low LO power requirements. Today, almost allupconverting and downconverting IC mixers use some version of a Gilbert celltopology. The basic schematic diagram of a Gilbert cell mixer is shown in Figure11.15. A variant on this design, shown in Figure 11.16, uses inductor loads insteadof resistor loads between the LO differential pairs of transistors and the power sup-ply. The use of inductors is very helpful in maximizing conversion gain and poweroutput, but since the inductors are often chosen for their ability to “resonate out”other capacitive components in the schematic, such mixers are often narrowband inperformance. The use of resistor loads is usually reserved for less-demanding appli-cations where wide bandwidth is an important requirement.

11.4 Fully Balanced Active Multiplying Mixers (Gilbert cell) 205

Figure 11.14 A schematic diagram of a Gilbert cell mixer (represented as a pair of single-balanced transistor multiplying mixers) showing how the LO signal currents cancel to zero at themixer’s output load. This canceling of LO currents in the mixer’s output creates extremely highL-to-I isolation (and high L-to-R and R-to-I isolations) in this class of mixers.

206 Mixer/Modulator Design

Figure 11.15 The schematic diagram of a Gilbert cell mixer circuit with resistor loads and a trans-former output circuit. All element values to allow simulation are included in the diagram. Gilbert

Figure 11.16 The schematic diagram of a Gilbert cell mixer circuit with inductive loads and atransformer output circuit. All element values to allow simulation are included in the diagram. Theinductive loads increase the mixer performance because they create little or no dc voltage drop atthe top transistor’s collectors relative to Vcc. However, wide bandwidth operation may be limitedby making this choice. Gilbert cell mixers with inductive loads are often used in upconvertingtransmitting modulator applications.

The four transistors that respond to the LO signals (called the top transistors) ineffect act as switches that “commutate” (alternately change the direction of thedifferential signal as it enters the load) the mixer’s output signal to the differentialload at a rate determined by the LO frequency. This commutation process is shownschematically in Figures 11.17 and 11.18. The top transistors act as ideal switches(that is, if the LO signal is of sufficient strength to cause the transistors to be eitherfully on or fully off), then only two transistors at a time are a part of the conductionpath of the mixed signal flowing to the load, as shown in Figure 11.17. The signalapplied to the two transistors that are driven at the input frequency (called the bot-tom transistors) is conducted through the two “turned-on” top transistors, wheremixing with the LO signal occurs. These mixing product currents flow into the dif-ferential load and appear at the load as a superposition of new frequencies. How-ever, as shown in Figure 11.14, the LO signal currents, which are not commutatedat the load (unlike the mixed output signals, which are commutated), are alwaysadded up (and cancelled) at the load in two equal amounts, which are exactly 180ºout of phase (flowing out of the collectors of the two “turned-on” top transistors).This means that, ideally, the LO signals are completely cancelled in the load. Inactual physical mixers, several nonideal situations can lead to reintroduction of theLO signal at the load. Chief among these LO regenerators are imbalance in thephysical layout of the Gilbert cell, differences in gain between the left-hand andright-hand bottom transistors, and side-to-side imbalance in the straybase-to-collector capacitance in the top and bottom transistors. It doesn’t take

11.4 Fully Balanced Active Multiplying Mixers (Gilbert cell) 207

Figure 11.17 A schematic diagram of a Gilbert cell mixer showing how the LO transistors playthe role of switches during alternating half–LO cycles. During this commutation process, the direc-tion of the mixer’s output current alternatively changes direction as it flows into the transformerload.

much imbalance to cause a significant amount of LO regeneration. If the bottomtransistors have the equivalent of as little as 2 mV difference in their Vbe, theLO-signal-to-mixed-output-signal ratio may be as high as –25 dB. Also, if the imbal-ance in base-to-collector stray capacitance is as much as 10 fF, theLO-signal-to-mixed-output-signal ratio can be as high as –25 dB. Therefore, it isimportant to be sure the ultimate layout of Gilbert cell mixers is extremely symmet-ric and totally free from imbalance in parasitic capacitances. Much care must betaken at the layout level to ensure that these conditions are met. In some applica-tions, in particular transmitting mixers (modulators), excessive LO regeneration canbecome a significant problem. In these cases, provided all precautions have beentaken during layout, an alternative way might be to provide some form of gainadjustment in the bottom transistors to ensure perfect side-to-side balance. Thistechnique works if the root cause of the LO regeneration is gain imbalance. How-ever, if the root cause is imbalance in the base-to-collector capacitance, gain adjust-ments will not be effective in canceling the regenerated LO signal because of theinherent 90º phase shift between the conductive currents associated with gain con-trol and the reactive currents associated with the unbalanced stray capacitance. Inthis case, layout modifications are the only recourse. This subject requires very care-ful attention by the designer.

Next we will proceed with a small signal analysis (in contrast to the switchingmixer descriptions given above) of a Gilbert cell mixer. Following P. Gray [7], thefollowing is a small-signal analysis of a multiplying-type Gilbert cell mixer. Con-sider the emitter-coupled pair shown in Figure 11.19(a). The collector currents of Q1

and Q2 are given as

208 Mixer/Modulator Design

Figure 11.18 A schematic diagram of a Gilbert cell mixer showing how the top transistors playthe role of switches during the second half-cycle. The output current reverses direction in thetransformer load during this second half of the commutation process.

Ic1 = Ie/[1 + exp(–Vid/VT)] (11.23)

Ic2 = Ie/[1 + exp(+Vid/VT)] (11.24)

where Vid is the differential input voltage, and VT is the thermal voltage, and Ie is thetotal emitter current of the differential pair.

The differential collector current, Icd, is

Icd = Ic1 – Ic2 = Ie tanh(Vid/2VT) (11.25)

As an approximation,

tanh(Vid/2VT) = Vid/2VT

for Vid/2VT << 1.

Therefore, the differential collector current becomes

Icd = Ie(Vid/2VT) (11.26)

Ie is a bias current that can be made equal to

Ie = K0(Vi2 – Vbeon) (11.27)

by replacing the current source with a third transistor whose input signal is Vi2.Therefore,

Icd = K0Vid(Vi2 – Vbeon)/2VT (11.28)

Equation (11.28) tells us that the differential collector current, Icd, is propor-tional to the product of the differential input voltage, Vid, and the voltage Vi2, whichcontrols the current source. This circuit now functions as a mathematical multiplierwith Vid × Vi2 as its output. We see from this result that each half of Gilbert cell mix-ers operating under small-signal conditions are truly analog multipliers of the twoinput signals.

Next, consider the circuit diagram of a complete Gilbert cell mixer as shown inFigure 11.19(b). As before, the collector currents are given as (noting that the collec-

11.4 Fully Balanced Active Multiplying Mixers (Gilbert cell) 209

Figure 11.19(a) The schematic diagram of a differential pair of transistors.

tor currents of the bottom transistors are the total emitter currents of the top of thetransistors):

Ic3 = Ic1/[1 + exp(–V1/VT)] (11.29)

Ic4 = Ic1/[1 + exp(+V1/VT)] (11.30)

Ic5 = Ic2/[1 + exp(+V1/VT)] (11.31)

Ic6 = Ic2/[1 + exp(–V1/VT)] (11.32)

The currents Ic1 and Ic2 are related to V2 by using (11.23) and (11.24). Com-bining Ic3, Ic4, Ic5, and Ic6 in terms of V1 and V2 is expressed as

Ic3 = Ie/[1 + exp(–V1/VT)] [1 + exp(–V2/VT)] (11.33)

Ic4 = Ie/[1 + exp(–V2/VT)] [1 + exp(+V1/VT)] (11.34)

Ic5 = Ie/[1 + exp(+V1/VT)] [1 + exp(+V2/VT)] (11.35)

Ic6 = Ie/[1 + exp(+V2/VT)] [1 + exp(–V1/VT)] (11.36)

The mixer’s differential output current can then be expressed in terms of thesefour collector currents as:

210 Mixer/Modulator Design

Figure 11.19(b) The schematic diagram of a Gilbert cell mixer circuit composed of multiple dif-ferential pairs. No loads are included in the diagram.

Icd = (Ic3 + Ic5) – (Ic6 + Ic4) (11.37)

or Icd = (Ic3 – Ic6) – (Ic4 – Ic5)

And, finally,

Icd = Ie[tanh(V1/2VT)] [tanh(V2/2VT)] (11.37a)

Equation (11.37) shows that the dc transfer characteristics of a Gilbert cellmixer are the product of the hyperbolic tangent of the two input voltages.

Using the approximation

tanh(x) = x – x3/3 + … (11.38)

and assuming that x << 1 (the small-signal assumption), the hyperbolic tangentfunctions may be expressed as tanh(x) = x.

Applying this result to (11.37), we arrive at the final result that

Icd = Ie (V1/2VT) (V2/2VT) = (Ie/4VT2) (V1V2) (11.39)

Equation (11.39) is the characteristic of a perfect multiplying mixer undersmall-signal conditions. This multiplying behavior continues until the LO signalgrows to the point that the top transistors begin to act as switches, as previously dis-cussed. Therefore, Gilbert cell mixers that have two clearly defined nodes of opera-tion; a small signal true analog mutliplying mode, and a large LO level mode, wheretop transistor switching action takes over. This behavior can be clearly seen in Fig-ure 11.20, where the conversion gain increases with LO power with a 1:1 scope atlow LO powers (small signal, multiplying region), until a critical LO power isreached (about –10 dBm), afterwhich the conversion gain becomes a constant indi-cating the top transistors are entering switching mode operation. The linear range ofa Gilbert cell mixer can be extended by using hyperbolic tangent predistortion onboth the V1 and V2 inputs. To increase conversion gain of this mixer, it is necessaryto increase the devices size in order to increase Ie. Typically, all transistors shouldoperate at the same current density, so if the top transistors (Q3, Q4, Q5, and Q6)have a nominal size of one, Q1 and Q2 are required each to have a nominal size oftwo. Therefore, the tail transistor, which is functioning as a current source, musthave a nominal size of four.

Gilbert cell mixer circuits are naturally arranged in what is know as a “totempole” configuration with the L transistors on top, the R transistors below them, andthe “tail” transistor current sources on the bottom. In order to bias the bases of allof these devices properly, it is necessary to use an ascending base-bias power supplycalled a bias tree, as shown in Figure 11.9. The bias tree uses base-to-emitter diodesformed by connecting the base of a transistor to its collector. These diodes are alsoconnected in a totem pole arrangement such that the dc voltage at the top of the firstdiode will be Vbe, the voltage at the top of the second diode will be 2 × Vbe, and thevoltage at the top of the third diode will be 3 × Vbe. dc voltage is a major issue withGilbert cell mixers because a totem pole configuration causes transistor biasingvoltage to add up quickly, and with three totem pole levels, the supply voltage must

11.4 Fully Balanced Active Multiplying Mixers (Gilbert cell) 211

be at least three times the base-to-emitter voltage of the individual transistors. Wecan easily estimate the dc biasing requirements for these mixers. The voltage acrosseach transistor in the totem pole will be at least Vbe. For InGaP/GaAs HBT technol-ogy, Vbe = 1.4V, which means the supply voltage must be at least 4.2V; perhaps 5.0Vis a good choice since it is a standard voltage in most systems. For SiGe technology,Vbe = 0.70V, which means the supply voltage must be at least 2.1V, indicating thatoperation in 3.0V systems is quite comfortable with SiGe technology. From thestart, we see a natural tendency to use SiGe in 3.3V battery-powered handheld sys-tems and GaAs HBT in system infrastructures where 5.0V power is available. This isquite a comfortable partitioning according to technology, which is true for mostRFIC components, with power amplifiers being the only exception. Today, mostlarge RFICs for handheld applications will use SiGe or RFCMOS technologies, andPAs in handheld applications and all other types of RFICs for infrastructure areusing GaAs HBT. A mixer’s bias tree, which uses diodes to produce biasing voltagesin steps of Vbe, 2Vbe, and 3Vbe in order to provide the mixer with the proper base-biaspotentials. Dropping resistors between the bias tree and the transistor’s bases areused to set the base current. In the case of mixers, it is best to experiment a little withthe bias point to be sure that it is set to a point that yields maximum conversion gain.This may not be the device’s maximum current point since, in mixer applications,the device’s degree of nonlinearity is a key factor in determining overallperformance.

Modern simulators are capable of analyzing a wide variety of Gilbert cell mixerperformance parameters. Figure 11.20 shows the Gilbert cell mixer’s conversiongain (as a downconverter) plotted as a function of LO power. Notice that full con-version gain is achieved at an LO power of –10 dBm. Using any more LO powerwould waste battery life in a handheld application. This ability to work to full per-formance with minimum LO power is one of the great strengths of the Gilbert cell

212 Mixer/Modulator Design

Figure 11.20 The simulated conversion gain (as a function of LO power) of the Gilbert cell mixeroperating as a downconverter at an input frequency of 1,800 MHz. Maximum conversion gain isachieved at an LO power of –10 dBm. At low LO powers this mixer functions as a multiplier, with a1:1 relationship between LO power and conversion gain. Above –10dBm Lo power, the mixerenters a switching mode of operation.

mixer. In Figure 11.21, a plot of conversion gain as a function of RF power is given.Notice that conversion-gain compression begins to occur for RF power levelsgreater than –25 dBm. This means that this particular mixer is best suited for use inreceiver applications where the input RF power will be quite low. If uncompressedoperation at higher RF powers is needed in a particular application, it may be neces-sary to increase the size of all transistors and increase their overall dc current.Notice that with the Gilbert cell topology, keeping the dc current density a constantin all transistors means it will be necessary to size the R transistors to be twice thearea of the L transistors (there are four L transistors and only two R transistors).The tail transistor must carry all of the dc current, so it must be sized to be twice thearea of the R transistor and four times the area of the L transistors.

All three of the mixer’s isolations are shown in Figure 11.22. Notice that allisolations are in the hundreds-of-decibels range, indicating perfect cancellation bythe virtual grounds provided at the three differential ports. If, in practice, the mixeris not perfectly balanced, one or more of the isolations will suffer and possiblydegrade to the 30–60 dB range. It is very important during layout of Gilbert cellmixers to take particular care to be sure the mixer is perfectly balanced physically interms of all interconnections. Whatever circuit elements appear on one side of themixer, the same elements must appear on the other side of the mixer. If this practiceis not strictly adhered to, the mixer’s isolations and its performance may suffer, per-haps profoundly. For instance, Figure 11.23 shows the resulting degradation in iso-lation if a single transistor is disabled in a Gilbert cell mixer. In some cases, theisolation may actually disappear. Figure 11.24 shows the simulated spectrum of aGilbert cell mixer being operated as an upconverter. Notice the two strong outputsignals, which correspond to Fr + Fl and Fr – Fl. These are the two possibleupconverted outputs. To select a single output frequency, a band-pass filter must belocated at the mixer’s output. Notice how suppressed the L frequency output iscompared to the upconverted outputs. This is L-to-I isolation at work. Figure 11.25shows the simulated upconverted conversion gain as a function of LO power. Just

11.4 Fully Balanced Active Multiplying Mixers (Gilbert cell) 213

Figure 11.21 The simulated mixer conversion gain as a function of RF power input with an LOpower of –10 dBm. The 1 dB gain-compression point for this Gilbert cell mixer is –20 dBm.

as in the downconversion case, the conversion gain has reached its full extent at anLO power level of –10 dBm.

214 Mixer/Modulator Design

Figure 11.22 Simulations of a Gilbert cell mixer’s RF and LO match, shown on a Smith chart as afunction of frequency, and its three isolations, which are all extremely high due to virtual ground

Figure 11.23 By disabling one transistor in a Gilbert cell mixer, all of the mixer’s isolations sufferdrastically as a direct result of this (and any other kind of) side-to-side imbalance.

Mixers also suffer from intermodulation spurs, just as amplifiers do. Thesimulations must now deal with three input signals—the two RF tones and the LOsignal—and, so, the harmonic-balance controller needs some adjustment. At thetransistor level, the simulator schematic does not change. Figure 11.26 shows theconversion gain (per tone) and the output intermodulation intercept point (OIP3),plotted as a function of LO power. Since both conversion gain and OIP3 are stillincreasing at –10 dBm LO power, it is possible that further performance improve-ments might be achieved using even higher LO power. In Figure 11.27, the ADSmix function is used to demonstrate exactly which frequencies are being generatedby the third-order and fifth-order nonlinear processes that contribute to

11.4 Fully Balanced Active Multiplying Mixers (Gilbert cell) 215

Figure 11.24 The simulated input and output spectra of an upconverting Gilbert cell mixer. Theinput frequency is 500 MHz, and the LO frequency is 2.2 GHz, resulting in an upconverted USB

Figure 11.25 The simulated upconverting conversion gain of the Gilbert cell mixer is plotted as afunction of LO power. Maximum conversion gain is 11 dB, which is achieved at an LO power of–10 dBm.

intermodulation. The two main tones are in the center of the chart with theintermodulation spurs arranged symmetrically around the main tones.

The Gilbert cell mixer’s noise figure can be simulated in ADS by connecting anonport L input source to the mixer’s LO port. The harmonic-balanced controllermust be placed in its nonlinear noise mode to perform this simulation. Thenoise-figure and conversion-gain simulations are given in the simulation status win-dows, shown in Figures 11.28. The noise frequency in these results is the IF fre-quency of the downconverting mixer. Noise figure is stated in both SSB and DSB

216 Mixer/Modulator Design

Figure 11.26 The simulated conversion gain and OIP3 of an upconverting Gilbert cell mixer areplotted against LO power. Best performance is achieved at an LO power of –10 dBm.

Figure 11.27 A chart of N × M mixing frequencies of a Gilbert cell downconverting mixer show-ing the third- and fifth-order two-tone intermodulation output frequencies.

form; however, the SSB form is most meaningful when compared with experiments.The DSB form of noise figure is always 3.0 dB below the SSB form of noise figurebecause DSB noise figure is defined assuming that a signal power is present at themixer’s image frequency, thus raising the overall signal-to-noise ratio by 3.0 dB.

11.5 I/Q Mixers

Gilbert cell mixers are very useful for creating what are called I/Q mixers and I/Qmodulators. These devices use two identical mixers whose common LO signal hasbeen phase-shifted by 90° at one of the mixers relative to the other mixer. The LOinput signal is split in-phase, and two equal-amplitude, 90° phase-shifted signals aredelivered to the mixer’s LO inputs. In the case of the downconverting I/Q mixers,the phase-modulated input signal is downconverted and, at the same time, reducedinto I and Q phase paths, which appear at the output. This technique is especiallyuseful in zero IF receiving systems, where the received signal phases need to be sepa-rated into I and Q paths prior to conversion to a digital format in a high-speed ADC.One challenge that must be faced when using this circuit configuration is dc offsets(see Chapter 3). These offsets may be caused by strong interfering signals mixingwith themselves, producing strong dc output voltages, or they may result from LOleakage signals returning through the input port to remix with the LO and produce

11.5 I/Q Mixers 217

Figure 11.28 Simulated SSB and DSB noise figures of a Gilbert cell mixer. Notice the 3 dB differ-ence between the two noise figures (the DSB noise figure is lower by 3 dB). This is because thedefinition of DSB noise figure assumes the presence of signal power at both the signal frequencyand the image frequency, raising its SNR by 3 dB (and lowering its noise figure by the sameamount) relative to the SSB noise figure. An SSB noise-figure measurement assumes that only anoise, and no signal, contribution occurs at the image frequency.

similar, strong dc-offset voltages at the mixer’s output. dc offsets can be very trou-blesome and difficult to eliminate. The problem is especially severe because the gainof the dc-coupled VGA amplifier that follows the mixer is very high. As is the case inany receiver, a zero IF receiver using an I/Q mixer followed by a VGA amplifier musthave about 90 dB overall gain. If the LNA has 20 dB gain, and the mixer has 10 dBgain, the VGA must have 60 dB gain to sufficiently amplify weak signals up to a levelat which they can be converted into digital form by the ADCs. Any dc offset will beamplified by 60 dB, immediately sending the VGA output to the rail. The most com-mon technique for dealing with dc offsets is to ac-couple the mixer to the VGA(which is placed between the mixer and the ADC). This technique has two associ-ated problems. First, ac-coupling the output base-band signal requires large capaci-tors that may not be easily located on-chip because of their physical size. The secondproblem is that any size capacitor (even a very large one) will still represent ahigh-pass filtering function. This means, then, that there will be some low-frequencysignal energy lost via high-pass filtering. This loss creates an inevitable reduction insignal-to-noise ratio. For these reasons, it has become popular to associate a feed-back loop with the VGA that follows a mixer whose design has the ability to cancelout dc-offset signals. Such feedback loops greatly complicate the design of the VGA;however, it is often a preferable alternative, considering the two major difficultiesassociated with the ac-coupling technique discussed above.

Another issue that could occur with I\Q mixers is the leakage of signal from onemixer to another, each being connected to a common LO distribution line. Sucharchitectures are often found in receiver systems with multiple inputs. A simple curefor this problem is to locate individual LO buffer amplifiers (see Chapter 7) at theLO terminals of each mixer. This is good practice in general and should be followedwith all designs involving multiple mixers. The buffer amplifier acts as a one-waystreet, allowing the LO signal to enter the mixer but not allowing signals generatedwithin the mixer to be introduced onto the common LO distribution line. Also, LOdistribution line mismatches will not affect the mixer in any way because of the iso-lation capability of the buffer amplifiers. An excellent design for these amplifiers is adifferential cascode amplifier topology (see Chapter 7). Figure 11.29 shows a blockdiagram of two I/Q mixers with buffer amplifiers connected to a common differen-tial LO bus line. Figure 11.30 shows the simulated performance of an LO bufferusing cascode topology. Since Gilbert cell receiving mixers require very little LOpower (–10 dBm or less), the LO buffer amplifier need only be of minimum size. Asingle-emitter-finger transistor should be sufficient for this purpose. See Chapter 7for additional information on high-isolation differential amplifiers.

It is a good practice with I/Q mixers to keep all circuits related to the I/Q mixerin differential form. By employing this practice, it is possible to avoid using a differ-ential-to-single-ended converter (i.e., balun) on-chip or, worse yet, having to gooff-chip (then back on-chip after the balun) in the middle of the circuit in order touse an off-chip balun for this purpose. The price that is paid is the need to build allcircuits in the receiver’s chain in fully differential form, which would mean that theLNA would have to be differential. The mixer, of course, is already differential, andthe LO and its buffers are all differential. If low-pass filters follow the mixer, theyalso must be differential. Even the input to the VGA would need to be differential.

218 Mixer/Modulator Design

By adhering to this practice, the designer avoids having to employ more than onebalun (either on- or off-chip) in the receiver chain.

11.6 I/Q Modulators

Following P. Gray [7], Gilbert cell multiplying mixers may also be used as balancedmodulators. This process is accomplished by making use of large LO signals essen-tially to switch the top transistors on and off in order to commutate the output cur-rent back and forth in the differential load resistor. It is very efficient in the case of a

11.6 I/Q Modulators 219

Figure 11.29 Using buffer amplifiers to increase the isolation between multiple mixers connectedto a common LO distribution line.

Figure 11.30 Simulated S-parameters of a cascode differential buffer amplifier.

modulator to drive the LO port (differential voltages V1+, V1

–) with a large-signalsquare-wave. This signal level is assumed to be large enough to fully turn on or offthe top transistors (switching mode operation). Therefore, in the case of a modula-tor, the small-signal input voltage (differential voltages V2

+, V2–) is alternately multi-

plied by +1 and –1. The large-signal output that results from this switching mode ofoperation must be Fourier-analyzed to obtain the desired frequency components.Assuming that the mixer’s small-signal modulation input voltage (V2

+, V2–) is a sine

wave, which may be expressed as

Vm = Vp cos mt (11.40)

then the large-signal LO square-wave voltage may be expressed as

V A n tc n cn

==

∞

∑ cos ω1

(11.41)

where An = sin(n /2)/(n /4).Therefore, the resulting output signal is the product of the input and LO signals:

( )V K V V K A V t to c m n p m cn

= ==

∞

∑ cos cosω ω1

(11.42)

Applying trig identities for the multiplication of cosines, we arrive at an expres-sion for the frequency components in the modulator’s output voltage:

( ) ( ) ( )[ ]V K A V n t n to n p c m c mn

== + + −=

∞

∑ / cos cos21

ω ω ω ω (11.43)

By adding a dc component to the modulator’s input voltage, the modulatingsignal becomes

Vm = Vp (1 + m cos mt) (11.44)

where m is the modulation index.We arrive at a final expression for the modulator’s output voltage:

( ) ( ) ( ) ( )[ ]V K A V n t m n t m n to n p c c m c mn

== + + + −=

cos ( / )cos ( / ) cosω ω ω ω ω2 21

∞

∑ (11.45)

The first term in 11.45 is the carrier term appearing at the square-wave’s fre-quency and all harmonics of the square-wave’s frequency. It should be noted thatthe carrier term is greatly suppressed by a well-designed Gilbert cell balanced modu-lator. The second term in 11.45 is the “sum” mixing term containing the modula-tion input frequency plus the square-wave’s frequency and all harmonics. The thirdterm is the “difference” mixing term between the modulation input frequency minusthe square-wave’s frequency and all harmonics.

220 Mixer/Modulator Design

I/Q modulators are simply I/Q mixers operating in reverse. As is the case withtheir mixer counterpart, I/Q modulators use Gilbert cell mixers, with one mixerbeing fed a common LO signal 90° out of phase with the other. Instead of having ahigh-frequency RF input signal and a low-frequency output signal, as with thedownconverting mixer, the I/Q modulator has a low-frequency (perhaps baseband)input signal and produces a high RF frequency output. In fact, the output of themodulator often consists of sidebands symmetrically arranged on each side of theLO’s carrier signal, which has been suppressed by the Gilbert cell mixer’s highL-to-I isolation. The input signal to the modulator is often a pair of analog signalsproduced by a digital-analog converter, taking the I and Q digital signals from theradio’s DSP and converting them into an analog form that is capable of driving themodulator. Very often the transmitter chain of a wireless transceiver consists of sim-ply an I/Q modulator followed by a PA (see Chapter 3). Since the modulated signalis the product of an I/Q modulation process, the output signal from the modulator iscapable of assuming many different types of phase modulations, including BPSK,QPSK, N-QAM, and OQPSK.

The primary specifications for an I/Q modulator are conversion gain, carriersuppression (L-to-output isolation), IIP3, and its output power. The major differ-ence between I/Q mixers and I/Q modulators, apart from the obvious differences infrequency inputs and outputs, are their power-handling capabilities. Quite often, amodulator will use significantly larger transistors than an equivalent mixer, andperhaps instead of using purely resistive loads, the modulator will make use ofinductive internal loads. The use of inductive loads will increase both power outputand gain, but at the expense of bandwidth since most inductive loads are resonatedby a parallel capacitor. This means high-performance operation will be availableonly over a narrow range of frequencies. Since modulators often operate athigher signal powers than mixers, it may be necessary to supply greater LO powerto a modulator than that needed by an equivalent mixer. LO power on the orderof 0 dBm is used by many I/Q modulators to increase both power output and IIP3.

I/Q modulators may be simulated by using a relatively low-frequency sine waveinput and observing the mixer’s output spectrum. This spectrum will contain twooutput signals, one at (Fl + Fr) and the other at (Fl – Fr).

11.7 Design Example 6: Cellular/PCS Downconverting Mixer RFIC

This design example involves both the three-transistor Darlington-like LNA designdiscussed in Chapter 8, low pass filters and differential phase shifters discussed inChapter 6, and the Gilbert cell mixer discussed in this chapter. This design exampleis the work of Amer Droubi in partial fulfillment of the requirements of the courseELEN 359A (“Advanced RFIC Design”) at Santa Clara University, Santa Clara,California. The RFIC die resulting from this design is a single-chip I/Q receiver frontend containing LNAs, mixers, a 90° LO phase shifter, and low-pass filters. Theinput frequency is approximately 1.9 GHz, and the downconverted output is fromdc to 100 MHz. Since this RFIC was designed for operation from a +5.0V supply,InGaP/GaAs HBT technology was used. If the design had been intended for +3.0V

11.7 Design Example 6: Cellular/PCS Downconverting Mixer RFIC 221

operation, SiGe HBT technology would have been the best choice because of SiGe’slow Vbe (0.70V versus 1.4V with InGaP/GaAs HBT).

The block diagram for the RFIC is shown in Figure 11.31. The design is entirelydifferential with a pair of LNAs in the front end feeding a pair of Gilbert cell mixers.The Gilbert cell mixers are fed differentially by 90° phase-shifted LO signals. Theresult is an in-phase (I) downconverted output from the mixer, which is fed with thenon-phase-shifted LO signal, and a quadrature-phase (Q) downconverted outputfrom the mixer, which is fed with the 90° phase-shifted LO signal. Both the I and Qdownconverted outputs are low-pass-filtered by a lumped-element low-pass filter ofthe type described in Chapter 6. The LNA circuit’s schematic is shown in Figure11.32. The LNA’s gain is approximately 30 dB at 1.9 GHz, with excellent input andoutput matches. The noise figure of the LNA is 1.6 dB at 1.9 GHz.

The Gilbert cell mixer’s schematic diagram is shown in Figure 11.33. Because ofthe nature of Gilbert cell mixers, all three ports are fully differential. The mixer’sschematic diagram follows the standard form for a Gilbert cell mixer discussed ear-lier in this chapter. A plot of the mixer’s conversion gain as a function of RF powerinput shows a 1 dB gain compression of about –10 dBm at the mixer’s input. For anLO power of –10 dBm, the mixer’s conversion gain is approximately 13 dB. For LOpowers above –15 dBm, the value of OIP3 is a nearly constant 0 dBm. The simulatedSSB noise figure of the mixer is approximately 7 dB.

A schematic diagram for the differential 90º LO phase shifter is shown inFigure 11.34. This phase shifter uses a resistive 6 dB power divider (using three17 ohm resistors) to split the LO power into two channels, with one channel to bephase-shifted by 90° relative to the other channel. The 90° phase shift takes place ina differential low-pass filter of the type discussed in Chapter 6. This type of filter hasa natural 90° phase shift at its start of roll-off frequency. The differential outputsthat pass through the low-pass filter are phase-shifted by 90° relative to the input;however, the differential outputs that do not pass through the low-pass filter are notphase-shifted relative to the input. At 1.9 GHz. the phase shifter’s insertion loss isabout 6 dB, which is determined entirely by the resistive power splitter. At 1.9 GHz,its phase shift is about 70°. The phase shifter element values need to be adjusted

222 Mixer/Modulator Design

Figure 11.31 The block diagram of a downconverting I/Q receiver RFIC design example usingInGaP/GaAs technology.

slightly to bring this value to a perfect 90°. Another consideration that may have abearing on this situation is the impedance level at the mixer’s LO port. If this imped-ance is much greater than 50 ohms, it may be necessary to add a termination resistorin parallel with the phase shifter’s output to ensure that the low-pass filter circuitsare terminated in 50 ohms, ensuring their proper operation. This is necessarybecause the filter’s terminating impedance will affect its phase shift, causing phaseerrors.

The schematic diagram for the lumped-element low-pass filters that follow theGilbert cell mixers is shown in Figure 11.35. The purpose of these low-pass filters isto reject all spurious and interfering signals that appear in the mixer’s outputs. If theapplication of this RFIC is in a direct-conversion receiver, the low-pass filters willplay the role of the narrowband IF filters, which determine the ultimate selectivityof a superheterodyne receiver, as discussed in Chapter 3. The filter has very lowinsertion loss until about 100 MHz, then begins its roll-off. By 4 GHz, the filterhas rolled off by 60 dB. Spurious mixer products and interfering signals that lie

11.7 Design Example 6: Cellular/PCS Downconverting Mixer RFIC 223

Figure 11.32 The schematic diagram of the RFIC’s differential LNA.

224M

ixer/Modulator D

esignFigure 11.33 The schematic diagram of the RFIC’s Gilbert cell mixer.

above 1 GHz will experience considerable rejection as a result of the action of thisfilter.

All of the circuit pieces of the system are now complete, so we can now turn ourattention to assembling the entire system. The resulting overall system’s perfor-

11.7 Design Example 6: Cellular/PCS Downconverting Mixer RFIC 225

Figure 11.34 The schematic diagram of the RFIC’s 90º differential LO phase shifter.

Figure 11.35 The schematic diagram of the RFIC’s low-pass filters.

mance predictions, using Agilent’s AppCAD, are a gain of 40 dB, a noise figure of3.2 dB, an OIP3 of –1 dBm, and an IIP3 of –40 dBm. These numbers are simplyscalar additions of the already simulated component performances. Therefore, theAppCAD prediction is only a “rough guess” of what the top-level system perfor-mance might be. However, such an analysis is very enlightening because if it falls sig-nificantly short of the desired top-level performance, it may be a strong indicationthat one or more of the system’s component parts needs to be redesigned to improveperformance.

The next design step is to combine all ADS component models into a singletop-level system configuration for final simulation. The top-level schematic diagramfor the entire RFIC is shown in Figure 11.36. Since ADS is hierarchical in its organi-zation, the individual circuit schematics for the LNA, mixer, phase shifter, and fil-ters can be placed into symbolic icons that are connected in the top-level schematic.The simulated conversion gain is in excellent agreement with the AppCAD analysis:both predict about 40 dB. The resulting small-signal conversion gain is about 39 dBwith roll-off beginning around –50 dBm. The P – 1 dB power is approximately –50dBm, which is about 10 dB lower that the goal of –40 dBm. Best performance inboth channels is achieved with an LO power of about –6 dBm.

By using AppCAD, the system’s noise figure and OIP3 may be inferred from thecomponent simulations. Using this technique, we arrive at a systems noise figure of3.0 dB and a systems OIP3 of 0 dBm. The relative phase shift between the system’s Iand Q output channels may be determined directly by simulating the voltage wave-form (in time domain) at the I and Q channel loads and recording the time delay inthe waveform’s zero crossings, as shown in Figure 11.37. By using this method, wearrive at an I-to-Q phase offset of about 66°, which is in excellent agreement withthe simulated 70° phase offset of the LO phase shifter. This number can be movedcloser to 90° by making small adjustments in the element values in the phase shifter’slow-pass filter.

Figure 11.38 shows a layout for the entire RFIC. The die size is 3,000 × 1,950um. A blow-up of the LNA layout is given in Figure 11.39, and a blow-up of themixer’s layout is given in Figure 11.40.

226 Mixer/Modulator Design

11.7D

esign Examp

le 6: Cellular/PC

S Dow

nconverting Mixer RFIC

227Figure 11.36 A schematic diagram for simulating the overall performance of the RFIC.

228 Mixer/Modulator Design

Figure 11.38 The layout of the RFIC.

Figure 11.37 A time domain plot of the RFIC’s I channel output and its Q channel output plottedon a common time scale. The phase offset between the I and Q channels is nearly 90º (i.e., thetime offset between channels divided by one period times 360º).

11.7 Design Example 6: Cellular/PCS Downconverting Mixer RFIC 229

Figure 11.40 A layout blow-up in the area of the RFIC’s Gilbert cell mixer.

Figure 11.39 A layout blow-up in the area of the RFIC’s differential LNA.

References

[1] Maas, S., Microwave Mixers, Boston: Artech House, 1986.[2] Henderson, B., “Reliably Predict Mixer IM Suppression,” Microwaves and RF, Vol. 22,

No. 11, 1983, p. 63.[3] Mattauch, R., “Frequency and Noise Limits of Schottky-Barrier Mixer Diodes,” Micro-

wave J., Vol. 28, No. 3, 1985, p. 101.[4] Burington, R., Handbook of Mathematical Tables and Formulas, Sandusky, OH: Hand-

book Publishers, 1955.[5] Lee, T., The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge: Cam-

bridge University Press, 1998.[6] Razavi, B., RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.[7] Gray, P., et al., Analysis and Design of Analog Integrated Circuits, New York: John Wiley

and Sons, 2001.

230 Mixer/Modulator Design

C H A P T E R 1 2

Frequency Multiplier Design

12.1 Frequency Doublers

Diodes are often used as the nonlinear elements for creating multiplying-type fre-quency translators [1]. A second approach to frequency translation is to use a mixer(Gilbert cell is best) for translating one frequency into another. However, in certainapplications, this approach is unnecessarily complex, and a simple diode frequencymultiplier will suffice. The simplest type of diode frequency multiplier is thedoubler. A doubler takes an input frequency and outputs its second harmonic, whilesuppressing the input fundamental signal at the output. Also, third- and all otherhigher-harmonics are suppressed by the doubler.

How do doublers work? Their topology is remarkably similar to somepower-supply topologies. One or more diodes (which can be created in bipolar ICtechnology by connecting a transistor’s base to its collector and making use of thediode associated with the transistor’s base-to-emitter junctions) are connected sothat an input sine wave is cut up into an output of half-wave-rectified sine wave. Itturns out that half-wave-rectified sine waves are very rich in second-harmonicenergy. Many power supplies, which use the same general topology, are subject toan output ripple at 120 Hz, double the 60 Hz input, about the intended dc output.Figure 12.1 shows the IV characteristic of a GaAs HBT diode of the type that is use-ful for constructing frequency multipliers. Simulating with the large-signal transis-tor models works fine. The key to making a successful doubler circuit is to be surethat all diodes are directing their output currents in the same direction. Doublers,like power supplies, produce a dc voltage, which is eliminated in the case of thedoubler by using a dc-blocking capacitor. Power supplies also produce sec-ond-harmonic outputs, which are suppressed by the use of choke inductors andbypass capacitors. Figure 12.2 shows the schematic diagram and waveforms of atypical diode doubler, which makes use of a pair of diodes. Although it is possible tobuild a frequency doubler with a single diode, the use of a pair of diodes produces ahalf-wave-rectified output waveform, which is particularly rich in second-harmonicenergy. Such a doubler is capable of conversion loss on the order of 8 or 9 dB andfundamental and third-harmonic suppression of approximately 30 dB. The simu-lated performance (using SiGe technology) of this doubler is shown in Figure 12.3.The doubler’s conversion loss is on the order of 9.0 dB, and its fundamental andthird-harmonic suppression is extremely high due to the idealized nature of the cir-cuit. A doubler fabricated in InGaP/GaAs technology would require higher inputpower to achieve the same level of performance because of the relatively high Vbe

(1.4V) associated with this technology.

231

A second doubler circuit, which is fully differential, is shown in Figure 12.4. Theadvantage of this circuit is that it can be used in applications where a fully differen-tial architecture is needed to match the differential nature of the surrounding com-ponents. A second advantage of this doubler is that its circuit uses four diodesinstead of the two diodes used in the previous doubler. This means a four-diodedoubler is capable of working to higher power inputs and power outputs. The simu-lated performance for the fully differential doubler is shown in Figure 12.5. Noticethat the waveforms are nearly ideal half-wave-rectified sine waves, which are perfectfor frequency doubling. The conversion loss of the doubler is 10.0 dB with +15 dBminput. The diodes used in the simulations are quite small (a single unit cell device).The series resistance of these diodes is quite high, increasing conversion loss. Per-

232 Frequency Multiplier Design

Figure 12.1 A graph of the IV characteristics of an InGaP/GaAs HBT transistor being operated as adiode. The transistor’s base is connected to its collector, making use of the device’s base-to-emitterjunction as a diode.

Figure 12.2 The schematic diagram and waveform diagram of a two-diode differen-tial-input-to-single-ended-output frequency doubler.

haps larger diodes would improve the performance of these doublers; however,their frequency response would be limited by the parasitic elements associated withtheir size.

12.2 Frequency Triplers

The idealized schematic diagram of a diode frequency tripler is shown inFigure 12.6. Frequency triplers use two identical diodes connected in parallel, butarranged “head to tail,” across a transmission line. Each diode will clip the wave-form of the input signal on alternating half-cycles: one diode clips the waveform inthe positive direction, and the other diode clips the waveform in the negative direc-tion. This clipping action produces an output waveform that approaches a symmet-ric square-wave centered about zero, as is shown in Figure 12.6. Because the input

12.2 Frequency Triplers 233

Figure 12.3 The simulated output power as a function of power input level and output voltagewaveform (for a number of power input levels) of the two-diode differential-input-to-single-ended-output frequency doubler. This doubler uses SiGe technology.

Figure 12.4 A schematic diagram of a four-diode (SiGe technology), fully differential doubler.

signal flows along the same transmission line as the output signal, this fre-quency-tripler circuit has no natural suppression of fundamental power at its out-put. To suppress the fundamental signal, it will be necessary to place a high-passfilter between the tripler’s output and its load. A simulation of the tripler circuit(using SiGe technology) is shown in Figure 12.7. The tripler’s conversion loss is 20dB at a power input of +15 dBm. Notice how the waveform more nearly approachesa symmetric square-wave as the power input level is increased. At high input levels,clipping of both the positive-going and negative-going peaks is very pronounced.However, even with the presence of pronounced symmetric clipping, the conversionloss of the diode tripler is about 20 dB. This high conversion loss, coupled withthe lack of fundamental suppression, does not add up to a particularly high-performance circuit topology. This situation can be improved significantly with theuse of buffer amplifiers and high-pass filters. However, to drive this tripler to its full

234 Frequency Multiplier Design

Figure 12.5 The simulated output power as a function of power input level and output voltagewaveform (for a number of power input levels) of the four-diode, fully differential frequencydoubler.

Figure 12.6 The schematic diagram and waveform diagram of a two-diode (SiGe technology),single-ended, input-and-output frequency tripler.

output power will require at least +15 dBm of input signal, which means a fairlyhigh amount of current consumption will be required in the amplifier that drives thetripler. For this reason alone, more efficient ways of translating signals from lowfrequencies to high frequencies need to be considered.

12.3 Frequency Translators

In order to find ways of converting low frequencies to high frequencies with highconversion efficiency (higher than is currently available with diode-type multipliercircuits), we need to consider circuits using Gilbert cell mixers as frequency transla-tors. Of course, any upconverting mixer can be thought of as a frequency translator.However, upconverters require an LO signal, whose availability is not always feasi-ble for all applications. As an alternative, a Gilbert cell mixer can be operated as afrequency multiplier by inputting identical signals to both its input and LO ports.Since it is a second-order nonlinearity that controls the mixing function, it is possi-ble to write an equation for the multiplying mixer’s output in the case of two identi-cal input frequencies based on (11.7).

K2(V1V2/2)[cos( 1 – 1)t + cos( 1 + 1)t] = K2(V1V2/2) (1 + cos2 1t) (12.1)

Equation (12.1) states that a doubler’s output for two identical inputs signalswill reduce down to a dc term plus an ac term at the second harmonic of the inputsignals.

12.3 Frequency Translators 235

Figure 12.7 The simulated output power and output voltage waveform (for a number of powerinput levels) of the two-diode, all-single-ended frequency tripler.

A block diagram of such a self-mixing doubler is shown in Figure 12.8. Forinstance, if the same signal, F0, is applied to both the input port and the LO port of amixer (by hardwiring these ports together), the input signal at F0 mixes with itself toproduce an output at the sum frequency, which is

F0 + F0 = 2F0 (12.2)

This process is not quite as straightforward as it sounds because many N × Mspur frequencies [2] produced within the mixer will add up or subtract at 2F0. Thismeans the mixer’s doubled output is derived from many sources, as the simulationsin Figure 12.9 show. Some of these mixing products phase with one another to pro-duce wave interference effects, creating a lot of uncertainty as to what will be theultimate conversion loss. Figure 12.10 shows the performance of a Gilbert cell

236 Frequency Multiplier Design

Figure 12.8 The block diagram of a Gilbert cell frequency doubler or frequency tripler(InGaP/GaAs technology). In the case of the doubler, both the input and the LO ports receiveidentical signals at the input frequency. In the case of the tripler, the LO port receives a signal atthe input frequency, while the input port receives a signal at two times the input frequency, whichis first created by a separate Gilbert cell doubler.

Figure 12.9 The simulated output spectrum, conversion loss, and N × M mixing components forthe Gilbert cell frequency doubler.

doubler in terms of its power-input-versus-power-output curve and its output wave-form. Fundamental and third-harmonic suppression are really excellent. However,the Gilbert cell doubler’s conversion loss is about 4 dB, which, though an improve-ment relative to the diode doubler’s, is not very good in comparison to the conver-sion “gain” of a Gilbert cell operation as a downconverting mixer, which can beover +10 dB.

We now consider a Gilbert cell tripler shown symbolically in Figure 12.11. Tofunction as a tripler, the input port must be driven at F0, and the LO port must bedriven at 2F0 (which is supplied by a separate doubling Gilbert cell mixer). Theseroles can be reversed with very little change in performance. To function, this archi-tecture requires that a first Gilbert cell doubler be available to produce a signal at2F0, which is then applied at the tripler’s I port. Like the Gilbert cell doubler, theGilbert cell tripler produces an output at 3F0 in a variety of ways involving manycombinations of N × M spurs. The net effect is the phasing of all of these 3F0 compo-nents such that the tripler’s conversion gain/loss is quite unpredictable and may be alittle disappointing compared to the mixer’s conversion gain as a downconvertingmixer. In Figure 12.12, we see many of the frequency combinations that can add upto produce an output at 3F0. This situation depends on what mathematical “order”is used during harmonic-balance simulation. Higher order is associated with moreoptions in terms of ways to create the 3F0 signal. The upshot of this process is, again,the creation of an output signal at 3F0 that has significantly reduced conver-sion-gain/-loss performance relative to that of the mixer operating alone as anupconverter or a downconverter at frequency 3F0.

12.3 Frequency Translators 237

Figure 12.10 The simulated output spectrum, conversion loss, and N × M mixing componentsfor a Gilbert cell frequency doubler.

Of course, when it is possible to introduce an LO signal into the system’s archi-tecture, very efficient up- and downconverters may be straightforwardly con-structed using Gilbert cell mixers. Since mixers obey strict rules about input andoutput frequencies, the stability and accuracy of the LO signal will have a profoundeffect on the stability and accuracy of the output signal. For this reason, it is notalways feasible to use the frequency-translation approach (i.e., the LO’s frequencystability and phase noise may not be sufficiently pure). In these cases frequency mul-tiplication is the preferred technique. However, if the frequency-translationapproach is used, the architecture must include filters to remove the most objection-able spurs from the mixer’s output. If the application is a narrowband type, the filterfunction is most easily satisfied by using a member of the band-pass filter family. Ifthe application is a wide-bandwidth type, the designer must make some hard choicesin terms of what kind of filter lineup will best serve the goal of removing all spurious

238 Frequency Multiplier Design

Figure 12.11 A symbolic drawing of a Gilbert cell frequency tripler showing all port functions interms of input/output frequencies.

Figure 12.12 The simulated output spectrum, N × M mixer component frequencies, and conver-sion gain of a Gilbert cell frequency tripler.

signals and letting only the desired harmonic or translated signal appear at the out-put.

References

[1] Maas, S., Microwave Mixers, Boston: Artech House, 1986.[2] Henderson, B., “Reliably Predict Mixer IM Suppression,” Microwaves and RF, Vol. 22,

No. 11, 1983, p. 63.

12.3 Frequency Translators 239

C H A P T E R 1 3

Voltage-Controlled Oscillator Design

Oscillators are the circuits which are used to generate signals at RF frequencies.These signals are used in both transmission and reception applications, most com-monly as local oscillators for either an upconverting mixer or a downconvertingmixer. Because wireless transmission frequencies are carefully regulated by in theUnited States by the Federal Communications Commission (FCC), it is usually nec-essary to find a way to stabilize the frequency of any oscillator used in these applica-tions. Stabilization is usually accomplished by the process of phase locking. In thephase locking of oscillators, the oscillator’s output signal is frequency divided downto a low frequency where it can be compared in phase and frequency to a highly sta-ble crystal oscillator. This comparison is usually done with a phase comparator (akind of analog multiplying mixer, see Chapter 11), which produces an output that isproportional to the phase error between the divided-down oscillator signal and thecrystal reference signal. By providing an electronic tuning control port as part ofthe oscillator’s design (making it a voltage-controlled oscillator, or VCO), the phaseerror between the oscillator and the reference is fed back around the phase-lockedloop to the VCO’s tuning port. Once this loop is closed, the oscillator will run atexactly the reference frequency times the divider ratio. Even if phase errors exist inthe loop, as long as the loop is locked, the VCO’s frequency will be locked to thecrystal reference oscillator’s frequency times the divider ratio, insuring a perfectlyfrequency-stable source of RF signal.

In order to facilitate phase locking, it is necessary that any oscillator used withinthe phase-locked loop have a voltage-tunable port as part of its design. In LC reso-nator oscillators, this is usually accomplished by introducing a circuit into the oscil-lator’s topology that will change either the total L or the total C of the oscillator’sLC resonator. Most commonly, it is C that is tuned using a tuning element called avaractor diode. Our discussion of VCOs starts with a discussion of varactor diodessince they are the most commonly used tuning elements in RF VCO circuits.

Following a discussion of varactor diodes, the chapter goes into a discussionof the general aspects of the conditions for oscillation. Types of feedback circuits arediscussed next, as it is the introduction of feedback into transistor circuits that givesrise to negative resistance, which is a necessary ingredient in all oscillators. Next, adiscussion of phase noise covers the physical causes of phase noise, plus calculationsof phase noise in both the 1/f and thermal phase-noise regions of the oscillator’sspectrum.

A type of frequency control called magnetically tunable quantum spinpresession is discussed as an alternative to varactor tuning in VCOs. This type ofoscillator uses a material called yittrium iron garnet (YIG) to achieve a wide-tuning

241

range (with a dc magnetic field). YIG’s high-Q RF resonance offers the designer anunbeatable combination of wide tuning and low phase noise. Although YIG-tunedoscillator cannot be fully integrated at present, they offer many of the characteristicsthat are needed in the cognitive radio systems of the near future (see Chapter 2).

The conclusion of the chapter is devoted to the design of a varactor VCO for an802.11a (see Chapter 2) application in the 5–7 GHz band. This oscillator design isworked out as both single-ended and differential versions. These VCOs areintended for fully integrated applications with Gilbert cell mixers and modulators(see Chapter 11).

13.1 Varactor Diode Basics

Varactor diodes are voltage-controllable, variable capacitor elements used to con-trol the frequency of VCOs [1]. Varactors are also used to control the frequency ofmany other types of devices, including tunable low-pass, high-pass, and band-passfilters. Figure 13.1 shows the structure of a varactor diode. Varactors are con-structed in both GaAs and silicon semiconductor materials. In cross section, thesediodes often consist of a substrate (usually N+ type material), an active layer ofN-type material, and a thin P+ layer, followed by an ohmic contact. The active layeris contained in a narrow portion of the diode called a mesa, whose purpose is to pro-vide diode-area control by selective etching. The fully integrated varactor diodesused in the SiGe BiCMOS fabrication technology may take on a variety of structuralforms (see Chapter 15). Figure 13.2 shows the doping profile of an abrupt-junctionvaractor diode. The heavily doped P region is closest to the top of the diode. The

242 Voltage-Controlled Oscillator Design

Figure 13.1 The structure of a varactor diode showing doping regions, depletion layer, and anequivalent circuit associated with each region.

doping level changes abruptly at the junction to a region of flat N-type dopant, thenagain changes abruptly to the flat N+ doping in the diode’s substrate.

Figure 13.3 shows the internal electric field and space-charge density within thediode. A varactor diode will support current flow when it is biased in its forwarddirection. However, under reverse-biasing conditions, a region of space charge,called a depletion region, forms within the N region of the diode. The width of thisdepletion region increases with increasing reverse bias until it extends across theentire N region. This depletion region is positively charged and is matched by anequal amount of negative charge (electrons) in the P region. As the reverse-bias volt-age increases, these charge layers move apart, causing an effect similar to what hap-pens as metal plates move apart in a parallel plate capacitor. As more charges aredepleted, by increasing the voltage, the capacitance of the diode decreases accordingto the relationship

13.1 Varactor Diode Basics 243

Figure 13.2 The doping profile of an abrupt-junction varactor diode.

Figure 13.3 The electric field behavior inside and outside of the depletion layer in a varactordiode.

C = A/D (13.1)

where

is the semiconductor’s dielectric constant.D is the nominal separation between charges.A is the effective area of the varactor’s junction.

At low reverse voltage, much of the N region is undepleted. This undepleted,N-doped material determines the series resistance of the diode. As the reverse volt-age increases, the depletion region extends over a greater portion of the N region,decreasing the diode’s series resistance. Series resistance is the chief cause of electri-cal loss in varactor diodes.

The relationships for the capacitance and resistance of an abrupt-junctionvaractor diode are

C(V) = A[ qn/2( – V)]1/2 (13.2)

C(0) = A[ qn/2 ]1/2 (13.3)

Rs(V) = (l – w)/qn A (13.4)

Rs(0) = (l – √2 /qn)/qn A (13.5)

W = [2 ( – V)/qn]1/2 (13.6)

W(0) = [2 /qn]1/2 (13.7)

where

A = the junction area.= the semiconductor’s dielectric constant.

n = the active region doping.V = the bias voltage.

= the barrier potential.q = the electronic charge.l = the active region length.D = the depletion layer width.

= the semiconductor mobility in the active region.C(V) = the varactor capacitance.Rs(V) = the varactor series resistance.W = depletion region width

An abrupt-junction varactor diode has a uniform doping profile that extendsacross the device’s active region. The doping profile of a hyperabrupt-junctionvaractor diode is tailored so that its capacitance change is more rapid with bias volt-age change than capacitance change in abrupt-junction diodes. The doping profileof a hyperabrupt-junction varactor diode is shown in Figure 13.4. Figure 13.5 shows

244 Voltage-Controlled Oscillator Design

a comparison between the capacitance of a hyperabrupt-junction diode and that ofan abrupt-junction diode. Notice how the hyperabrupt-junction diode’s capaci-tance changes more rapidly than the abrupt-junction diode’s capacitance, at leastover a limited voltage range. This increased frequency-tuning rate with hyperabruptvaractor diodes is useful, especially in low-voltage, battery-powered applications,where it is desirable to have a large change in capacitance for a small change involtage.

The capacitance of any varactor diode (either abrupt or hyperabrupt) may bewritten in terms of the following generalized expression

13.1 Varactor Diode Basics 245

Figure 13.4 The doping profile of a hyperabrupt-junction varactor diode.

Figure 13.5 A comparison of the capacitance change with voltage of an abrupt-junction varactordiode and a hyperabrupt-junction varactor diode.

C(V) = AK[n/(V + )]Γ (13.8)

where

A is the cross-sectional area of the diode.K is a constant.n is the average doping in the diode’s active region.

is the built in potential (0.70V for silicon, and 1.4V for GaAs).Γ is a slope parameter (about 0.50 for an abrupt junction and 1.0 for ahyperabrupt junction).

Figure 13.6 compares the frequency-tuning curve of an abrupt-junction diodewith that of a hyperabrupt-junction diode. A varactor diode’s series resistance ismore difficult than its capacitance to model in a general way. However, mobilityalways plays a key role in determining Rs. High-mobility material, such as GaAs,will have significantly lower Rs than is obtained with silicon. The difference in seriesresistance between silicon and GaAs may be calculated based on their mobility dif-ferences. In general, the resistance of the diode’s undepleted N-doped material is cal-ulated as:

Rs = l/a (13.9)

where

l is the length of the undepleted region.a is the diode’s cross sectional area

= 1/en (13.10)

where ρ is the material’s resistivity.

246 Voltage-Controlled Oscillator Design

Figure 13.6 Comparison of the frequency-tuning ratio for an abrupt-junction varactor diode andhyperabrupt-junction varactor diode.

Combining leads to a final expression for series resistance:

Rs = l/en a (13.11)

Since the mobility of GaAs has roughly a factor-of-four greater mobility thansilicon, we expect that

Rs(Si)/Rs(GaAs) = 4

The lower series resistance of GaAs varactor diodes can offer significantlyreduced loss in many VCO applications because Q is related to varactor loss. Thelower loss (i.e., higher Q) offered by GaAs varactor diodes can translate into a sig-nificant reduction in a VCO’s phase noise, as is discussed below.

The quality factor of any varactor diode is

Q = 1/2 fRsC (13.12)

It is important to ensure that the RF voltage across a varactor diode does notexceed the diode’s forward voltage. If this occurs, current will flow within thediode, even when it is biased at 0V dc, as shown in Figure 13.7. If current flows onvoltage peaks, harmonics will be generated within the varactor diode, which cancause excess oscillator power output at one or more harmonic frequencies. To avoidthis unwanted situation, it is important always to maintain an RF power at thevaractor diode that is less than a maximum safe RF power, which is calculated by

Pvmax = (Vf)2/Z (13.13)

Equation (13.13) tells us that for a Vf of 0.7V (typical for silicon diodes) and Zof 50 ohms, the maximum varactor power is +7 dBm. This power level must serve asan upper bound on how much RF power can be generated within a VCO’s resona-tor. Power levels in excess of this maximum are likely to cause excessive harmonic

13.1 Varactor Diode Basics 247

Figure 13.7 Rectification of an RF signal voltage that swings sufficiently far into the varactordiode’s forward IV characteristics leads to harmonic generation.

power to appear at the VCO’s output, due to the flow of a highly nonlinear currentwaveform within the varactor diode.

The capacitance change of a varactor diode as a function of temperature may beused as a way of calculating the degree to which a VCO’s frequency will drift withtemperature. Equation (13.8) may be simplified to

C(V) = C(0)/(V + )Γ (13.14)

Taking the partial derivative of the varactor’s capacitance with respect to tem-perature leads to

∂C(v)/∂T = –(∂ /∂T)ΓC(0)/(V + )(V + )Γ (13.15)

where

(∂ /∂T) = 2.3 mV/°C for silicon.= 0.7V for silicon.

Assuming the varactor diode plus an inductor are the frequency-determiningelements of the VCO, the value of ∂C(V)/∂T will translate directly into a frequencyshift via the normal resonant frequency relationship: Fres = (1/2 ) (1/LC)1/2

13.2 Negative-Resistance Concepts

Any oscillator is an energy-conversion device that transforms dc power into acpower. Like all energy-conversion devices, oscillators operate at less that 100 per-cent conversion efficiency due to general thermodynamic considerations. To modelan oscillator from a circuit point of view, techniques have been developed that repre-sent the energy-conversion process in terms of circuit elements. This process isclosely related to the concept of feedback [2]. Figure 13.8 shows a general oscillator

248 Voltage-Controlled Oscillator Design

Figure 13.8 Conditions for start oscillation for an amplifier with feedback.

block diagram representing the oscillator as an amplifier plus a positive feedbackloop. Based on well-known feedback concepts, the conditions for oscillation in thecase of this kind of feedback system are that the system’s open-loop gain must begreater than 1.0, and the system’s open-loop phase shift must be equal to N(2 ),where N is an integer. However, a simplification technique has been developed tomake this process expressible in terms of a circuit element concept called negativeresistance [3]. To understand negative resistance, we first refer to the simple circuitsshown in Figure 13.9. Let us initially review the thermodynamics of resistors.Referring to the left-hand circuit in Figure 13.9, the generator develops a voltage V,which causes a current I to flow into the resistor, which dissipates a power I2R.Next, consider the negative resistor on the right side of Figure 13.9. As in the case ofthe previous positive resistor, the generator develops a voltage, V, which isimpressed across this negative resistor (–R). As a direct result of the stimulation ofthe voltage source V, a current I = –V/R flows out of the negative resistor (and intothe voltage generator), which generates a power I2R.

Because all negative-resistance devices have the ability to produce power gain(and power gain), they can cause oscillations. In their most basic form, all oscilla-tors consist of just three component parts: a negative-resistance device, a resonator,and a load [4]. This basic oscillator topology is shown in Figure 13.10. Under theconditions that MAG[–R] is greater than Rload, this oscillator circuit has a net signalgain and will amplify any form of noise that happens to be present (some form ofthermal noise or shot noise is always present in any real circuit). This noise will be

13.2 Negative-Resistance Concepts 249

Figure 13.9 A symbolic diagram comparing the functions of a positive resistor and a negativeresistor. The positive resistor converts electrical energy from the ac voltage source (which is deliv-ered into the positive resistor) into thermal energy (dissipated power). However, the negative resis-tor, which is delivered energy into the ac voltage source, is generating electrical power.

Figure 13.10 In negative-resistance terminology, the conditions for start oscillation require thatthe magnitude of the negative resistor be greater than the value of the positive load resistor andthat all reactances around the loop add up to a resonance condition of zero, which determines thefrequency of oscillation.

amplified most strongly at the resonant frequency determined by the resonance of Land C. In fact, this noisy signal grows in time with an exponential characteristic,until becoming a sine wave at a frequency Fr, where Fr is the resonator’s resonant fre-quency. This sine wave is the signal developed by the oscillator, and it will continueto grow without limit until the negative resistance is reduced in magnitude by thenonlinear effects that occur in the active device(s).

When the magnitude of the negative resistance and the positive resistance asso-ciated with the load are just equal in magnitude, the wave amplitude will reach afixed (and unchanging) level, and the oscillator is said to have achieved steady state.This steady-state condition means the ac power generated by the negative resistanceis exactly equal to the ac power dissipated in the load resistance (including the reso-nator’s lossy elements). In all realistic oscillator circuits, the magnitude of –Rchanges value because the semiconductor device (which produces –R) saturates asthe signal level increases. From the point of view of negative resistance, we can gen-eralize by saying the conditions for start oscillation are that the magnitude of thenegative resistance must be greater than the load resistance, and the sum of all reac-tive elements around the loop must be equal to zero. In terms of equations, the con-ditions for start oscillation may be expressed as

MAG[–R] > RL (13.16)

∑ Xi = 0 (13.17)

For a simple LC resonant circuit, (13.17) includes an expression for resonance,which determines a relationship for calculating the oscillator’s frequency.

Fr = (1/2 )(1/LC)1/2 (13.18)

The conditions for steady-state oscillation require that the magnitude of the neg-ative resistance must be exactly equal to the total load resistance at the ultimatesteady-state power level.

[–R(Po)] = RL (13.19)

As in the conditions for start oscillation, the reactive resonance from (13.17)determines the steady-state operating frequency

Fr = (1/2 )(1/LC)1/2 (13.20)

Equation (13.20) fulfills the condition that at steady state, all reactive elementsaround the oscillator’s loop must add to zero. In other words, oscillations will beginwhenever the magnitude of the negative resistance of the transistor (with its feed-back) is greater than the positive resistance of the resonator and, simultaneously,when the reactance of the resonator is equal in magnitude and opposite in sign rela-tive to the reactance of the transistor (with its feedback). An oscillator’s steady-statepower output is reached when the negative resistance of the transistor (with feed-back) has been reduced by electronic saturation effects to a value exactly equal inmagnitude, and opposite in sign, to the resistance of the resonator plus the load. Sat-

250 Voltage-Controlled Oscillator Design

uration effects naturally reduce the negative resistance of the transistor as the powerlevel increases. Figure 13.11 shows what could be a typical path taken by the nega-tive resistance as saturation leads to steady-state oscillators. Simulation tools arehelpful in determining the conditions of oscillation for many different kinds of realoscillator circuits.

Today, most IC VCOs use either InGaP/GaAs HBT or SiGe HBT technology (orRFCMOS, if phase noise is less critical) for their active devices [5, 6]. The transistoris transformed into a negative resistance when feedback, in some form, is connectedto its terminals. From a power and energy thermodynamic viewpoint, dc power isapplied to the transistor in the form of bias voltages and bias currents. The biasedtransistor develops gain over a range of useful frequencies. When feedback isapplied to the transistor’s terminals, negative resistance is developed. A resonator isconnected to the transistor’s negative-resistance terminals and serves as a load resis-tance (with reactive elements) for the oscillator. If the conditions for oscillation aremet, oscillations start at the resonator’s frequency, and ac power is delivered intothe load. Conversion efficiency describes the ratio between the ac power deliveredto the load to the dc bias power. Figure 13.12 diagrams the functional parts of atransistor oscillator. As shown in Figure 13.12, if a high Q resonator is a part of theoscillator’s loop, the frequency of the oscillation will be almost entirely determinedby the high Q resonator’s frequency.

13.2 Negative-Resistance Concepts 251

Figure 13.11 Although the magnitude of the negative resistance is greater than the load resis-tance at start oscillation, as the oscillations build up, the negative resistance decreases due to satu-ration effects in within the transistor. This process continues until a steady-state level of oscillationis reach at the point of signal amplitude where the magnitude of the negative resistor exactlyequals the value of the load resistor.

Figure 13.12 If a high-Q resonant circuit is connected between the negative-resistance deviceand the load, the frequency of oscillation will be determined almost entirely by the resonant fre-quency of the resonant circuit.

13.3 Types of Resonators

In the case of IC VCOs, only the varactor diode plus spiral inductor resonator isused for determining frequency. It is this combination of circuit elements that makeselectronic tuning possible. A varactor diode and a spiral inductor can be connectedeither in a series resonance configuration or in a parallel resonance configuration.The choice of a parallel or series resonant circuit depends on the equivalent circuit ofthe negative resistance associated with the transistor with feedback. The following isa useful rule of thumb: If the transistor plus feedback circuit takes the form of areactance in shunt with a negative resistance, then a parallel resonant circuit shouldbe used. If the transistor plus feedback circuit takes the form of a reactance inseries with a negative resistance, then a series resonant circuit should be used. Sincethis is not a hard-and-fast rule, it would be wise to evaluate both possibilities insimulation.

13.4 Feedback Circuit Topologies for Producing Negative Resistance

Transistors are three-terminal devices, and there are many ways to apply feedbackbetween any two of the transistor’s terminals, causing a negative resistance toappear at its third terminal. Two popular ways of applying feedback to bipolar tran-sistors are the common-base, inductive-feedback, negative-resistance oscillator cir-cuit shown in Figure 13.13 and the Colpitts oscillator circuit shown in Figures 13.14and 13.15 [7]. The common-base inductive negative resistance circuit has the advan-tage of simplicity, but its negative resistance is band limited at both low and high fre-quency extremes. The Colpitts oscillator circuit is less robust at high frequencies buthas negative resistance over a very broad frequency range. Both techniques are usedextensively in RFICs. In general, all feedback/negative-resistance oscillator circuitsmay be represented by the block diagram shown in Figure 13.16. The advantage ofcombining the resonator with the feedback circuit is that if simulations indicate thepresence of any negative resistance, then start oscillations are assured.

13.4.1 Negative-Resistance Oscillator Circuits

A simple, but highly effective, oscillator circuit is the common-base circuit withseries inductive feedback (see Figure 13.13). The circuit in Figure 13.13 ignores bias-ing elements and simply contains a common-base-connected bipolar transistor withan inductor L connected between the transistor’s base and ground. A load resistor

252 Voltage-Controlled Oscillator Design

Figure 13.13 A simplified circuit schematic diagram (no bias circuit elements are included) of anegative-resistance oscillator circuit making use of an inductive feedback element connectedbetween the transistor’s base and ground. The resonator is connected between the transistor’semitter and ground.

RL is connected between the transistor’s collector and ground. By placing a resona-tor at the transistor’s source terminals, this circuit can start oscillating anywhere

13.4 Feedback Circuit Topologies for Producing Negative Resistance 253

Figure 13.14 A simplified circuit schematic diagram (no bias circuit elements are included) of acommon-collector Colpitts oscillator circuit making use of capacitive feedback connected betweenthe transistor’s base and emitter (and also from the emitter to ground). The oscillator’s inductiveresonator is connected between the transistor’s base and ground.

Figure 13.15 A simplified circuit schematic diagram (no bias circuit elements are included) of acommon-base Colpitts oscillator circuit making use of capacitive feedback connected between thetransistor’s base and emitter (and also from the emitter to ground). The oscillator’s inductive reso-nator is connected between the transistor’s collector and ground.

Figure 13.16 For purposes of simulation, the real and reactive components of the resonator’s cir-cuit are connected to the transistor plus its feedback elements and its load. This combination ofnegative-resistance elements and power-dissipating elements in the resonator and the load allowsan accurate prediction of start-oscillation conditions based on the requirement that the real part ofthe impedance associated with S11 be net negative and the imaginary part of this impedance benet zero at the frequency of oscillation.

over a wide range of frequencies, limited only by the value of the inductor L and oneof the transistor’s internal parasitic capacitances (Cbc). Insight into the oscillator’soperation may be gained by representing the transistor as a current-controlledcurrent source (CCCS) (of a value – Ib) with an internal parasitic capacitor Cbc

connected between its base and its collector terminals, the equivalent circuit of thenegative-resistance oscillator may be redrawn in terms of a current source and alumped-element circuit.

If a resonator is connected between the transistor’s emitter terminal and ground,oscillations will start if a strong negative resistance is present at the transistor’s emit-ter terminals. This negative resistance may be evaluated at the transistor’s emitterterminal. By connecting a voltage source, Vs, between the transistor’s emitter andground, the current into the oscillator circuit, Is, may be determined. The imped-ance, Zin, at the emitter terminals may then be calculated as

Zin = Vs/Is (13.21)

The oscillator’s negative resistance may be determined by expressing Zin as thesum of its real and imaginary parts:

Zin = Rin + jXin (13.22)

Start oscillator conditions will be fulfilled at all frequencies for which Rin has anegative value. Two important limiting cases for negative-resistance oscillators maybe immediately identified:

1. For Rb < L, at low frequencies the negative resistance will disappear forfrequencies where the inductor’s reactance is lower than some critical value(i.e., the frequency where the inductor begins shorting out the input voltagesource).

L < X1 (13.23)

2. At high frequencies, the circuit’s negative resistance will disappear atfrequencies where the reactance of the device parasitic capacitor Cbc is lessthan some critical value (because Cbc shorts out the transistor’scurrent-controlled current source).

1/ Cbc < X2 (13.24)

where X1 and X2 are numerically low values (in the 1 ohm–10 ohm range).Next, let us compare the simulated negative resistance of the negative-resistance

oscillator circuit of a transistor that is represented in the simulator schematic as aGummel Poon model, with the same circuit using the transistor modeled as acurrent-controlled current source and a parasitic capacitance, Cbc. The schematic ofa fully biased, negative-resistance oscillator using a Gummel Poon model for thetransistor is shown in Figure 13.17. Figure 13.18 show the simulated negative resis-tance of this circuit from 2.8 to 8.7 GHz with the feedback inductance set to 5 nH.Notice that most of the impedance locus is outside of the standard Smith chart (i.e.,MAG(S11) > 1.0). Impedances that lie outside of the MAG(S11) = 1.0 contain nega-tive resistance and can start oscillators at the frequency of the circuit’s reactive reso-

254 Voltage-Controlled Oscillator Design

nance. As can be seen in Figure 13.18, the circuit’s negative resistance disappears atfrequencies below 2.8 GHz and above 8.7 GHz, which is consistent with a negativeresistance that is expected to disappear below a first critical frequency and above asecond critical frequency. The maximum value of negative resistance is encounteredat mid-band and is equal to about –45 ohms. In the region of negative resistance, theoverall impedance is always inductive, which means that the oscillator’s resonatormay simply be a capacitor. A VCO may be naturally designed using a nega-tive-resistance circuit simply by making use of a varactor diode as its resonator. Theinductive component of the circuit’s resonator is supplied by the transistor and theseries feedback inductance that is connected between the transistor’s base andground.

Now compare the negative resistance simulated with a Gummel Poon model forthe transistor with the negative resistance obtained with the CCCS-plus-Cbc model

13.4 Feedback Circuit Topologies for Producing Negative Resistance 255

Figure 13.17 A schematic diagram of a common-base, negative-resistance oscillator (includingbiasing elements and values for elements) using a Gummel Poon transistor model and InGaP/GaAsHBT technology.

Figure 13.18 The simulated impedance of the common-base, negative-resistance oscillator at thetransistor’s emitter terminals. This impedance is plotted on an “expanded” Smith chart. Noticethat negative resistance is available with this circuit over a frequency range of 2.8 to 8.7 GHz. Apeak negative resistance of –43 ohms occurs at 5.0 GHz.

for the transistor that is discussed above. Cbc stands alone as the only element in thetransistor’s equivalent circuit (other than the controlled current source itself) that isimportant in determining the circuit’s negative behavior. The model for the nega-tive-resistance oscillator using this equivalent circuit for the transistor is shown inFigure 13.19. The oscillator’s model contains an ideal current source, with a beta of100, the input base resistance set idealistically to 2 ohms, and the current source’s

256 Voltage-Controlled Oscillator Design

Figure 13.19 The common-base, negative-resistance oscillator’s transistor may be modeled as aCCCS plus a parasitic capacitance, Cbc, which is connected between the transistor’s base and col-lector terminals. The oscillator’s 5 nH feedback inductor is connected from the transistor’s base ter-minal to ground. The current source’s beta is set to 100, which is consistent with Gummel Poonmodels. The base resistance is set to a low value (1ohm), and the collector resistance is set to ahigh value (10k).

Figure 13.20 The simulated impedance of the modeled (see Figure 13.19) common-base, nega-tive-resistance oscillator as it appears at its transistor’s emitter terminals. This impedance is plottedon an “expanded” Smith chart. Notice that negative resistance is available over a frequency rangeof 1.7 to 8.1 GHz. A peak negative resistance of –45 ohms is obtained at 6.0 GHz. These simulatedresults are almost identical to the simulations using a Gummel Poon large-signal transistor model,as shown in Figure 13.18. We conclude from this result that common-base, negative-resistanceoscillators make use of two feedback elements: the first is the inductor connect between the tran-sistor’s base and ground, and the second is an internal capacitance feedback element, Cbc, which isconnected internally from the transistor’s base to its collector. Without having both of these ele-ments in the oscillator’s circuit, negative resistance entirely disappears. Other internal feedback ele-ments, such as Cbe and Cce, have almost no effect on negative resistance and may be safely ignoredin this application.

output shunt resistance set to 10,000 ohms. As in the Gummel Poon example, theinductor is set to 5 nH, and the load is set to 50 ohms. The value of Cbc is assumed tobe 0.07 pF (typical for a single-finger transistor) is connected between the base andthe collector terminals. As shown in Figure 13.21, the locus of impedances, Zin, isplotted on an enlarged Smith chart. As in the previous Gummel Poon simulation,the simulated negative resistance of the equivalent circuit model begins at 2.8 GHzand continues up to 8.4 GHz. The maximum value of negative resistance is–43 ohms at 5.9 GHz. These results are almost identical to those obtain by using afully biased Gummel Poon model for the transistor, clearly indicating that a cur-rent-controlled current source plus a parasitic capacitor Cbc is a sufficiently accurateequivalent circuit for analyzing the behavior of negative-resistance oscillators. Sincethe transistor’s Cbc cannot be directly controlled by the designer, it may be neces-sary, especially at low frequencies, to use a larger-area device (which can still bebiased at low current densities to reduce power consumption, as well as the shotnoise and 1/f noise that contribute to phase noise) in order to achieve a requiredvalue of Cbc and insure strong values of negative resistance at the low end of theband of interest.

In the case of the common-base inductive circuit, we understand the feedbackinductance, together with parasitic capacitances in the transistor’s model, workingtogether to form a circuit linkage between the RF current flowing into the load anda feedback “input” voltage applied between the base and the emitter terminals ofthe transistor. The value of this inductance determines the bandwidth of the nega-tive resistance, with high values of inductance associated with operation at low fre-quencies and low values of inductance associated with operation at highfrequencies. Using a simultaor’s optimization function it is possible to optimize thiscircuit to produce negative resistance over at least two octaves in frequency. Thenegative resistance appearing at the emitter-to-ground terminals is an impedanceconsisting of the negative resistor in series with an inductive reactance. In mostcases, the value of this inductive reactance is very nearly equal to 2 F0Lf, where F0 isthe operating frequency and Lf is the feedback inductor, which is connectedbetween the transistor’s base and ground. As a simple electrical model for the active

13.4 Feedback Circuit Topologies for Producing Negative Resistance 257

Figure 13.21 A schematic diagram of a common-base Colpitts oscillator using a Gummel Poontransistor model and InGaP/GaAs HBT technology.

part of this oscillator, the designer may use a negative resistance (created by the tran-sistor plus its feedback) in series with the inductance, which is connected betweenthe transistor’s base and ground. This circuit has significant advantages for VCOdesign because the base inductor can also function as the inductive portion of theVCO’s LC resonator. Of course, a varactor diode functions as the capacitance por-tion of the LC resonator and is completely responsible for electronic tuning. Asshown in Figure 13.13, the varactor diode must be connected between the transis-tor’s emitter terminal and RF ground. Because the varactor diode’s capacitance iselectronically tunable, the VCO’s frequency is controlled by the dc voltage appliedto the varactor. The question that needs to be answered is, what is the bandwidth ofthe negative resistance? The best way to answer this question is to use simulatortools the exact values of the negative resistance as a function of frequency. A VCOcircuit may first be optimized to maximize small-signal negative resistance over thefrequency range of interest and later simulated in large-signal mode (i.e., harmonicbalance) to calculate power output, exact frequency of oscillator at steady state,waveform shape, and phase noise. Loss in the resonator (i.e., the varactor diode’sseries resistance) will work to prevent the oscillations from starting. Therefore, anysuccessful VCO design must have a negative resistance that is significantly greaterthan the varactor diode’s series resistance at all frequencies of operation.

To maximize the robustness of any oscillator, it is important to maximize boththe negative resistance and the bandwidth of the negative resistance. Often,increased negative resistance and enlarged bandwidth can be achieved simulta-neously by adding a reactive output matching network between the transistor’s col-lector and the load. This output matching network may simply be a shunt L and aseries C. Or it could be a series L and a shunt C. The designer should experimentwith several options. The same simple matching networks used within amplifier cir-cuits can also be considered for use in oscillators. The simulator’s optimizer can behelpful for evaluating options. Both the resistance and reactance of the resonatormust be accounted for in the circuit model if this process is to be meaningful. It is notunusual to simulate the forward gain of an oscillator. Such gain is important becauseexcessive loss in the resonator must be made up for by gain if the oscillator’s circuitis to deliver a reasonable level of power output to the load under all conditions. If thegain is low (i.e., high loss exists between the resonator and the load) oscillator powermay not be efficiently transferred from the resonator to the load, even if oscillationsdo start. Some gain, or at the least very little loss, is necessary to ensure that goodpower output is delivered into the load.

13.4.2 The Colpitts Oscillator Circuit

One of the oldest oscillator circuit topologies is called the Colpitts oscillator after itsinventor Edwin H. Colpitts (1872–1949) [8]. The Colpitts circuit remains a veryimportant class of oscillator circuits, and they are used today in a wide variety ofRFIC applications. Figure 13.15 shows the schematic diagram of a common-baseColpitts oscillator (a common-collector version of the Colpitts oscillator is shown inFigure 13.14). The Colpitts circuit consists of a transistor Q1, a load resistor R, twocapacitors (C1 and C2), and an inductor L.

258 Voltage-Controlled Oscillator Design

As shown in Figure 13.21, a fully biased Colpitts oscillator circuit may beconfigured to allow the simulation of its input impedance, Zin, in order to test for astrong region of negative resistance over a band of frequencies. This reconfigurationinvolves the removal of the inductor, L, from the circuit and inserting a test portwhere the inductor had been connected. The reason for this change is the recogni-tion that the inductor L represents the resonating element in a Colpitts oscillator cir-cuit, and in order to produce oscillators, the rest of the oscillator’s circuit mustpresent a negative resistance (that is, the real part of Zin must be negative) at theinductor’s terminals. For this purpose, we may follow the same procedure that wasapplied above to the negative-resistance oscillator. The schematic diagram for afully biased common-base Colpitts oscillator using an InGaP/GaAs HBT GummelPoon transistor model is shown in Figure 13.21. The equivalent schematic for itscommon-collector version is shown in Figure 13.22. The values of C1, C2, and L arechosen from experience to provide a negative resistance in the 3–6 GHz band offrequencies. The load resistor is lightly coupled to the oscillator circuit with asmall value coupling capacitor. The simulation of Zin for this circuit is shownin Figure 13.23, and the common-collector circuit simulation is shown inFigure 13.24. The circuit’s maximum negative resistance is –33.5 ohms (overall Zin

is capacitive, which means the oscillator will resonate when the inductor L is recon-nected to the circuit) and occurs at a frequency of 2.4 GHz. The common-collectorversion of the Colpitts oscillator circuit has nearly identical negative-resistance per-formance to the common-base version. The transistor Q1 chosen for this oscillatoris a ten-finger transistor. This larger transistor performs better that a smaller-sizetransistor because its Cbc is large, providing increased internal base-to-collectorfeedback, which is necessary for producing strong negative resistance with this classof oscillators.

We next replace the transistor’s Gummel Poon simulator model with a cur-rent-controlled current source plus the parasitic capacitance, Ccb, in order to test theusefulness of this simple transistor equivalent circuit in Colpitts oscillator circuit

13.4 Feedback Circuit Topologies for Producing Negative Resistance 259

Figure 13.22 A schematic diagram of a common-collector Colpitts oscillator using a GummelPoon transistor model and InGaP/GaAs HBT technology.

simulations. Because we are dealing with a larger-size transistor (by a factor of ten)than in the case of the negative-resistance oscillator, the value of Cbc in the devicemodel will increase by a factor of ten to about 1.0 pF. The circuit schematic for a

260 Voltage-Controlled Oscillator Design

Figure 13.23 The simulated impedance of the common-base Colpitts oscillator at its resonatorterminals. This impedance is plotted on an “expanded” Smith chart. Notice that negative resis-tance is available over a frequency range of 1.0 to 10.0 GHz. A peak negative resistance of –33Ωoccurs at 2.4 GHz.

Figure 13.24 The simulated impedance of the common-collector Colpitts oscillator at its resona-tor terminals. This impedance is plotted on an “expanded” Smith chart. Notice that negative resis-tance is available over a frequency range of 1.0 to 10.0 GHz. A peak negative resistance of –41Ω isobtained at 2.4 GHz. This result is almost identical to the simulated impedance of a common-baseColpitts oscillator shown in Figure 13.23.

Colpitts oscillator (common collector) with the simplified device model is shown inFigure 13.25. The simulated values of Zin over a band of frequencies is shown inFigure 13.26. The peak negative resistance is –17 ohms, which occurs at 15 GHz (asin the case of the Gummel Poon device model, Zin is capacitive). However, the valueof Zin at increasingly higher frequencies agrees less well with that predicted using theGummel Poon model. This result indicates that the simple CCCS-plus-Cbc model isnot sufficiently accurate to predict the behavior of a Colpitts oscillator, and realdesign exercises will require the use of either Gummel Poon or VBIC device models.

It is important to note that even if the device is made large to achieve strongnegative resistance over a desired band of frequencies, the dc current should be keptlow simply by adjusting the base-biasing circuit. By keeping the base current and thecollector current low, the shot noise and 1/f noise (which is also current driven) con-tribution to the oscillator’s phase noise will be minimized.

13.5 Frequency-Temperature Stability

The stability of an oscillator’s frequency over a range of temperatures is an impor-tant issue in many applications. Temperature stability of the resonator is controlledby factors such as differential thermal expansion of the materials used to constructthe oscillator and the temperature-capacitance drift of the varactor diode itself.Varactor diode capacitance drifts considerably with temperature (see Section 13.1),so some means must be provided to prevent excessive temperature-frequency driftin varactor-tuned VCOs. The most common method involves the use of aphase-locked loop to hold the VCO’s frequency constant, as determined by anexternal high-stability frequency standard. Often, this standard operates at a muchlower frequency. The VCO’s frequency must be divided down so that it can be com-pared with the reference signal under closed-loop conditions. The resulting overallfrequency stability is determined by the reference oscillator and not by the VCO as

13.5 Frequency-Temperature Stability 261

Figure 13.25 Modeling the common-collector Colpitts oscillator’s transistor as a CCCS with aparasitic capacitance Cbc connected between its base and collector terminals. The current source’sbeta is set to a value of 100, which is consistent with Gummel Poon models. The base resistance isset to a low value (20 ohms), and the device’s collector resistance is set to a high value (10k).

long as the VCO has sufficient electronic tuning (plus a good safety margin) to allowthe phase-locked loop to “hold” the VCO’s frequency constant relative to the refer-ence signal over the full required range of temperatures. The designer needs to makesure that a VCO design has ample electronic tuning so that the phase locked loop isnot required to tune the oscillator into regions of low power or high phase noise attemperature extremes. Some basic trade-offs must be observed. For a particularvaractor diode with a given tuning-voltage range, the only way to increase theamount of electronic tuning is to decrease the resonator’s Q. This can be done bydecreasing the Q of the resonator’s inductance or by coupling the varactor diodemore tightly to the inductor. However, when Q is reduced to increase the VCO’selectronic tuning range, the net effect is to cause an increase in phase noise sincephase noise depends on the inverse square of the resonator’s Q. However, in the caseof YIG-tuned oscillators (see Section 13.8), the oscillator’s resonator is tuned by anexternal magnetic field (generated by either a permanent magnet or by an electro-magnet) acting on specialized magnetic properties of the YIG material (quantummechanical spin precession), and in this case, no such trade-off exists between theresonator’s Q and the oscillator’s electronic tuning range. However, as is the casewith all magnetically tunable oscillators, some amount of tuning power is required,in contrast to varactor diodes, which are voltage-tunable devices requiring no tuningcurrent, therefore no tuning power.

262 Voltage-Controlled Oscillator Design

Figure 13.26 The simulated impedance of the modeled common-collector Colpitts oscillator.The frequency of the simulated negative resistance ranges from 5 GHz to over 15 GHz, with avalue of –18 ohms obtained at 15 GHz. This result does not agree with its equivalent GummelPoon model as well as the results obtained with the common-base, negative-resistance oscillator,shown in Figure 13.20. We conclude that there are additional important parasitic elements, whichare accurately captured by the Gummel Poon transistor model, that are not present in the simpli-fied model shown in Figure 13.25.

13.6 Phase Noise

Noise sources within the transistor and varactor diode that form a VCO will modu-late the output signal, producing low-level noise sidebands lying on either side of themain “carrier” signal. These noisy sidebands are called either amplitude modula-tion (AM) noise or phase noise. AM noise results from the noisy amplitude modula-tion of the oscillator by the noise sources. Phase noise results from the noisy phasemodulation of the oscillator by the same noise sources. The spectra for oscillatorphase noise is shown in Figure 13.27. Most systems are capable of cancellingAM noise, but phase noise remains a fundamental limitation on the performance ofmost wireless communications systems.

Three kinds of noise sources are at work in the transistors and varactor diodes.The first is a low-frequency noise source called 1/f noise, which originates in sur-face-trapping states on the semiconductor material from which the devices are fab-ricated (see Chapter 8). The second noise source is called thermal noise. Thermalnoise is a direct result of the thermal agitation of the charge carriers within the elec-tron gas that comprises the current flowing within semiconductor devices. The thirdnoise source is called shot noise, which is a noise source related to the discreteness ofelectronic charge.

First, consider what happens in the case of thermal noise [9]. Thermal noisesources modulate the oscillator’s frequency and phase such that a mean square fre-quency deviation, ∆ 2 is created. This frequency deviation modulates the carrier.

13.6 Phase Noise 263

Figure 13.27 The phase-noise spectrum of any oscillator is divided into three distinct frequencyregions. The lowest of these regions is called the 1/f region and is a result of upconverted 1/f noisegenerated within the transistor. Phase noise in the 1/f region has a slope of 30 dB per decade withoffset frequency. The middle region is called the thermal noise region. Thermal phase noise is adirect result of thermal noise (i.e., kTB) noise effects within the transistor. In bipolar transistors,shot-noise-generated phase noise behaves in much the same way as thermal phase noise. Thermalphase noise has a slope of 20 dB per decade with offset frequency. The frequency where 1/f phasenoise transitions to thermal phase noise is called the 1/f corner frequency. With bipolar transistors,the 1/f corner frequency is in the range of 1 to 100 KHz. At the highest frequencies, phase noisebecomes flat with offset frequency as it enters the background region. Background phase noise is aresult of the noise figure of components external to the oscillator, such as buffer amplifiers.

The value of this mean square frequency deviation may be calculated from theexpression

∆ 2 = 02kTnB/4Qr

2Pout (13.25)

where

0 is the oscillator’s angular center frequency.k is Boltzmann’s constant (1.38 × 10–23 J/K).Tn is the transistor equivalent noise temperature.B is the bandwidth of measurement.Qr is the resonator’s quality factor (the energy stored per cycle divided by theenergy dissipated per cycle).Pout is the oscillator’s power output.∆ 2 is the oscillator’s thermal mean square frequency deviation.

A similar expression to the above equation (13.25) can be derived for the phasenoise associated with shot noise sources. In bipolar devices, shot noise, like thermalnoise, is flat with frequency. but unlike thermal noise, it is proportional to dc cur-rent. Both base and collector currents make independent contributions to shot phasenoise. As in the case of LNAs (see Chapter 8), bipolar VCOs will exhibit their lowestphase noise far from the carriers if their base and collector currents are kept to aminimum. Of course, there is a trade-off between shot noise intensity and the Pout

term in the denominator of (13.25). Some intermediate current will deliver the bestnoise. The mean-squared frequency deviation can be converted into a phase-noisepower-to-carrier power ratio in units of dBc per hertz by using the equation

N/C (dBc) = ∆ 2/ m2 (13.26)

where m is the frequency offset from the carrier (i.e., the modulation frequency).Because of the inverse square dependence of (13.26) on m, the phase-noise

spectrum of any oscillator far from the carrier (i.e., beyond the effect of 1/f noise)decreases at a 20 dB per decade rate.

Thermal noise dominates phase noise far from the carrier. However,upconverted 1/f noise dominates phase noise at frequencies close to the carrier [10].The upconverted, mean-squared frequency deviation of a transistor oscillator isgiven by

∆ 2 = [ o (∂Cd/∂V0)/2QrGr]2Sv0( m)B (13.27)

where

o is the oscillator’s angular center frequency.∂Cd/∂V0 is the active device’s capacitance change with voltage (i.e., the changein emitter base capacitance with Vbe).Qr is the resonator’s quality factor.Gr is the resonator’s equivalent parallel conductance.

264 Voltage-Controlled Oscillator Design

Sv0( m) is the spectrum of the low-frequency noise fluctuations.

m is the offset angular frequency.B is the bandwidth of measurement.

The phase noise, in terms of a noise-to-carrier ratio associated with (13.27), isgiven by applying (13.26) to (13.27).

Since the cause of the low-frequency phase noise is 1/f noise, the spectrumSv0( m) has a 1/f shape in frequency and assumes the form of

Sv0( m)B = N/( m) (13.28)

where

N is a noise strength parameter.is a spectrum shape coefficient (close to 1.0).

The upconverted 1/f phase noise has a 1/( m)3 dependence on m, based on theinverse square term from (13.17) and the inverse frequency dependence of Sv0( m)from (13.28). The total effect is to predict (as shown in Figure 13.27) aphase-noise-to-carrier ratio that falls at a 30 dB per decade rate (i.e., 1/( m)3), in thesame way that the thermal phase noise found far from the carrier falls at a rate of 20dB per decade. Every oscillator has a point in offset frequency ( c) where theclose-in, upconverted 1/f noise exactly equals the thermal noise. This point is calledthe corner frequency, Fc. For offset frequencies less than the corner frequency, thephase-noise spectrum decreases at a 30 dB per decade rate. For offset frequenciesgreater than the corner frequency, the phase-noise spectrum decreases at a 20 dB perdecade rate. A 30 dB per decade region (associated with upconverted 1/f noise) isclearly seen at low offset frequencies, and a 20 dB per decade region (associatedwith thermal noise) is clearly seen at high offset frequencies. All oscillators have anoise spectrum that follows this general shape. Notice that both the expression forthermal phase noise (13.25) and the expression for upconverted 1/f phase noise(13.27) depend inversely on the square of the resonator’s quality factor. This factoris the single most important circuit parameter for controlling phase noise. Qr

must be maximized to ensure low phase noise both close to and far from the car-rier. A problem that develops in the design of VCOs comes about because theamount of electronic tuning range also depends inversely on the square of theresonator’s quality factor. This means everything that is done to reduce phasenoise will also reduce the VCO’s electronic tuning range, and everything that isdone to increase the VCO’s electronic tuning range will also increase its phasenoise. Not much can be done to improve this situation except to pick an activedevice with minimum noise temperature and minimum 1/f noise. Bipolar devicesare always the best choice in this regard because their vertical structure is notinfluenced by the surface-trapping states that cause 1/f noise. The lowest noisebipolar transistors offer excellent phase noise in VCO applications because their1/f corner frequency is so low (about 50 KHz for InGaP/GaAs HBT and 1 KHzfor SiGe.)

13.6 Phase Noise 265

13.7 Quadrature Phase-Shifting Networks

Because nearly all wireless applications rely on I/Q upconverting mixers in transmit-ter architectures and I/Q downconverting mixers in receiver architectures, it is nec-essary to phase-shift the LO signals for these mixers by 90° when applying the LOsignal to the Q mixer’s LO port. If LO frequency division is used in the overall sys-tem architecture, this quadrature phase shift can be accomplished digitally by thedivider circuits. However, if the LO signal is planned to be at the same frequency asthe VCO’s output, it becomes necessary to design a circuit that provides an accurate90° phase shift of one LO output relative to the other. Since the mixer inputs are dif-ferential, in reality it becomes necessary to produce four LO signals, each one sepa-rated by 90° (see Chapter 6). The I mixer LO signals will be at phases of 0° and 180°.The Q mixer LO signals will be at phases of 90° and 270°.

There are three circuit types that can provide the required quadrature phaseshift, as discussed in Chapter 6. These are a polyphase network, a low-pass network,and a high-pass network. The low-pass and high-pass filter networks are identical tothose described in Sections 6.1 and 6.2. As discussed in these sections, a sin-gle-section low-pass filter circuit has exactly –90° phase shift at Fh, and the sin-gle-section high-pass filter circuit has exactly +90° phase shift at Fh. Therefore, eithercircuit will phase-shift the input LO signal by the required 90°, at a single frequency,Fh. With both the low-pass and the high-pass filter circuits, the zero phase-shiftedLO output will simply be the input signal, and the 90° phase-shifted LO signal willbe the filter’s output. If operation over a broadband of frequencies is required, it isbest to consider using the digital divider approach for quadrature phase-shiftingsince passive filtering networks are inherently narrowband. The polyphase circuithas two outputs that are shifted in phase by +/–45°, again at a single frequency.

Because of impedance interactions it may be necessary in the case of thelow-pass and the high-pass filter networks to split the input power with a resistivepower splitter (see Chapter 6).This technique is used to split the two output LOsignals while maintaining a good 50 ohm match at the filter’s inputs. At the filter’soutput, it is assumed the mixer’s LO terminals will provide a good 50 ohm match tothe phase-shifting networks. However, if this is not the case, it may be necessary toload the phase shifter’s output with a shunt resistor to ensure the existence of a good50 ohm match. Achieving a good match is important because the filter’s designrequires a known output impedance to ensure that the performance of the networkis consistent with its design. The filter design (see Chapter 6) was based on a particu-lar value of impedance.

Figure 6.26 provides a block diagram showing a demonstration for convertingsingle-ended phase shifters into differential phase shifters, provided the VCO’soutput is in differential form (see the design example below). It is for this reason thatthe design of a differential VCO becomes important. Without a differential VCOoutput, it would become necessary to provide an on-chip balun to accomplish thesingle-ended-to-differential conversion. If necessary, this can be done by using thecombination of a low-pass filter and a high-pass filter, as shown in Figure 6.24.However, the use of a naturally differential VCO will prevent having to deal withthe design and real estate requirements of an on-chip balun.

266 Voltage-Controlled Oscillator Design

13.8 Ring Oscillators

Traditional YIG-tuned oscillators (YTOs) have made use of a nega-tive-resistance-type circuit and very large magnetic structures to produce micro-wave sources with extremely linear magnetic tuning and excellent phase noise overan electronic tuning range of one to two octaves. In many important ways, YTOsoffer superior performance relative to other types of oscillators, such as VCOs anddielectrically tuned oscillators (DTOs); however, size and weight considerationshave long prevented the adoption of YTOs by many areas of the electronics indus-try. This is especially true of YTOs operating in the Ku band or higher, where thetraditional YTO magnetic structures are very large. Varactor-tuned VCOs are smalland light but lack the wide linear tuning range and low phase noise of YTOs. DTOshave excellent phase noise but are limited to fixed-tuned applications. Also, DTOsremain expensive due to the high cost of the skilled alignment labor required fortheir manufacture.

Recently, a significant advance in the YTO field has been made by R. Parrott atVida Products [11, 12], offering superior performance by making use of a patented(U.S. patent # 5,801,591) highly refined miniature magnetic structure tuning a sin-gle-sphere YIG filter that completes a feedback loop as part of a InGaP/GaAs HBTring oscillator circuit topology of the kind described by A. Hajimiri and T. Lee [13].The magnetic structure is less than one-quarter the size and weight of traditionalYTOs but is capable of tuning the oscillator to 18 GHz and beyond. The ring oscil-lator circuit topology uses a InGaP/GaAs HBT Darlington amplifier circuit (seeChapter 9) providing nearly flat gain from dc to 15 GHz. Ring oscillator circuits usepositive feedback, which can start oscillations over the full operating bandwidth ofthe amplifier, providing the parallel feedback around the amplifier produces anopen-loop gain greater than 0 dB and an open-loop phase of N(2 ), where N is aninteger. As long as these conditions are met, the resulting oscillator can potentiallybe tuned over the entire bandwidth of the amplifier, which, in the case of an HBTDarlington amplifier, could exceed one decade (see Chapter 9).

Traditionally, YTOs use silicon bipolar transistors for applications up to 10GHz and GaAs MESFET transistors above 10 GHz. In both cases, nega-tive-resistance circuits are used. The silicon bipolar circuit makes use of a com-mon-base configuration with an inductive feedback element connecting thetransistor’s base to ground (see Section 13.4.1). The GaAs MESFET circuit uses acommon source configuration with a capacitive feedback element connecting thetransistor’s source to ground. Both types of negative-resistance circuits are limitedat high and low frequencies because of reactance shifts within their inductor andcapacitor feedback elements. Because of these considerations, negative-resistanceoscillators are inherently limited to one to two octaves of bandwidth. In terms ofphase noise, the silicon bipolar circuits are quite good as a direct result of the low 1/fnoise associated with this class of transistor. However, in the case of GaAs MESFETdevices, which are most often used at high frequencies, the close-in phase noise (inthe 1/f3 region) is often poor due to up conversion of the 1/f noise produced by sur-face-trapping states associated with this class of transistor. The result is that tradi-tional YTOs can produce excellent phase noise up to 10 GHz, but at higherfrequencies, their phase noise may be compromised.

13.8 Ring Oscillators 267

We now compare these YTO characteristics with what can be obtained with thering oscillator topology shown in Figure 13.28. The ring oscillator is made up of aInGaP/GaAs HBT Darlington amplifier and a YIG-tuned filter closing a parallelfeedback path around the amplifier. A second, identical Darlington amplifier servesas a buffer amplifier, reducing load-pulling effects and raising the output power. Aslong as the open-loop gain and phase requirements for oscillation are satisfied, thiscircuit can oscillate over the full frequency range of the amplifier. In terms of phasenoise, like their silicon bipolar counterparts, GaAs HBTs are bipolar transistors andare far less subject to 1/f noise than are GaAs MESFETs, which usually exhibitstrong 1/f noise created by surface-trapping states. Therefore, we expect this circuittopology to yield excellent phase noise up to 20 GHz and beyond.

The ring oscillator is composed of a wideband Darlington amplifier plus aYIG-tuned filter. This filter, which is configured as two half-loops offset by 90°, is anatural differential circuit. The filter’s behavior is critical to the overall operation ofthe YTO because it is this magnetically tunability of the filter that selects the fre-quency at which oscillation starts.

In the YIG-tuned ring oscillator, the filter consists of two half–wire loops, onerunning under the YIG sphere and the other running over the top of the sphere. Theclearance between the sphere and the loops is 10 mil. YIG resonance is a direct resultof a quantum mechanical phenomenon called spin precession. Unlike circuit elementresonators, such as those found in varactor-tuned VCOs, YIG resonators, by virtueof their quantum mechanical nature, maintain high Q factors to extremely high fre-quencies. The result is low phase noise over extremely wide tuning bandwidths. Thespin-precession resonant frequency of YIG is set by a z-directed dc magnetic field,Hdc. The RF magnetic field vector, which is in the x-y plane, rotates at right angles tothe dc magnetic field, which is aligned along the z axis. Hrfx and Hrfy are the x- andy-directed components of the rotating RF magnetic field associated with spin preces-sion. Because RF currents flow in opposite directions within the two (top and bot-tom) coupling loops, a natural 180° phase shift occurs between the same-sided filterinputs and outputs. Since the physical plane of the top loop is rotated by 90° relativeto the physical plane of the bottom loop, a natural 90° phase shift occurs betweenthe loops because one of them is always experiencing a peak of the RF magnetic fieldoccurring at 90° relative to the other. Therefore, a total phase shift of 270° is directly

268 Voltage-Controlled Oscillator Design

YIG SPHERE

STUB

BUFFER AMP

OUT

OSCILLATOR AMP

FBLOOP

BLOCKINGCAP

YIG RESONATOR

Figure 13.28 The block diagram of a YIG-tuned ring oscillator using a Darlington amplifier (seeChapter 9) to produce loop gain and an identical Darlington amplifier used as a buffer stage.

associated with the YIG filter. The measured S21 of this YIG filter at F0 = 12 GHz isshown in Figure 13.29. The filter’s 3 dB bandwidth is about 25 MHz. For simula-tion purposes, this YIG filter is modeled as a differential Bessel filter coupled to thesurrounding loop elements by two ideal transformers. The bandwidth of each filteris set to 25 MHz, which implies a Q factor of about 600 at 12 GHz.

Identical wideband Darlington gain block amplifiers are used in the ring loopand as a buffer amplifier. The gain block amplifier makes use of a Darlington topol-ogy and GaAs/InGaP HBT fabrication technology. The amplifier’s two bipolartransistors have emitter dimensions of 2 × 20 µm and 2 × 40 µm, respectively. Thisamplifier, whose overall dimensions are 350 × 500 µm, has nearly flat gain from dcto 15 GHz and almost constant phase shift over frequency. The amplifier’s out-standing performance is due to its small size and freedom from parasitic elements.The amplifier’s measured S-parameters are shown in Figure 13.30.

A model for the Darlington amplifier, including layout parasitic elements, isused to simulate the performance of the ring oscillator. Agreement between themeasured and simulated amplifier performance is excellent. The amplifier’s dc biasconditions are set by design to 5.0V at 50 mA.

The oscillator’s open-loop gain and phase may be analyzed in the followingway: The elements of the open-loop oscillator circuit are connected in a way that theloop is opened for analysis. The open-loop gain and phase of the oscillator may nowbe simulated to determine the conditions necessary for the start of oscillation. If wesimply add up the individual phase contributions around the loop, we get 2 plus90°. However, component interactions and the effect of stub tuning reduce this totalto 360° (i.e., 2π). Simulations of the open-loop gain and phase at 12 GHz are shownin Figure 13.31.

13.8 Ring Oscillators 269

Figure 13.29 The measured S-parameters (S21) of a YIG resonator, showing a bandwidth ofabout 25 MHz at 12 GHz. This measured performance corresponds to a Q of about 500. (Source:Courtesy of Vida Products, Inc.)

Notice that the open-loop gain is greater than 0 dB, and the phase shift is cen-tered at 0° (i.e.,0 × 2 ) and is adjustable with the length of a coplanar wave-guidestub connected to one port of the YIG filter. This transmission-line stub serves as aphase adjustment, providing an easy way to set the center frequency of the desiredband of oscillations. At 12 GHz, the open-loop phase shift may be adjusted by+/–40° with this stub. Adjustment of the stub’s length is the only alignment steprequired during the manufacture of this YTO, leading to low manufacturing costs.The simulated open-loop gain and phase fulfill all of the conditions for start oscilla-tion as stated in Section 13.2. In the physical realization, the circuit elements are

270 Voltage-Controlled Oscillator Design

Figure 13.30 The measured S-parameters of the Darlington loop (and buffer) amplifier.

Figure 13.31 Simulated open-loop gain and open-loop phase of the YIG-tuned ring oscillator asevaluated at 12 GHz. Since there is net gain around the loop and the open-loop phase at is zero,start-oscillation conditions are fulfilled at 12 GHz.

mounted on a ceramic substrate, which has a cutout allowing the YIG sphere to bemounted in the middle of two orthogonal half–coupling loops (one on the top andone on the bottom of the YIG sphere).

A diagram of the YTO’s magnetic structure is shown in Figure 13.32. This min-iature YTO uses a permanent magnet ring and field focuser to define a narrow airgap, typically 100 mil, in which the YIG sphere is located. The permanent magneticdetermines the center of the band operating frequency. The main tuning coil sur-rounding the permanent magnet has 2,200 turns, providing a tuning rate of 25MHz per mA. Tuning current will raise or lower the frequency relative to bandcenter. A shield magnet above the field focuser prevents magnetic flux from flowingin the outer shell. These magnetic shielding techniques greatly reduce the effects ofmechanical vibration and “phase hits” that occur at temperature extremes or undermechanical shock or vibration. The YTO’s overall size (including outer shell) is0.75 in. in diameter and 0.60 in. in height. Its weight is 25g. This structure can easilybe adapted to surface-mounted technology.

By closing the loop, it is possible to simulate the YTO’s power output, wave-form, and phase noise over a range of frequencies. According to Hajimiri and Lee, itis important with ring oscillators to maintain a highly symmetric output waveformin order to keep the phase noise associated with upconverted 1/f noise to a mini-mum. Since the GaAs/InGaP HBT devices generate very little low-frequency 1/fnoise due to their bulk effect structure, the presence of a highly symmetric wave-form will provide double protection against 1/f3 low-frequency phase noise associ-

13.8 Ring Oscillators 271

Tuning coil

Ring magnet

YIG Field focuser

Shield magnet

Figure 13.32 A mechanical cross section of the miniature YIG-tuned ring oscillator. (Source: Cour-tesy of Vida Products, Inc.)

ated with upconverted 1/f noise. Simulations have demonstrated that thisoscillator’s output waveform is nearly sinusoidal over a wide range of operating fre-quencies, fulfilling the Hajimiri, Lee conditions.

The oscillator’s simulated power output is shown in Figure 13.33. Strong oscil-lations are predicted over an octave from 7 to 14 GHz, with power output in accessof +10 dBm. Under closed-loop conditions, the simulated phase noise at 12 GHz,which is shown in Figure 13.34, is less than –125 dBC per hertz at 100 KHz. Thisphase-noise performance represents greater than 10 dB improvement over MESFETYTOs operating at this frequency. Simulations of frequency pulling into a 2:1VSWR load rotating through all phases indicates a +/–10 KHz frequency shift, andsimulated frequency pushing is on the order of 500 KHz/V.

The measured power output as a function of tuning is shown in Figure 13.35.Measured power is about +10 dBm, closely following the simulated power output.Tuning bandwidth can be adjusted inversely with stub length. Measured phase noiseat 12 GHz, given in Figure 13.36, was found to be in close agreement with the simu-lated phase noise. The measured phase noise of this oscillator is a significant stepforward in improving YTO performance at the X and Ku bands.

13.9 Design Example 7: 802.11a (Wi-Fi A) Differential VCO

The following example shows a procedure for designing a differential RFIC VCOsfor wireless communications applications [14–16]. This particular VCO is designedto operate in the 6 GHz range for 802.11a applications. However, a similar proce-dure could be followed for any desired band of operation. For 5V supply operation,

272 Voltage-Controlled Oscillator Design

Figure 13.33 The simulations of the YIG-tuned ring oscillator’s power output, exact center fre-quency, and voltage and current waveforms, when the circuit’s YIG resonator is tuned to 18.0GHz.

the technology of choice is InGaP/GaAs. For 3V supply operation, the technology ofchoice is SiGe.

13.9 Design Example 7: 802.11a (Wi-Fi A) Differential VCO 273

Figure 13.35 The measured power output of a YIG-tuned ring oscillator operating from 7 to 14GHz. The adjustable parameter is the open stub’s length. (Source: Courtesy of Vida Products, Inc.)

Figure 13.34 The simulated phase and amplitude noise for the YIG-tuned ring oscillator operat-ing at 18 GHz. Notice that the phase noise at 10 KHz offset frequency is –103 dBc, which isapproximately 30 dB lower than what can be obtained with the best varactor-tuned VCO operat-ing at this frequency.

The VCO’s top-level schematic diagram is similar to that shown in Figure 13.16.The return side of the varactor resonator is connected to a terminated test port. S11measured at this port will give an indication of the magnitude and frequency rangeof the oscillator’s negative resistance. For this design, 5V operation will be used, sothe technology of choice is GaAs/InGaP HBT. Component blocks on the top-levelschematic contain the transistor-level oscillator schematic diagram and the varactordiode resonator. Both the transistor and the varactor diodes have large-signal mod-els associated with them. Figure 13.37 contains the transistor-level schematic dia-gram of the oscillator circuit, including common-base inductive feedback and all ofthe necessary bias control resistors. Spiral inductors are used for feedback and col-lector bias current injection, and the emitter dc ground return. The three ports of theoscillator block are RF output, varactor resonator, and dc bias. Figure 13.38 con-tains the elements in the varactor resonator component block, including the

274 Voltage-Controlled Oscillator Design

Figure 13.36 A chart comparing the measured and simulated phase noise of a YIG-tuned ringoscillator operating at 12 GHz. (Source: Courtesy of Vida Products, Inc.)

Figure 13.37 The schematic diagram of the transistor-level varactor-tuned VCO circuit using anegative-resistance oscillator circuit topology and InGaP/GaAs HBT technology.

varactor’s model. A layout of this VCO is shown in Figure 13.39. This layout pro-vides for an off-chip varactor diode since these devices are rarely available inInGaP/GaAs foundry processes. However, if the VCO were fabricated in SiGe tech-nology, the varactor diode would be on-chip (see Chapter 5).

Initial simulations are used to determine start-oscillation conditions. The simu-lated S-parameters (S11) at the resonator’s return port (which is electrically equiva-lent to an open-loop condition with a feedback amplifier) are found in Figure 13.40.These parameters are displayed as both magnitude (in decibels) and angle, and alsoas a reflection coefficient plotted on a Smith chart. In the Smith chart presentation,the negative-resistive region, as a function of frequency, is clearly seen as lying out-put side of the normal (magnitude S11 = 1.0 circle) Smith chart. That is, the com-

13.9 Design Example 7: 802.11a (Wi-Fi A) Differential VCO 275

Figure 13.38 The schematic diagram of a varactor resonator, including a blocking capacitor anda bias choke inductor.

Figure 13.39 The layout of the varactor-tuned negative-resistance oscillator.

bined oscillator/resonator circuit will present a net negative resistance as a functionof frequency for all S11 that lie beyond a reflection coefficient of 1.0. Notice that forthe chosen tuning voltage, the resonance in phase shift occurs at 6 GHz, and the neg-ative resistance at that frequency is about –26Ω in magnitude. This is a strong nega-tive resistance, and oscillations will start once the resonator’s return port is attachedto ground. By adjusting the tuning voltage on the top-level schematic (Figure 13.37),the resonant frequency may be varied from 5 to 6 GHz, covering all of the 802.11aband.

Next, the oscillator’s steady-state performance is simulated by using large-signalsimulator analysis. Notice that a component block called “oscport” must be addedto the schematic diagram between the oscillator circuit block and the varactor dioderesonator circuit block for ADS simulations. The purpose of oscport element blockis to allow the simulator (ADS) to sense the frequency and signal levels as oscilla-tions build up. There is some art to properly locating the oscport block in the overallschematic diagram. The best insertion point seems to be at a break in the circuitwhere the resonator connects to the negative-resistance portion of the oscillator, butthere are many other possibilities. In theory, any connection within the oscillator’scircuit should work as an oscport location. However, experience has shown thatsome locations are better than others in terms of successful convergence of the finallarge-signal performance parameters.

Figure 13.41 shows the simulated large-signal performance of the oscillator.Parameters given in Figure 13.41 are the oscillator’s power output at its fundamen-tal frequency and also at several harmonic frequencies. (The oscillator’s spectrum is

276 Voltage-Controlled Oscillator Design

Figure 13.40 The simulated S-parameters of the varactor-tuned VCO are shown, predicting thatstart oscillation will occur at a frequency of 6.0 GHz. The oscillator’s net negative resistance,including losses in the varactor, is –25ohms at 6.0 GHz.

displayed in terms of a harmonic number index.) The fundamental frequency andall harmonics frequencies are also given. The waveform of the output voltage isplotted versus time. There is a little high-voltage clipping of the waveform, which isan indication of how the saturation process is occurring for this oscillator. Noticethat the oscillation frequency has increased (7.3 GHz versus 6 GHz) relative to thesmall-signal plots shown in Figure 13.40. This is a demonstration of howlarge-signal reactive effects can occur as the oscillator’s signal builds up. The oscilla-tor may require frequency retuning to account for these effects.

The oscillator’s phase noise may be simulated with the help of the slightly modi-fied top-level schematic diagram. In Figure 13.42, the simulated phase noise isshown plotted as a function of offset frequency. It is often helpful when plottingphase noise to use a log scale on the x axis, which is the offset (or modulation) fre-quency. By plotting the log of offset frequency, it is possible to display up to six ormore decades in frequency on a single plot. Such a graphical display can be verymeaningful with phase-noise simulations. The universal units of phase noise are dBcper hertz calculated at each offset frequency. The ADS simulator uses two differentalgorithms to calculate phase noise. The first is a frequency-modulation algorithm;the second is a noise-mixing algorithm. Experience indicates that the frequency-modulation algorithm yields results that are closer to actual measured data. Inaddition to phase noise, ADS also calculates the oscillator’s amplitude noise. Thisnoise is of less practical interest because most balanced mixers naturally cancel anyLO amplitude noise. Notice that phase noise (using the frequency-modulation algo-rithm) rolls off at an unchanging 20 dB per decade over at least six decades of offsetfrequency. This is because the Gummel Poon model used for the oscillator’s transis-tor contains only thermal noise and shot noise parameters and no 1/f noise (because

13.9 Design Example 7: 802.11a (Wi-Fi A) Differential VCO 277

Figure 13.41 Simulations of the varactor-tuned VCO’s power output, frequency, and output volt-age waveform. Simulated dc base and collector currents are shown.

the 1/f noise parameters have been set to zero). Had 1/f noise parameters been pres-ent in the Gummel Poon model, at offset frequencies below the 1/f corner frequency,the rate of descent would have become 30 dB per decade.

13.10 Figure of Merit

A metric called the figure of merit (FOM) of an oscillator has been developed toallow designers to calculate a single number that characterizes an oscillator’s phasenoise performance in order to easily compare the relative phase-noise performanceof a number of oscillators [17].

The calculation of FOM relies on the fact that thermal phase noise depends onthe square of the oscillator’s center frequency, F0, and the inverse square of the offsetfrequency of measurement, Fm. Also, phase noise depends inversely on the oscilla-tor’s output power. Taking into account these three natural behaviors, any oscilla-tor’s phase noise can be “normalized” in terms of center frequency, offset frequency,and power output (this item is handled by using the oscillator’s dc power in order toinclude the oscillator’s dc-to-RF conversion efficiency within the final metric).

The final FOM value for a given oscillator characterizes that oscillator’s resona-tor Q, dc-to-RF conversion efficiency, and device noise temperature (noise figure).An equation for FOM is the following

FOM = 20log(F0/Fm) – 10log(Pdc) – [measured phase-noise (at F0, Fm)] (13.29)

278 Voltage-Controlled Oscillator Design

Figure 13.42 The simulated phase noise of the varactor-tuned negative-resistance VCO operatingat an output frequency of 6.9 GHz.

As an example, consider the calculation of the FOM for the VCO shown inFigure 13.42. In the case of this VCO, its phase noise is –55 dBC for Fm = 10 KHz.The oscillator’s dc power is 0.02W(5V × 4 mA), and the VCO’s center frequency is7.0 GHz. In this case, FOM is calculated as

FOM = 20log(7E9/10E3) –10log(0.02) – (–55)

FOM = 117 + 17 + 55 = 189 dBc/Hz

The result of 189 is an excellent FOM for a VCO and indicates that this particu-lar VCO design is highly competitive in terms of phase-noise performance withother types of VCOs.

Since 1/f phase noise is greater than thermal phase noise at all offset frequenciesbelow the corner frequency, it follows that FOM values calculated at low offset fre-quencies will exhibit strong 1/f characteristics, which will negatively affect FOMcompared to FOM predictions calculated for higher offset frequencies (i.e., beyondthe corner frequency). Although the intent of FOM is to calculate a single numberthat characterizes an oscillator’s behavior, in reality, it is necessary either to specifywhich Fm was used in making the calculation or to always ensure that Fm is wellbeyond the corner frequency so that the phase noise being compared is alwayspurely thermal (or shot) in its origin.

13.11 Electronic Tuning and a Differential VCO Topology

It is possible to reconfigure ADS’s harmonic-balance controller in such a way thatsimulation parameters will sweep across the oscillator’s tuning range so that poweroutput and frequency are graphically plotted as a function of tuning voltage. By set-ting the tuning voltage to sweep from 0V to 3V, the simulation can demonstrate (asshown in Figure 13.43) that the oscillator’s frequency is tuned from 5.7 to 6.8 GHz.Also, over this tuning range, the oscillator’s output power varies from –1.5 dBm atthe low end (consistent with the higher varactor loss at lower voltage) to 0.0 dBm atthe high end (consistent with the lower varactor loss at higher voltage). The abilityto sweep varactor voltage is useful for simulating the final performance of a VCOcircuit. This ability to sweep power and frequency as a function of tuning voltageallows the designer to know instantly how much electronic tuning range is avail-able with a given design and how much output power will vary across the VCO’stuning range.

Since most mixers (e.g., Gilbert cell mixers) require a differential LO input, itwould be useful to design a differential VCO [18]. By placing two oscillator transis-tors in this VCO topology we can accomplish this goal in much the same way aswhen two amplifier transistors are placed in parallel within a differential amplifiertopology. A tail transistor is attached to the common emitter connection of the twooscillator transistors to control dc current. The tail transistor is used as a gain con-trol for starting oscillations and for setting the oscillator’s dc current. A schematicdiagram for the entire differential oscillator is shown in Figure 13.44. The base ofeach of the oscillator transistors is connected to a feedback inductor, whose otherend is attached to an RF ground, which is also connected to a dc base-biasing net-

13.11 Electronic Tuning and a Differential VCO Topology 279

work. A back-to-back pair of tuning varactor diodes is connected from the collectorof one transistor to the collector of the second transistor. Where the varactor diodesmeet along the oscillator’s centerline, tuning voltage is applied in such a way that thetotal voltage drop across each diode is equal to the (Vcc – Vtuning). This means thatwhen Vtuning is equal to Vcc, the varactor diode’s voltage is zero (i.e., Vcc – Vcc). How-ever, if Vtuning is equal to zero, the varactor diode voltage is equal to Vcc in the reversedirection because of the direction of diode connection. Also, connected across thepair of varactor diodes is an inductor, which serves as a resonator element (which ishelpful in setting the center frequency) within the differential oscillator. All of the

280 Voltage-Controlled Oscillator Design

Figure 13.43 The simulated sweeped power output and sweeped frequency of the nega-tive-resistance VCO as a function of varactor tuning voltage (from 0.0V to 3.0V). Under these con-ditions, the simulated power output ranges from –1.5 dBm at 0.0V to 0.0 dBm at 3.0V. Thefrequency ranges from 5.8 GHz at 0.0V to 6.9 GHz at 3.0V. This behavior is consistent with thetypical behavior of an abrupt-junction varactor diode, with the expected high capacitance andhigh series resistance at low voltages (corresponding to low frequency and low power) and lowcapacitance and low series resistance at high voltages (corresponding to high frequency and highpower).

Figure 13.44 The schematic diagram of a differential varactor-tuned VCO circuit. This circuit usesSiGe technology.

base-bias circuits are supplied from separate bias supplies. The oscport block is con-nected between one of the transistor’s bases and RF ground (through a 100 pFcapacitor). This choice of oscport block placement is just a guess that worked well,but other placements may work equally well. The simulated performance of thecomplete differential oscillator is shown in Figure 13.45. Notice that the waveformsat the Vout+ and Vout– ports are exactly 180° out of phase, as is expected with any dif-ferential signal. The fundamental power output is –3.8 dBm, and the fundamentaloperating frequency is 8.9 GHz. The dc operating current of this oscillator is low(4 mA). By creating this differential oscillator, we avoid the necessity of including anon-chip balun for converting the single-ended output of a conventional oscillatorinto a differential output for connection to the differential LO port of a Gilbert cellmixer. The one disadvantage of this type of oscillator is the extra chip area that itoccupies. However, the differential form of this VCO is likely to pay for itself interms of avoiding the headaches associated with designing and laying out a broad-band on-chip balun.

References

[1] Sweet, A., MIC and MMIC Amplifier and Oscillator Circuit Design, Norwood, MA:Artech House, 1990.

[2] Razavi, B., RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.

13.11 Electronic Tuning and a Differential VCO Topology 281

Figure 13.45 The simulation of a differential varactor-tuned VCO circuit showing its power out-put, frequency (8.9 GHz), dc current, and voltage waveforms at the oscillator’s two outputs.Inspection of the waveforms demonstrates that the two outputs are exactly 180º out of phase.

[3] Uwano, T., et al., “Design of a Low Phase Noise VCO for an Analog Cellular PortableRadio Application,” Vol. 77 (part 2), No. 3, 1994, pp. 58–65.

[4] Milnes, A., Semiconductor Devices and Integrated Electronics, New York: Van NostrandReinhold, 1980.

[5] Shin, H., et al., “A 1.8V, 6/9-GHz Switchable Dual-Band Quadrature LC VCO in SiGeBiCMOS Technology,” IEEE Radio Frequency Integrated Circuits (RFIC) Symp., Seattle,WA, 2002.

[6] Soyuer, M., et al., “Low-Power Multi-GHz and Multi-Gbps SiGe BiCMOS Circuits,” Proc.IEEE, Vol. 88, No. 10, October 2000, pp. 1572–1582.

[7] Gray, P., et al., Analysis and Design of Analog Integrated Circuits, New York: John Wileyand Sons, 2001.

[8] Lee, T., The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge: Cam-bridge University Press, 1998.

[9] Leeson, D., “A Simple Model of Feedback Oscillator Noise Spectrum,” Proc. IEEE, Vol.54, February 1966, pp. 329–330.

[10] Sweet, A., “A General Analysis of Noise in Gunn Oscillators,” Proc. IEEE, Vol. 60, No. 8,August 1972.

[11] Sweet, A., and Parrott, R., “A Novel Miniature YIG-Tuned Oscillator Achieves OctaveTuning Bandwidth with Ultra Low Phase Noise in X and Ku Bands,” IEEE MicrowaveSymp., San Francisco, CA, June 2006.

[12] Sweet, A., and Parrott, R., “A Miniature YIG-Tuned Oscillator/Frequency Divider AchievesOctave Tuning Bandwidth with Ultra Low Phase Noise in S, C X and Ku Bands,” EuropeanMicrowave Conf., Manchester, UK, September 2006[[AQ: dates?]].

[13] Hajimiri, A., and Lee, T., “A General Theory of Phase Noise in Electrical Oscillators,”IEEE J. Solid State Circuits, Vol. 33, No. 2, 1998, pp. 179–194.

[14] Rael, J., and Abidi, A., “Physical Processes of Phase Noise in Differential LC Oscillators,”Proc. CICC 2000, pp. 569–572.

[15] Lai, P., and Long, S., “A 2.4 GHz SiGe Low Phase Noise VCO Using On-Chip TappedInductor,” IEEE ESSCIC 2003, pp. 505–508.

[16] Zhang, L., “A 37~50 GHz InP HBT VCO IC for OC-768 Fiber Optic CommunicationApplications,” 2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., Seattle, WA,June 2002.

[17] Lai, P., and Long, S., “A 5-0GHz pHEMT Transformer-Coupled VCO,” 2005 IEEE RadioFrequency Integrated Circuits (RFIC) Symp.,” Long Beach, CA, June 2005.

[18] Tiebour, M., “Low-Power Low-Phase Noise Differentially Tuned Quadrature VCO Designin Standard CMOS,” IEEE J. Solid State Circuits, Vol. 36, No.7, July 2001, pp.1018–1024.

282 Voltage-Controlled Oscillator Design

C H A P T E R 1 4

Layout Design Strategies

14.1 Minimum Area

It is an economic fact of life that the product cost of an RFIC chip is directly propor-tional to its area. Therefore, there are strong forces pushing the designer to mini-mize the ultimate layout area of any given design. This is not all bad from anelectrical-performance viewpoint because minimizing chip area often minimizes theperformance-robbing parasitic elements, such as interconnecting metal lines andcapacitor bottom plates. There is no hard-and-fast rule to determine the optimumarea for a given RFIC requirement. There are so many factors influencing this deci-sion that it is more of an art than a science to arrive at a final value. In the end, thesuccessful design addresses a number of trade-offs and balances all of the importantdetermining factors to come up with the simplest possible design that will meet allrequirements. Let us now consider some of the factors that must be considered incoming up with a successful design layout.

14.2 “On-Chip” versus “Off-Chip” Component Decisions

The designer must constantly wrestle with the decision making relative to placing acomponent on-chip or relying on the chip’s ultimate customer to place a key compo-nent “off-chip” on the circuit board and make connections to the packaged chipthrough circuit board traces. The on-chip-versus-off-chip question is never an easyone to address, but it is very necessary. Here are some general guidelines that mayhelp in making these difficult decisions:

1. Capacitors: Capacitors should be placed off-chip when their values makethem physically too large if placed on-chip. The question to be answeredhere is, how large is too large? The best way of approaching this question isto recognize that semiconductor chips are not a good economic way tomanufacture capacitors. If the capacitor in question is large enough tooccupy a substantial fraction of the chip’s area, it is best moved off-chip,where tiny surface-mount capacitors are readily available to extremely highvalues of capacitance. On rule of thumb is never to let the total on-chipcapacitance occupy more that half the chip’s total area. If the “half” rule isapproached, it may be a signal to the designer to consider moving the largestcapacitors off-chip.

2. Inductors: Inductors are always realized on-chip as spiral inductors.Off-chip inductors will be in the form of surface-mounted devices, which

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have considerably lower loss than on-chip spiral inductors and can handlemuch higher currents without compromising reliability. Spiral inductors,like MIM capacitors, can be major chip-area drivers. Therefore, the mainmotives for moving inductors off-chip are to reduce losses, increase currentlimits, and save chip area. All of these reasons are good and need to beconsidered seriously. There is some interaction between the reasons; forinstance, an on-chip spiral inductor that is required to carry high dc currentmust have a trace wide enough to carry this level of dc current safely (seeChapter 4) without compromising reliability. Therefore, the requirementsfor high current will inflate the area of a spiral inductor, providing tworeasons to consider moving this device off-chip. In terms of area, the designershould consider, as in the case of the capacitor, moving one or more of thespiral inductors off-chip if the total area occupied by all spiral inductorsbecomes greater than 50 percent of the total chip area. Again, it is a case ofrecognizing that semiconductors are not the most economically efficient wayof manufacturing inductors. However, in the case of inductors, it may benecessary to place certain key inductors off-chip simply because these devicesmay be located in a critical area of the chip’s circuit requiring extremely lowloss (as in the front-end matching elements of an LNA). Another reason tolocate an inductor off-chip is to take advantage of an off-chip inductor’sability to carry large currents without the need to resort to extremely widemetal traces if the inductor is realized on-chip. One might also use off-chipinductors as very high-Q inductors that may only be available as off-chipdevices. Such high-Q inductors can be frequency-determining components inVCOs, for example. On-chip spiral inductors, which are naturally low Q,may not be capable of achieving the level of Q needed in certainlow-phase-noise VCO applications.

3. Resistors: Most resistors can be realized on-chip, but there are someexceptions. For instance, high-precision resistors are often hard to realizeon-chip. Also, high-value resistors can be hard to realize on-chip, even usingso-called interdigitated techniques. This is particularly true with a foundryprocess that has only a 50 ohms-per-square available TFR resistor option.

4. Specialized components: Certain components are not easily realized on-chipor simply may not exist in an on-chip format. This category includes, but isnot limited to, transformers, baluns, Lange couplers, high-Q filters, varactordiodes, PIN diodes, and transistors from other technologies. While the bestrule to follow is to avoid components like these in your designs, it issometimes impossible not to use such components because of the nature of agiven requirement. Therefore, these specialized off-chip components must bealways be treated on a case-by-case basis.

14.3 Minimizing Parasitics

Minimizing parasitic elements is always a good idea in any design. However, some-times these parasitic elements can be used to advantage as circuit matching elements.Since they are often unavoidable, it is a very good plan to include them in your cir-

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cuit schematic in a way that will do some good. This is not always possible, but thedesigner needs to be aware of the potential and take advantage of any and all oppor-tunities to put unavoidable parasitic elements to good use. An example of putting aparasitic element to good use is in the design of Darlington amplifiers, where themetal line connecting the emitter of the first transistor to the base of the second tran-sistor can be used to peak up the amplifier’s high-frequency gain. This connectionhas to be made anyway, so why not put it to good use.

Unfortunately, many, and perhaps most, parasitic elements will only degradeperformance and should be minimized or, better still, avoided all together. There isno by-the-numbers technique to make this happen. Probably the best step to take inthis direction is to use the simplest possible circuit schematic and the simplest possi-ble layout. Complications in the schematic will only lead to additional interconnec-tions, which inevitably bring with them additional parasitic elements.

The art of a successful design often means maintaining simplicity in both circuitdesign and layout. In terms of layout, try initially to place all major components inpositions where the signal paths flow naturally from one device to another with aminimum of interconnecting metal. In most designs, it is good practice to place allof the input pads on one side of the chip (conventionally, this is the left side) and allof the outputs on the other (right) side of the chip. In a large, multifunction chip, thismay not always be possible, but if it is possible, this convention is very helpful inmaintaining the signal flow paths of minimum length, thereby minimizing parasiticeffects. In general, a meandering back and fourth of the signal flow path is to beavoided in layouts. Such back-and-fourth signal flows are certain to add to the para-sitic content of the circuit and degrade overall performance. It pays big dividendsfor the designer to consider carefully the signal flow paths from device to devicewithin the chip and to plan accordingly for the placement of each device in such away that the overall signal path flow is as natural and direct as possible.

14.4 Testability

Testability is of paramount importance with RFIC chips because there is no easyway to modify them once they are fabricated, making diagnostics of any problemsdifficult. Testability is accomplished in two ways. The first consideration is to besure that bonding pads pair of a standard size and spacing are provided at all RFinputs and outputs. These pad pairs, as discussed in Chapter 4, are useful whenusing a measurement device called an on-wafer probe station to test RFIC designsbefore they have been packaged—in fact, before the die are separated from thewafer. On-wafer probe equipment has tiny contacts that have been designed to pro-vide a very accurate 50 ohm impedance test point at the probe ends. In this way, anymeasurement device, such as a network or spectrum analyzer, may be connecteddirectly to the RFIC chip’s input and output terminals while the chip is still part ofan overall wafer. This type of testing is very useful and time saving in the prototypestage of development because it allows the designer to obtain performance data assoon as wafer fabrication has been completed without having to wait for the indi-vidual die to be separated from the wafer, packaged, and electrically evaluated on atest board.

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A second valuable technique for testability is to make use of test cells. Test cellsare critical portions of the overall circuit that have been cut out of the layout andplaced, together with sets of on-wafer probe test pads, in separate layouts. The testcell is used to trouble-shoot a design that does not function as expected. Since thefabricated chip cannot be cut up for testing purposes, it may be impossible to testcertain internal functions within the chip. If the RFIC has performance problemsthought to be linked to one of these internal functions, it will be very difficult to eval-uate the problem if you only have the input and output pads of the entire chip to test.However, by placing one or more of these critical circuits in a “test cell,” they can beevaluated piecemeal using the same on-wafer probing techniques as are used to testthe design as a whole. At a minimum, all sizes of transistors that appear in the designshould be included in their test cells.

Test cells, of course, occupy wafer area that could be used for the complete RFICor second versions of the complete RFIC. For this reason, it is not desirable to “gowild” and place every little subcircuit in its own test cell. Again, like most designchoices made in the RFIC world, it is very important to choose wisely which andhow many subcircuits will appear in test cells. Probably the best rule of thumb is tomake choices based on which circuits you think are most likely to cause problems.This is the same as saying, be aware during the initial design process whichsubcircuits have the most difficulty in achieving their goals. It is these criticalsubcircuits that should be placed in test cells for evaluation on a stand-alone basis.While you must always bet on success, it is wise to make special arrangement to testseparately those subcircuits or devices that you suspect may cause problems for theperformance of the overall design.

14.5 Types of CAD Systems

RFIC circuits have become so massive that it is impossible to consider doing anRFIC layout without using CAD software tools. Many fine tool packages availablein the industry allow the designer to make use of a wide variety of editorial featuresthat simplify the layout process. However, all CAD layout tools share the ability tooutput the final layout in a stream file language called Graphic Data System IIStream Format (GDSII). Since GDSII represents a common language among CADlayout tools, it makes it possible to develop a layout with one tool set and thentransfer the layout easily via GDSII to a different tool set. This is of critical impor-tance if you are constructing a layout on one tool set, and the foundry is using a dif-ferent tool set to perform DRC checks and to make masks. Before purchasing a set ofCAD tools, be sure to check with the foundry to insure file compatibility. You maywant to send test files generated on the CAD tools that you are considering purchas-ing and asking the foundry to verify that they can read these files.

The price of CAD layout tools varies widely depending on the supplier. SomeCAD layout tools come bundled with simulation software, while some do not. Somesimulators come bundled with a layout tool. You may or may not want to use thebundled tool combination. The advantage is instant compatibility between the sche-matic diagrams in the simulator and the layout elements showing up on the layouttools screen. This feature can be of great help when you are making editorial

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changes because it automatically updates the schematic if you make a layout changeand may update the layout if you make a schematic change. Some tool packages donot have the capability to make updates in both directions (i.e., changes to the lay-out may be reflected in the schematic, but changes to the schematic may not bereflected in the layout).

Your foundry may supply you with “applicas” for certain structures like tran-sistors and inductors. These applicas should always be used instead of creating thedevice from scratch because in some cases, like transistors, many levels are involvedin the process of creating the layout, and the applicas can save you a lot of work anduncertainty in getting the layout right. Some foundries also offer design IP forsale. Such IP contains certain subcircuits that may be very difficult and/or time-consuming to design. By purchasing the foundry’s IP for, say, a phase-locked loop, the designer is in effect trading money for the time necessary to do thedesign him- or herself. A second advantage of using an IP subcircuit is the assurancethat the foundry has completely evaluated this subcircuit design, and you candepend on its working correctly. The foundry will usually supply you with test datataken during verification.

Some examples of the leading CAD layout-tool suppliers include Cadence, Inc.,Mentor Graphics, and IC Editors. All of these tool sets have proven track records inthe industry and can be counted on to do an excellent job for the designer. As adesigner, you may want to do your own layouts, or you may want to outsource thelayout work (or, in a large company, you may make use of the services of a centrallayout group that serves design engineers in many parts of the company). Theadvantage to doing the layout yourself is the detailed knowledge that you have con-cerning layout routing decisions and basic floor planning. However, layout is atime-consuming process, and many designers prefer to work with a well-known andtrusted layout specialist. As the designer, you may need to spend considerable timewith the layout specialist to insure that the layout proceeds according to your ownvision. However, once the major decisions have been made and the process becomesmore or less mechanical, you, the designer, are freed up to return to what you dobest, which is circuit design. Layout specialists do layout every day of their workingweek, so they become very good at what they do. In most cases, the layout specialistcan complete a layout in less time than a designer, who does not have the daily expe-rience with the tools to gain the same level of expertise that the specialists has. Bothtechniques can be made to work quite well, and the choice may, in the end, dependon practical considerations like budgets and the availability of company resources.

14.6 Foundry Comparison

There are a number of excellent foundries for both InGaP/GaAs HBT and SiGeprocesses in the United States, Europe, and Asia. At present, the most widely usedGaAs HBT foundries are located in Asia. The Asian foundries offer larger wafersizes and lower wafer-fabrication costs than those found elsewhere, adding to theirpopularity. Some examples of these foundries are Win Semiconductor Corporationin Taiwan and Knowledge On, Inc., in Korea. In the United States, Triquint Semi-conductor, Inc., and GCS Corporation offer GaAs HBT foundry services. At present

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most of the leading SiGe foundries are in the United States. The chief examples areIBM and Jazz Semiconductors, Inc. Because SiGe is usually part of a BiCMOS pro-cess, it is always offered by a company that already has CMOS foundry capability.In Asia, TMSC offers a SiGe BiCMOS process.

When shopping for a foundry, the designer should, if possible, visit the foundryand talk personally to the foundry’s engineers. In a relationship with any foundry,it is very important to know whom to contact for technical help. All foundries havean excellent staff of modeling engineers and designers, like yourself. It is very impor-tant to get to know these people so they can help you when problems arise. Also,take the time to get to know the foundry’s CAD operators, these are the people whowill be processing your designs. If problems arise with either DRC errors or last min-ute corrections or additions, these are the people you will be working with.

When getting to know a foundry, ask about the details of their electrical models.These models include both transistors and passive devices, like thin film resistors,MIM capacitors, and spiral inductors. Be sure to check the model verification datato assure yourself that the foundry’s models are accurate, especially at high frequen-cies. Also, become familiar with the foundry’s reliability data. Ask questions abouthow they arrived at the data. What experiments and life tests have they performed,and are any of these tests ongoing? If they are ongoing, ask for updates of results asthey become available. Become familiar with the maximum current conditions ineach class of components based on reliability considerations. Often trade-offs willdevelop in the course of a design between performance and reliability. You need tounderstand completely the implications of these trade-offs so that you can makeinformed choices.

Many foundries will have alternative ways of forming resistors, capacitors, andinductors. While there is no fixed rule about which type of resistor, capacitor, orinductor you may choose, the decision may become clearer to you once you haveinvestigated the background and implications of each option. For example, animplant resistor may offer higher resistance than will a thin film resistor for a givensize, but its precision may not be as good as the thin film resistor’s. The choice in thiscase may be determined by considering whether you need high resistance in a smallsize or if you need high precision in a larger size.

Another sometimes difficult choice comes about in sizing transistors. The areaof a transistor may be increased either by adding emitter fingers and placing all unitcells in parallel or by increasing the length of the emitter finger in a unit cell, usingfewer unit cells to achieve a given transistor area. This is not an easy choice, and itmay depend on various modeling considerations. For instance, many foundries onlyprovide large-signal models for particular unit cell emitter lengths. In this case, thedecision is an easy one: you stay with the emitter length supported by a foundrymodel. However, if the foundry’s models support many choices of emitter-fingerlength, the only way to make an informed decision is to experiment in your simula-tions with transistors of the same total size but with different emitter-finger lengths.This process becomes one of understanding how the transistor’s parasitic elementsare affected by its unit cell’s aspect ratio. At low frequencies, it may not matter whataspect ratio you choose, but as the frequency increases, you may find that the shorteremitter fingers are more favorable.

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14.7 Reticle Assembly

The first step in photo mask making is the assembly of a “reticle” which contains allRFIC and test cell layouts. Many foundries will take care of assembling your reticle,but some require the designer to perform this task. It is a straightforward procedure,but a number of basic considerations must be adhered to. To start the process, con-sider the completed reticle shown in Figure 14.1. This pattern will be step andrepeated across the entire wafer during fabrication. In order to assemble all circuitand test cell designs together into a common reticle, some base rules must beobserved:

1. Add (1/2) street borders around all design layouts. Be sure that the emitterfingers of all transistors are oriented in the same direction. The foundrydevice models assume a particular crystalogical direction for the device’semitter fingers, and the model only works for this direction. Therefore, alltransistors must, in the end, be oriented in the same direction relative tosome fixed angular reference (often a “flat” on one side of the wafer). SeeFigure 14.2.

2. Assemble the reticle by joining all of the (1/2) streets for each circuit designand test cell. There can be absolutely no gaps between the (1/2) streets of anydesigns. When the circuits are brought together, they form a common street

14.7 Reticle Assembly 289

Figure 14.1 The layout of a completed reticle.

between them of standard width simply by combining the (1/2) streetsassociated with each circuit, as shown in Figure 14.3.

3. All designs must share a common dimension and, perhaps, have only two orthree options for the second dimension. If the common dimension isarranged in the horizontal direction, then all columns will have the samewidth, but there may be more than one row width. In my experience, it is fareasier to place all designs within a (1/2) street border with commondimensions. This simplification will waste a little wafer area, but it willgreatly simplify the reticle assembly process.

4. Arrange all circuits into a common array of rows and columns withstreets running between each circuit design, forming the reticle, as shown inFigure 14.3. The foundry will give you a specification about the overall sizeof the reticle. In some cases, the overall reticle size is fixed; at other foundries,it is expressed as an upper-bound maximum. In either case, it is usually bestto use the maximum reticle size. Of course, this will force the designer tomake decisions about the mix of designs that populate the reticle. You maydecide to put ten layouts of design A on a reticle but only five layouts ofdesign B. This choice reflects your desires relative to how many die of a givendesign you wish to receive after wafer fabrication. In most cases, you onlyneed to receive a very limited number of tests cells; however, circuit designsthat you may wish to sample customers with may need to be available inhigher quantity.

5. The foundry will require that in your reticle you either locate, or make spaceavailable within the reticle to locate a foundry layout pattern called aprocess control monitor (PCM). The easiest way to do this is simply to

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Figure 14.2 An example of a simple feedback amplifier die layout surrounded by (1/2) streets.

remove one or more of your design layouts and to insert the PCM there.Some foundries will have specific locations for their PCMs, which you must

14.7 Reticle Assembly 291

Figure 14.3 An array of prototype die layouts arranged in rows and columns separated by streetsthat are formed as the individual die layout (1/2) streets are merged together.

Figure 14.4 The foundry’s PCM pattern layout must be located at a position (or positions) withinthe array of die layouts that make up the reticle. The foundry specifies the PCM position (orpositions).

adhere to. Some may even require more than one PCM in your reticle. Areticle containing a PCM is shown in Figure 14.4. After wafer fabrication,assuming the wafer is acceptable to the foundry, you will receive a completeset of PCM data, sometimes with a map of how the data is distributed acrossthe wafer. This is very handy data to have and should be examined carefullyfor signs of device performance gradients across the wafer. Fortunately,bipolar device technology is very uniform, and such gradients (which areoften experienced with field-effect transistor technologies) are rare withbipolar processes.

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C H A P T E R 1 5

RFIC Economics

15.1 Levels of Integration

The optimal level of integration for a given RFIC can often be a hotly debated topic.Many considerations must be researched in order to make a truly informed deci-sion. Integrating a chip to very high levels has two important benefits and severalpotential disadvantages. The benefits are smallest possible size and lowest possiblecost, which are truly huge benefits. The disadvantages are possible yield problems(it only takes one defect in a very large chip to render it useless), the inability to usedifferent technologies in areas where their strengths lie, and the enormous task ofassembling so many circuits on a common die. Another potential problem is madeespecially serious when a large integrated chip enters the test, verification, and trou-bleshooting phase. It is impractical to bring all critical test points out of the chip toenable complete testing of all circuits. Therefore, the designer who troubleshootssuch a large circuit has to rely on a combination of simulations, theories, andhypotheses to make progress in identifying causes and solutions for problems. Ingeneral, the degree of difficulty in troubleshooting is a very steeply increasing func-tion of the total die area. This is not to say that you should not attempt a large,highly integrated design because this is how true progress is made in the RFIC field,but you must be realistic and budget enough time for evaluations and redesign. It isnot uncommon with a large, highly integrated design to go through as many as fouror five design-fabrication cycles (spins). The cost of such a design exercise can bestaggering, and the time to market can become a problem if the competition is mak-ing good progress.

The alternative is to split the overall system design into several smaller pieces.Several advantages can be achieved by partitioning the system in this way. The firstadvantage is in keeping each die at a manageable size. The second is the ability touse multiple technologies to advantage (i.e., the LNA could be in PHEMT, the PAcould be in GaAs HBT, and so forth). By partitioning the system, the best possibleperformance can be achieved simply by making use of the performance advantagesof two or more different technologies. This is clearly a case of trading performance(highest with less integration) for low production cost (with higher integration). Butperhaps the most important feature of lower integration with a partitioned system isthe ability to test and troubleshoot more easily. Since the individual die have fewercircuit functions each, the test-and-evaluation phase of the project is significantlysimplified. Divide and conquer is at work here. Another important outcome will befewer spins to success because a more complete evaluation can be accomplished ateach spin. This translates into shorter time to market.

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To sum up, the partitioned RFIC system will have better performance, take lesstime (and less money) to develop, and get to market more quickly than the equiva-lent fully integrated chip system. However, the price paid for these advantages ishigher production cost and larger area (because the customer will have to set asidemore board area for this design). Another cost driver with the partitioned approachis the added cost of multiple packages. No longer is it a neat situation of one die inone package. The partitioned approach produces multiple die in multiple packages.This is called a chip set, and it is always more costly to use a chip set than a sin-gle-chip solution.

Some manufacturers take the middle road by designing and prototyping a parti-tioned system. The resulting chip set is used to estimate market size and acceptabil-ity. Only when the market potential is deemed large enough to warrant thedevelopment cost of a fully integrated solution will a company take on its develop-ment. Of course, the danger of this approach is that if a competitor company has“leapfrogged” straight to a fully integrated solution they may be in a position to takeaway most of the business before the company which is taking the more cautious,two-phase approach can complete the development of a fully integrated chip andenter the market place with this solution.

15.2 Single-Ended versus Differential Topologies

A growing trend among RFIC designers is to use more and more differential circuitswithin their designs. This trend is driven by a number of considerations. Probablythe most important reason for this trend is the widespread use of Gilbert cell mixers,which are naturally differential at all three ports. Most wireless systems today makewidespread use of Gilbert cell mixers both for receiving downconverters and trans-mitting modulators. Because of the heavy reliance on phase modulation in most, ifnot all, wireless applications, these mixers and modulators are usually arranged intoquadrature-phase I/Q mixers and modulators designed for the detection and genera-tion of phase-sensitive modulations. This trend requires that two Gilbert cell mixerbe associated with each system function, multiplying by two the number of Gilbertcell mixers required by a typical system. This enlarged population of Gilbert cellmixers means that there are a lot of differential inputs and outputs within a typicalsystem. Rather than facing the difficult task of converting all of these inputs and out-puts to single-ended format (being on-chip does not make this task any easier), it isgenerally easier simply to design all on-chip components in differential form. Thisapproach is not really all that difficult, and since transistors are essentially free inintegrated circuits, there is little cost penalty to this approach. Of course, thedesigner has to be careful not to let the overall area become significantly inflated bythe presence of all these differential circuits, but this is not generally a serious prob-lem. One way to answer the single-ended-versus-differential question is to simplyconsider the size of the design and the overall count of Gilbert cell mixers. If the chipis very small and has no mixers (for example, a simple Darlington amplifier), it willbe best to design it in single-ended form. However, if the design is large enough tocontain several mixers, then it is best to use all differential circuits and make allinputs and outputs differential also. The customer is free to convert these inputs and

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outputs from differential to single-ended form by using off-chip commercial balunsplaced right next to the chip on the system’s circuit board.

15.3 Process Technology Choices

Not too many years ago, there were only two fabrication technologies available tothe RF/microwave circuit designer. The first was standard silicon bipolar transistortechnology, which was only good for frequencies up to about 1 GHz. The secondwas GaAs MESFET technology, which held the promise of operation up to 10 GHz.That situation has changed over the past few years. Today, there are as many as fivemajor technologies (GaAs HBT, GaAs MESFET, GaAs PHEMT, RFCMOS, andSiGe) with at least four more technologies waiting in the wings for industry accep-tance. As you might expect, no one technology offers the lowest cost and highestperformance in all applications. This makes the job of choosing a technology thatmuch more difficult. There is always the performance-versus-cost issue, but eventhat choice is further complicated by the question of whether we are talking aboutprototyping costs or production costs.

Let us first look at performance considerations. On a purely performance basis,the best technology for an LNA is GaAs PHEMT. Also, GaAs PHEMT makes reallyexcellent switches which are only exceeded in performance by PIN diode switches.In terms of power amplifiers, GaAs HBT makes really excellent, highly linear poweramplifiers. Because of their low threshold voltages (Vt for RFCMOS and Vbe forSiGe), both RFCMOS and SiGe are excellent technologies for designing Gilbert cellmixers and modulators for applications requiring low dc voltages.

In terms of passive components, like spiral inductors and MIM capacitors, thesemi-insulating GaAs substrate used for GaAs HBT is unbeatable. All silicon-basedtechnologies have a conductive substrate that potentially holds loss mechanismsthat reduce performance.

VCOs are best designed with a bipolar technology in order to keep the 1/f con-tributions to their phase noise to a minimum. All field-effect transistor technologies(MESFET, PHEMT, RFCMOS) have serious 1/f noise problems and are bestavoided in favor of bipolar technologies in applications requiring extremelylow-phase-noise VCOs.

If it is imperative that only one technology be used for your designs, then youmust learn to live with its weaknesses. A single-technology design will always haveperformance compromises. This is a given even before the design process begins.The main reason for pursuing a single-technology design is cost, either prototypecost, or more likely production cost. Cost is a very serious matter and cannot betaken lightly. However, the designer needs to recognize from the outset that using asingle-technology design is an exercise in trading off performance for cost. If this isdeemed to be a good trade-off in a business sense, based on market research, thentaking this path makes good sense. But if there is any expectation that the finaldesign must have maximum achievable performance and simultaneously lowestpossible cost, then red lights should go on. The first law of good engineering prac-tice states that you can’t get something for nothing. You can play the trade-offs toyour own advantage, but you can never have it both ways. Engineering is the art and

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science of crafting favorable trade-offs. It is very much like drawing up and consum-mating a good business deal with nature. You can never have it all, but with skill andcleverness, at the end of the day you can achieve those objectives that are mostimportant by giving up those objectives that are less important.

15.4 Area versus Performance Trade-offs

A very important trade-off in RFIC design is between chip area and performance.This seems like a very straightforward trade-off, but a lot of subtle factors affect thedecision that needs to be made. If you implode the chip to an extreme degree to savearea, all of the metal lines, transistors, resistors, capacitors, and inductors will betouching each other. Of course, at this point the chip is nonfunctional because ofelectrical short circuits. However, there is a broad middle ground in which the harddecisions need to be made. Let me say at the beginning that chip area and chip costare essentially the same thing. This is because there is a fixed fabrication cost perwafer, which translates into a cost per die that is inversely proportional to its area(the number of die available on a given wafer equals the area of the wafer divided bythe area per die). The bottom line is that from a cost point of view, there is heavymotivation to keep the die area to an absolute minimum. As I have already pointedout, if we “crunch” the chip’s area down to some absolute minimum, at some pointin the crunch process the chip could become nonfunctional. So, the practical ques-tion to be answered is how much can the chip’s area be reduced before the impact onperformance becomes unacceptable. This question assumes either that you have aperfect simulator that can give you an accurate assessment of performance for eacharea reduction or that you have unlimited time and resources to test hardware per-formance at each step in the area-reduction process. For most designers, neither pos-sibility exists. Therefore, chip-area reductions become largely an exercise in riskmanagement. Every proposed change in the design’s layout will have some impacton the design’s performance (usually performance will degrade if the change is asso-ciated with an area reduction, but not always). Each change is a special case untoitself. For instance, if he or she wishes to change the aspect ratio of a large capacitorto allow the occupation of some unused space, the designer must ask how the capac-itor’s model is changed by the change in aspect ratio. At low frequencies, the answer,most likely, is not much, but at higher frequencies, the simple answer may no longerhold true. Modified current paths will always have parasitic elements associatedwith them that can play significant performance roles, especially at high frequencies.Another factor to consider is how much more strongly a device couples to its neigh-bors as they are packed closer and closer together. Cross talk between componentscan become a leading source of performance degradation as die area is reduced. Thissituation is equivalent to the noise problems experienced by residents of an apart-ment complex who are required to live closer and closer to their nearest neighbors.Component-to-component interaction and cross talk can be a major driver in deter-mining the performance-versus-area trade-off.

A second important area affecting performance as the chip’s area is reduced isthe length of metal interconnecting lines. Initially, you would expect that a smallerchip would have shorter interconnecting lines. In many cases, this may be true, and

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it is even possible that performance enhancements may result from this process ini-tially. However, as the components get closer and closer together, it becomesincreasingly difficult to route the metal lines in such a way that overlaps areavoided. When overlaps occur, there is always a coupling capacitance between theoverlapping lines (assuming they are different metal layers), leading to complicatedinteractions and cross talk. Another difficulty is with metal lines that need to be aspecific length. For instance, in a Gilbert cell mixer, in order to maintain peak per-formance, it is very important that the interconnecting metal on both sides of themixer have identical lengths. However, this may no longer be possible if the areaavailable for the mixer and its connections to surrounding components is signifi-cantly reduced. There will come a point where area reductions will make it very dif-ficult to maintain the kind of metal-line-length symmetry that allows balancedcomponent designs, like Gilbert cell mixers, to perform to their peak potential.

15.5 Electrical Yield

In most cases, a given die’s electrical yield is determined by the severity of its specifi-cations. A relatively easy set of specifications usually implies a high electrical yield,whereas a very difficult set of specifications may lead to a lowered electrical yield.This is simply a case of minor process variations’ having an effect when the specifi-cations are inherently difficult to achieve, whereas when the specifications arerelatively easy to achieve, minor process variations have very little impact onelectrical yield.

Bipolar processes are usually very stable from wafer to wafer. This is becausethe important parameters for determining electrical performance have already beenbuilt into the wafer during the process of epitaxial growth. In many cases, bipolarRFICs are tested only for dc conditions and not for RF performance due to the highdegree of confidence in such a process’s repeatability. If the decision is made to per-form RF electrical tests on each device, it is often best to delay the testing until thedevices have been packaged in order to make use of automated test systems, such ascomputer-controlled network analyzers and chip handlers. The question is always,how much testing is enough? Perhaps only few key electrical parameters are neces-sary to perform a meaningful test. Perhaps one or two critical electrical specifica-tions need to be 100 percent tested, but nothing else. Much good judgment must beexercised in making these decisions.

If the die is a semicustom part targeted for only one customer, the manufactur-ing engineers at both companies must get together and agree on a set of tests that areboth meaningful and cost-effective. The key in such cases is to identify those specifi-cations that are truly critical and, for testing purposes, to disregard the rest.

It is very important economically that once a part reaches production, its yieldin manufacturing be quite high. It is poor practice to move a product into the pro-duction with a low yield in final electrical testing. Such a situation would mean thata lot of parts are thrown away, which is never a good thing. If you find yourself in asituation such as this, it becomes important to work with the designers in order tomodify the design such that the electrical yield can be improved to at least 70 to 80percent. In a large-scale manufacturing situation, it is worth investing considerable

15.5 Electrical Yield 297

engineering resources to improve the chip’s design to the point that electrical yield isacceptable. It is in no one’s best interest to continue running parts that will only belargely thrown away at the end of the line.

15.6 Prototype Costs

When working with a foundry, it is very important to understand what costs you arefacing in the near term and, ultimately, in larger-scale production. During theprototyping phase, foundries may charge their customers for a variety of services.The list of prototyping services varies from foundry to foundry, but the following isa partial list based on experience with a number of InGaP/GaAs HBT foundries:

1. Design rules: Foundries often charge $3,000 to $5,000 for a set of their latestdesign rules.

2. Training: The foundry may offer a course in how to design with theirparticular set of design rules and models. Such a course may last one day toone week at a cost of $10,000 to $30,000.

3. DRC (design rules check): Most foundries offer a DRC check of your designas part of the overall prototyping service. Even if you have your own abilityto perform DRC, it is well worth making use of the foundry’s DRC servicefor the piece of mind of knowing that the foundry agrees that your design ismanufacturable.

4. Mask making: It will cost $15,000 to $20,000 for a mask set of upwards offifteen layers. This number can be greatly reduced for prototyping by using aso-called pizza mask, in which case you will share the cost of masking withseveral other organizations, whose parts will also be fabricated on thecommon wafer that you all share. The cost of a pizza mask and prototypefabrication is about $5,000 to $15,000 for a 5 × 5 mm slice of the materialholding your prototypes.

15.7 Production Costs

Production costs are mainly determined by the cost of fabricating a wafer and howmany of your die it will yield. If you are forced to make a new production mask, thiscould mean an additional $20,000, or perhaps more. Other than that, it is purely amatter of determining how many of your die will be yielded by the wafer.

As an example, we consider determining the cost of a 1,100 microns ×900 microns die. The major cost items involving RFICs are

1. Die size2. Wafer fabrication cost3. Cost per die = (die area/total wafer area) times the fabrication cost per wafer4. Yield by 80 percent for material lost in the saw streets5. Yield by 80 percent for electrical yield6. Added package cost (about $0.10 for a simple SOT-89 plastic package)

298 RFIC Economics

7. Added cost of electrical testing (about $0.20 for a simple die)

Therefore the cumulative cost of manufacturing this die is:

1. Wafer fabrication cost per wafer is $3,000.2. Cost per die = $3,000 (1,100 × 900/7,853,981,635) = $0.37.3. Yield for streets = $0.47.4. Electrical yield = $0.59.5. Package cost (assume plastic) = $0.69.6. Electrical testing = $0.89.

15.7 Production Costs 299

Acronyms

A attenuationACPR adjacent channel power ratioADC analog digital converterADS Advanced Design SystemAM amplitude modulationAMPS Advanced Mobile Phone ServiceBER bit-error rateBiCMOS bipolar/complementary metal oxide semiconductorBJT bipolar junction transistorBPF band-pass filterBPSK binary phase-shift keyingBWO backward wave oscillatorCAD computer-assisted designCDMA code domain multiple accessCM collector contact metalCMOS complementary metal oxide semiconductorDRC design rule correctionDSB double side bandDSP digital signal processingDSSS direct sequence spread spectrumDTO dielectrically tuned oscillatorEDA electronic design automationEVM error vector magnitudeFCC Federal Communications CommissionFET field effect transistorFM frequency modulationFOM figure of meritGaAs gallium arsenideGDSII Graphic Data System II Stream FormatGe germaniumGFSK Gaussian frequency shift keyingGPS Global Positioning ServicesGSM Global System for Mobile CommunicationsHBT heterojunction bipolar transistorHF hydrofluoric acidHPF high-pass filter

301

I in phaseIC integrated circuitIEEE Institute of Electrical and Electronics EngineersIF intermediate frequencyIIP3 input intermodulation intercept pointInP indium phosphideIP intellectual propertyIS-95 CDMA standardISM industrial scientific medicalLC inductor capacitorLDMOS lateral diffused metal oxide semiconductorLMR land mobile radioLNA low-noise amplifierLO local oscillatorLPF low-pass filterLSB lower side bandM1 first metalM2 second metalMAG maximum available gainMBE molecular beam epitaxyMCLIN ADS schematic elementMESFET metal-semiconductor field-effect transistorMIM metal insulator metalMLIN ADS schematic elementMMDS Multipoint Microwave Distribution SystemMMIC microwave monolithic integrated circuitMOCVD metal oxide vapor depositionMOS metal oxide semiconductorMOSCAP metal oxide semiconductor capacitorMRIND ADS schematic elementMSUB ADS schematic elementN N–quadrature amplitude modulation)NADC North American Digital CellularNF noise figureNPN n-type, p-type, n-type bipolar transistorNV nitride viaOFDM orthogonal frequency division multiplexingOIP3 third-order intermodulation intercept pointOIP5 fifth order intermodulation intercept pointOQPSK off set qudrature phase shift keyingPA power amplifierPAE power-added efficiencyPCB printed circuit boardPCM process control monitorPCMCIA standard plug-in module for lap top computersPCS personal communication servicePDA personal digital assistant

302 Acronyms

PDK process design kitPHEMT pseudomorphic high electron mobility transistorPIN p-type, insulator, n-type diodePV polyimide viaQ quadrature phaseQAM quadrature amplitude modulationQPSK quadrature phase-shift keyingRC resistor times capacitance time constantRF radio frequencyRFCMOS radio frequency complementary metal oxide semiconductor

technologyRFIC radio frequency integrated circuitRL resistor times inductorRMS root mean squareS/N signal-to-noiseSi siliconSiGe silicon germaniumSMT surface mount technologySNR signal-to-noise ratioSP2T single pole two throw switchSPG Gummel Poon spice modelsSPV scratch protection viaSSB single side bandSV substrate viaT/R transmit/receiver switchTCC temperature coefficient of capacitanceTCR temperature coefficient of resistanceTDMA time domain multiple accessTFR thin film resistorTSMC Taiwan Semiconductor Manufacturing Co.TWT traveling-wave tubeUHV/CVD ultrahigh vacuum chemical vapor depositionUSB upper side bandUWB ultrawidebandVBIC Vertical Bipolar Industrial Committee bipolar transistor

modelVCO voltage-controlled oscillatorVGA variable gain amplifierVSWR voltage standing wave ratioWLAN wireless local-area networkWUSB wireless USBYIG yittrium iron garnetYTO YIG-tuned oscillator

303

About the Author

Allen Sweet has been a consultant in the field of RF and microwave circuit designfor nearly 30 years. His clients range worldwide, and include many of the leadingcorporations engaged the design of RF and Microwave devices, circuits and sys-tems. His first book, on designing MIC and MMIC Amplifiers and Oscillators, waspublished by Artech House, Boston MA, in 1990. He holds a Ph.D. degree in Elec-trical Engineering (with minors in Physics and Applied Physics) from Cornell Uni-versity, and has published widely in the field of RF/Microwave circuits (more than30 published journal articles and conference papers). In 1977 he was a co-receiverof the IEEE MTT Microwave prize for his work on phase locked power amplifiersfor FM/FDM telecommunications applications. In 1992 he served as the technicalprogram chairman for a first ever conference (held in Santa Clara California)devoted to exploring newly emerging commercial applications of RF and Micro-wave technology. Since 2002 he has been an adjunct professor of Electrical Engi-neering at Santa Clara University in Santa Clara California; where he teachesgraduate classes in Radio Frequency Integrated Circuit design, and undergraduateclasses in electrical circuits. He is a member of the IEEE.

His current research interests are low phase noise VCOs, mixers, and low noiseand power amplifiers. His hobbies are amateur radio, reading, music, and travel.

305

Index

1/f noise. See Flicker noise

AAbrupt-junction varactor diodes, 243–48

capacitance and resistance relationships,244

capacitance change, 245doping profile, 244–45frequency-tuning ratio, 246at low reverse voltage, 244See also Varactor diodes

Active device sizing, 177–81Active mixers, 200–217

defined, 200fully balanced multiplying, 205–7single-balanced multiplying, 200–205topologies, 200See also Mixers

Adjacent channel power ratio (ACPR), 15defined, 145power amplifiers, 145–46specifications, 145, 146two-stage differential PCS power amplifier,

188, 189Advanced Mobile Phone Service (AMPS), 14Amplifier design, 105–13

cascode amplifiers, 111–13differential amplifiers, 109–11Fano’s limit, 106–7gain compensation, 106matching techniques, 105–6stability, 107–9See also Low-noise amplifiers (LNAs);

Multistage amplifiers; Poweramplifiers

Amplitude modulation (AM) noise, 263Analog digital converters (ADCs), 21AppCAD, 174–75, 226Applicas, 287Applications, 10, 13–24

Bluetooth, 17–18

cellular/PCS handsets, 13–15cellular/PCS infrastructure, 15–16cognitive radio, 20–21digital TV and set-top boxes, 20physical layer standards, 22–24spectrum allocation, 21–22UWB, 18–19WiMax, 19–20WLANs, 16–17

AutoCAD, 70Avalanche breakdown, 45Avalanche multiplication, 78

BBack-to-back transformers, 97Backward wave oscillators (BWOs), 1Ballasting, 166, 167Baluns, 102–4Band-pass filters (BPFs), 93–95

construction methods, 93–94lumped-element, 94–95S-parameters, 96two-section, 96

Base after gate (BAG), 76Base-biasing network, 152, 154Bias circuits

power amplifiers, 150–54for stabilizing bipolar amplifier at high

frequencies, 151for stabilizing bipolar amplifier at low

frequencies, 151BiCMOS, 5, 9

fabrication, 71SiGe process, 83

Binary phase-shift keying (BPSK) modulation,26–27

analog multiplying mixer, 27constellation diagram, 26idealized generator, 26phase noise, 27signal generation, 27

307

Bipolar process stability, 297Bit-error rate (BER), 10, 25BJT devices, 71

RF, 71Si, 71, 72

Blocking capacitors, 152Bluetooth, 17–18, 23Boltzmann’s constant, 119Bonding pads, 60–61

cross section, 61input/output pattern, 61layout, 60mechanical strength, 60in on-wafer testing, 61

Buffer amplifiers, 41, 219Bypass capacitors, 152

CCadence Spectra RF simulation tool, 80Cadence tool set, 79–80, 81CAD layout tools, 286–87

Graphic Data System II Stream Format(GDSII), 286

InGaP/GaAs HBT, 70SiGe HBT, 86–87suppliers, 287

Cascode amplifiers, 111–13construction, 111–12defined, 111schematic diagram, 112simulated gain and stability, 113voltage gain, 112

Cellular/PCS, 13–16handsets, 13–15infrastructure, 15–16

Cellular/PCS downconverting RFIC, 221–29block diagram, 222differential LNA layout, 229differential LNA schematic diagram, 223Gilbert cell mixer, 224Gilbert cell mixer layout, 229layout, 228LO phase shifter schematic diagram, 225lumped-element low-pass filters, 223, 225overall performance simulation, 227time domain plot, 228

Cellular repeaters, 16Choke inductors, 152Class AB power amplifiers, 139–41

collector current, 140current waveform, 140dc power, 140–41

defined, 134efficiencies, 139loadline resistance, 140–41power-added efficiency, 140–41RF power output, 140–41See also Power amplifiers (PAs)

Class A power amplifiersdefined, 134loadline, 138See also Power amplifiers (PAs)

CMOSdevices, 9fabrication backbone, 85gate fabrication, 76passive devices, 85

Code domain multiple access (CDMA), 14,15, 22

envelope source parameters, 188, 190handset power amplifiers, 192modulation spectrum, 145nonlinearity and, 133simulated constellation diagram, 191,

192, 193simulated spectrum, 191, 192, 193

Cognitive radio, 20–21Colpitts oscillator circuit, 258–61

common-base, 253, 257common-collector, 159, 253, 262defined, 258with Gummel Poon model, 257, 259schematic diagram, 253, 257, 259simulated impedance, 260, 262See also Feedback circuit topologies;

Voltage-controlled oscillators (VCOs)Costs

production, 298–99prototype, 298technology, 295–96

Couple microstrip lines, 54, 55Crossover capacitances, 61–62Current-controlled current source (CCCS), 254

DDarlington amplifiers, 154–64, 269

advantages, 155gain estimate, 155with horizontally aligned emitter fingers,

162, 163layout, 159lumped-element, 157–58noise figure, 160parasitic-enhanced performance, 161

308 Index

parasitic inductance, 164power output, 155properties, 154–55schematic diagram, 155, 156, 160simulated power input versus power output,

158, 161simulated S-parameter, 157, 160, 163, 164stability performance, 164third-order intermodulation intercept point,

158with vertically aligned emitter fingers, 162wideband gain block, 154–64without layout parasitic elements, 163See also Power amplifiers (PAs)

Darlington LNA, 127–32compression point, 131defined, 127–28differential broadband, 130–31layout, 130noise figure, 129schematic diagram, 129simulated S-parameter, 129See also Low-noise amplifiers (LNAs)

Dc offset, 38Dc power efficiency, 25Device models

InGaP/GaAs HBT, 45–48SiGe HBT, 79–81

Device-to-device isolation, 77Dielectrically tuned oscillators (DTOs), 267Differential amplifiers, 109–11

performance, 111schematic diagram, 110simulated gain and stability, 111voltage gain, 111

Differential Darlington LNA, 130–31Differential filters, 95–99

schematic diagram, 98simulated S-parameters, 98, 99

Differential I/Q phase-shifting network, 104Differential PCS power amplifier, 181–93

ACPR, 188, 189ADS CDMA schematic diagram, 190ADS GSM signal source, 189ADS harmonic-balance controller, 188base bias, 182block diagram, 183collector bias, 182constellation diagram, 189, 190–91envelope-simulation controller, 189first stage calculation, 182first stage schematic diagram, 183

layout, 193output stage size calculation, 182output transistor schematic diagram, 186RF collector voltage, 185second stage schematic diagram, 184simulated CDMA spectrum, 191, 192, 193simulated dynamic loadline, 187simulated GSM spectrum, 189, 190simulated OIP3, 187simulated power input versus power output,

185simulated S-parameters, 183, 184simulated third-harmonic output, 185simulated voltage and current waveforms,

186Differential topologies, 41, 294–95Differential VCO, 95, 272–78

electronic tuning and, 279–81layout, 275phase noise, 277, 278power output simulation, 277schematic diagram, 274simulated S-parameters, 276top-level schematic diagram, 274varactor resonator schematic diagram, 275See also Voltage-controlled oscillators

(VCOs)Digital TV, 20Diode mixers, 197–200

conversion loss, 197double-balanced, 199passive, 197–98single-balanced, 198–99single-diode, 198See also Mixers

Double-balanced mixers, 199Double-conversion superheterodyne receiver,

36Downconverting mixers

block diagram, 197cellular/PCS, 221–29Gilbert cell, 216single-balanced transistor, 204See also Mixers; Upconverting mixers

EEber-Moll equation, 110Economics, 293–99

area versus performance trade-offs, 296–97differential topologies, 294–95electrical yield, 297–98integration levels, 293–94

Index 309

Economics (continued)process technology choices, 295–96production costs, 298–99prototype costs, 298single-ended topologies, 294–95technology costs, 295–96

Electrical yield, 297–98Energy-conversion process, 248Error vector magnitude (EVM), 30, 32

defined, 146power amplifiers, 146–47in UWB systems, 146in WiFi systems, 146

FFano’s limit, 106–7Feedback

application, 164in LNAs, 123parallel network, 127resistors, 165series, 165

Feedback circuit topologies, 252–61Colpitts oscillator circuit, 258–61negative-resistance oscillator circuits,

252–58See also Voltage-controlled oscillators

(VCOs)Feedback power amplifiers, 164–71

ballasting, 166ballasting resistor layout, 167–68layout, 68, 170lumped-element circuit design, 169lumped-element circuit schematic, 169RF resistors, 165schematic diagram, 165, 166simulated OIP3 versus frequency, 171simulated power input versus power output,

171simulated S-parameters, 169, 170See also Power amplifiers (PAs)

Figure of merit (FOM), 278–79Filtering, mixers, 197Flicker noise, 118, 119–20

bipolar transistor susceptibility, 120defined, 119problem, 120spectrum, 119trapping states, 120See also Noise

Foundriesapplicas, 287

comparison, 287–88getting to know, 288PCM pattern layout, 291

Frequency doublers, 231–33differential, 232–33diodes, 231Gilbert cell, 236, 237schematic diagram, 232, 234simulated output power, 233topology, 231waveform diagram, 232

Frequency multipliersdesign, 231–39diode-type, 235doublers, 231–33translators, 235–39triplers, 233–35

Frequency-temperature stability, 261–62Frequency-translating upconverting mixer, 31Frequency translators, 235–39Frequency triplers, 233–35

Gilbert cell, 236, 237–39output voltage waveform, 235schematic diagram, 234simulated output power, 235waveform diagram, 234

Front-end attenuation, LNAs, 117Fully balanced active multiplying mixers.

See Gilbert cell mixers

GGaAs HBTs, 5

temperature rise, 45wafer cross section, 44wafer fabrication, 44See also Heterojunction bipolar transistors

(HBTs)GaAs/InGaP interconnect lines, 82GaAs MESFETs, 2, 3GaAs PHEMT, 295GaAs varactor diodes, 247Gain compensation, 106Gaussian frequency-shift keying (GFSK), 18Gilbert cell mixers, 30, 41

circuit arrangement, 211circuit diagram, 209–10circuit schematic diagrams, 206defined, 205differential collector current, 209differential output current, 210–11differential pair of transistors, 209disabled transistor and, 214

310 Index

downconverting, 216as frequency multiplier, 235–39intermodulation spurs, 215as I/Q mixers, 217–19as I/Q modulators, 219–21isolations, 213LO transistors, 207nodes of operation, 211noise figures, 216–17performance parameters, 212–13RF and LO match, 214RFIC, 224schematic diagram, 205signal analysis, 208–9simulated conversion gain, 212, 213simulated input and output spectra, 215simulated upconverting conversion gain,

215top transistors, 208upconverting, 216See also Mixers

Global Positioning Services (GPS), 19Global System for Mobile Communications

(GSM), 15, 22Golden Gate harmonic-balance simulator,

80–81Graphic Data System II Stream Format

(GDSII), 286Gummel Poon model, 8, 45

large-signal, 46limitations, 45simulated dc IV curves, 47S-parameter simulation with, 47

Gummel Poon SPICE models (SPG), 79

HHeterojunction bipolar transistors (HBTs)

advantages, 7–8GaAs, 5, 44–45GaAs/AlGaAs, 7InGaP/GaAs, 7, 10, 43–70InP, 8–9SiGe, 10, 71–87technologies, 8

Heterojunctions, 6–7High-pass filters (HPFs), 93

phase shifter, 103schematic diagram, 93simulated S-parameters, 94, 95single section, 93two-section, 93, 95

IIC Editors layout tool, 70Image filters, 34–35InGaP/GaAs HBT, 7, 10, 43–70

bonding pads, 60–61CAD layout tools, 70crossover capacitances, 61–62cross section, 45device models, 45–48fabrication layers, 49–50fabrication technology, 43–70, 181Gummel Poon model, 45layout example, 65layout parasitic elements, 65, 66maximum electrical ratings, 67–70microstrip lines, 53–55passive structures, 48–67process layer resistivity, 52process layer thickness, 52process minimum layer line spacing, 52process minimum layer line widths, 52spiral inductors, 62–64transistor dummy cells, 64–65transistor structures, 43–45VBIC model, 45–46See also Heterojunction bipolar transistors

(HBTs)InP HBT, 8–9Input-referred mean-squared noise voltage,

124Interference, 33I/Q demodulators, 29I/Q mixers, 217–19

buffer amplifiers and, 219circuits in differential form, 218signal leakage, 218See also Gilbert cell mixers

I/Q modulators, 30–32, 219–21architecture, 30defined, 30, 221frequency-translating upconverting mixer,

31input voltage, 220output, 32, 220simulation, 221specifications, 221

I/Q receivers, 25–30

JJohnson power limit, 78

Index 311

KKirk effect, 73

LLayout design strategies, 283–92

CAD systems, 286–87foundry comparison, 287–88minimum area, 283on-chip versus off-chip component

decisions, 283–84parasitics, minimizing, 284–85reticle assembly, 289–92testability, 285–86

Linear efficiency, 144Loadline impedance, 179Loadline resistance

class A amplifiers, 138class AB amplifiers, 140–41simulated, Smith chart, 148unit cell, 175

LO leakage, 38, 39Low-noise amplifiers (LNAs), 10, 32, 41

best technology for, 295circuit topologies, 118–26Darlington, 127–32design, 115–32effective, 126feedback, 123front-end attenuation and, 117input circuit, 124matching topology, 122multistage, 173–75noise figure calculation, 125noise figure concepts, 115–16noise temperature, 116–17parallel feedback network, 127project balance, 126purpose, 32in receiver sensitivity, 32–33schematic diagrams, 123, 124, 125, 127single-ended PCS, 126–27single-stage, 123, 124, 125, 127See also Amplifier design

Low-pass filters (LPFs), 89–92differential, 98–99in lumped-element form, 90phase shift, 90phase shifter, 104RFIC, 225schematic diagram, 89, 91, 92simulated S-parameter, 91, 92

single-section, 91two-section, 92

MM1-to-M2 vias, 57Matching networks, 149–50

band-pass output, 150high-pass output, 149low-pass output, 149multistage amplifiers, 176, 178

Matching techniques, 105–6Maximum available gain (MAG), 105Metal insulator metal (MIM) capacitors,

6, 57–58cross section, 58layout, 57, 58simulator model, 59

Metal migration, 68, 69Metal-semiconductor field-effect transistors

(MESFETs)device gates, 4GaAs, 2, 3

Microstrip lines, 53–55ADS schematic symbol, 54coupled, 54cross section, 53electrically critical dimensions, 53formation, 53layouts, 54

Microwave circuits, 1Microwave monolithic integrated circuits

(MMICs), 3–4Mixers, 195–229

active, 200–217basics, 195–97cellular/PCS example, 221–29design, 195–229diode, 197–200double-balanced, 199downconverting, 33, 197as frequency-conversion device, 195fully balanced active multiplying, 205–17Gilbert cell, 30, 41I/Q, 217–19as nonlinear devices, 195output filtering, 197passive, 197–98power-series expression, 196schematic symbol, 195single-balanced, 198–99, 200–205upconverting, 31, 197

Mixing frequency, 197

312 Index

Multistage amplifiers, 173–93active device sizing, 177–81cascade of interstage matching networks,

178dc current requirements, 178dc power requirements, 180design procedure, 180–81differential PCS PA, 181–93gain allocation, 177interstage matching network, 176LNAs, 173–75loadline impedance, 179maximum power output, 176power allocation, 177power amplifiers, 175–76power output tracking, 179spreadsheets, 179, 180unit cell requirements, 180

NN dB compression point, 141Negative resistance, 248–51

power gain, 249resistance magnitude, 250start oscillation, 249symbolic diagram, 249

Negative-resistance oscillator circuits, 252–58common-base, 255, 256with Gummel Poon model, 254–55robustness, 258schematic diagram, 252simulated impedance, 256

Noiseflicker, 118, 119–20phase, 263–65shot, 118, 119, 121sources, 118thermal, 118, 119, 120–21white, 119

Noise figure (NF)calculation, 125concepts, 115–16conversion to noise temperature, 116–17Darlington amplifier, 160Darlington LNA, 129defined, 115Gilbert cell mixer, 216–17minimum, 121multistage contributions, 117–18PCS LNA, 128second-/third-stage contributions, 118spectrum, 119

Noise matching, 109Noise temperature, 116–17

conversion to/from noise figure, 116–17defined, 118

Nonlinear performance metrics, poweramplifiers, 141–45

Nonzero IF receivers, 32–37North American Digital Cellular (NADC), 15NPN HBT devices, 73, 75–76N-quadrature amplitude modulation

(N-QAM), 10, 32

OOIP3 requirements, 179Orthogonal frequency division multiplexing

(OFDM), 17multiband approach, 19subchannels, 18

PParasitics, minimizing, 284–85Passive circuit design, 89–104

band-pass filters, 93–95differential filters, 95–99high-pass filters, 93low-pass filters, 89–92phase shifters and baluns, 102–4splitters/dividers, 99–102technology and substrates, 99

Passive mixers, 197–98Passive structures

bonding pads, 60–61crossover capacitances, 61–62InGaP/GaAs HBT, 48–67M1-to-M2 vias, 57microstrip lines, 53–55MIM capacitors, 57–58SiGe HBT, 81–86significant layout parasitic elements, 65, 66spiral inductors, 62–64substrate vias, 58–60TFR resistors, 55–56transistor dummy cells, 64–65

PCM pattern layout, 291PCS LNA, 126–27

layout, 128noise figure, 128parallel feedback network, 127schematic diagram, 127simulated S-parameter, 128topology, 126–27

Index 313

PCS LNA (continued)See also Low-noise amplifiers (LNAs)

Phase modulations, 25–26BPSK, 26information rate, 26performance criteria, 25

Phase noise, 263–651/f, 279differential VCO, 277, 278ring oscillator, 273spectrum, 263thermal noise domination, 264upconverted 1/F, 265See also Noise

Phase shifters, 102–4differential LO, 225HPF schematic, 103LPF schematic, 104

Power amplifiers (PAs)adjacent channel power ratio (ACPR),

145–46bias circuits, 150–54circuit topologies, 147–48class A, 134, 138class AB, 134, 139–41class B, 134class C, 134class D, E, and F, 135classes, 134–35conversion efficiency, 133design, 133–71differential PCS, 181–93error vector magnitude (EVM), 146feedback, 164–71handset, 192loadline concepts, 134–36loadline resistance, 137, 139matching, 136matching circuit options, 149–50maximum gain, 135maximum power and efficiency, 136–39multistage, 175–76nonlinear performance metrics, 141–45OIP3 calculation, 143–44stability, 150supply voltage, 138two-tone intermodulation spectrum, 143wideband gain block Darlington, 154–64

Power dividers, 99–102impedances, 102resistive, 99, 100

Power splitters, 99–102

impedances, 102Wilkinson, 99, 100, 101

Process technology choices, 295–96Production costs, 298–99Prototype costs, 298Pseudomorphic films, 74P+ substrate, 82

QQuadrature phase-shifting networks, 266Quadrature phase-shift keying (QPSK), 17, 19

constellation diagram, 28defined, 27modulator block diagram, 28phase states, 27

RRadio frequency (RF) circuits, 1Ratio frequency integrated circuits (RFICs),

4–5applications, 10, 13–24CAD systems and, 286–87cellular handsets, 13–15cellular infrastructures, 15–16cellular/PCS downconverting, 221–29circuit elements, 6economics, 293–99heterojunction bipolar technologies, 10highly integrated, 6inductor elements, 62–63testability, 285–86WiMax and, 20See also RFIC architectures

ReceiversI/Q, 25–30nonzero IF, 32–37selectivity, 33superheterodyne, 33, 33–34, 34, 36WiFi, 38zero IF, 37–41

Resistive power dividers, 99, 100Reticle assembly, 289–92RFCMOS, 5RFIC architectures, 25–41

differential versus single-ended topologies,41

I/Q modulators, 30–32I/Q receivers, 25–30nonzero IF receivers, 32–37zero IF receivers, 37–41

314 Index

See also Ratio frequency integrated circuits(RFICs)

Ring oscillators, 267–72block diagram, 268measured power output, 272, 273measured S-parameters, 269, 270mechanical cross section, 271open-loop gain and phase, 269, 270simulated phase and amplitude noise, 273simulated power output, 272wideband Darlington amplifier, 268YIG-tuned filter, 268See also Voltage-controlled oscillators

(VCOs)

SScaled linearity, 144Scratch protection via (SPV), 60Selectivity, 33Series feedback, 165Set-top boxes, 20Shot noise, 118

collector, 121mean square current intensity, 120–21spectrum, 119as white noise source, 119See also Noise

SiGe, 9bipolar devices, 76epitaxial base layers, 73epitaxial concentration, 72foundry processes, 79maximum stable base thickness, 75thin films, 73, 74transistors, 72VCOs, 9

SiGe BiCMOS process, 83–86capacitor options with electrical parameters,

85capacitor simulator model, 83cross talk substrate coupling with, 87metal layer parameters, 84resistor options with electrical parameters,

85resistor simulator model, 83spiral inductor simulator model, 84varactor diode options, 86

SiGe HBT, 10, 71–87CAD layout, 86–87design rules, 86device evolution, 71device models, 79–81

dual heterojunction, 72extrinsic-base, 76fabrication technology, 71–87, 181GaAs/InGaP interconnect lines, 82passive structures, 81–86transistor structures, 71–78See also Heterojunction bipolar transistors

(HBTs)Signal-to-noise ratio (SNR), 14, 32Significant layout parasitic elements, 65, 66Single-balanced mixers, 198–99

active multiplying, 200–205bias tree layout, 204conversion gain, 205conversion loss, 204input power, 202isolations, 204layout, 203output spectrum, 204power conversion gain, 202schematic diagram, 201totem pole bias supply, 202transistor layout, 203waveform, 204See also Mixers

Single-ended topologies, 41, 294–95Spectral efficiency, 25Spectrum allocation, 21–22Spiral inductors, 62–64, 102

electrical model for simulation, 64layout, 64resonator elements, 63square spirals, 62–63

Splitters/dividers, 99–102Stability

in amplifier design, 107–9bipolar process, 297cascode amplifiers, 113Darlington amplifier, 164differential amplifiers, 111factor, 108frequency-temperature, 261–62power amplifiers (PAs), 150

Substrate vias, 58–60cross section, 60defined, 58layout, 59

Superheterodyne receiver, 33, 34double-conversion, 36downconversion process, 34single-conversion, 34

Surface-mount technology (SMT) inductors, 69

Index 315

TTechnology costs, 295–96Testability, 285–86TFR resistors, 55–56

cross section, 55, 56layout, 56simulator model, 56

Thermal noise, 118resistors, 120spectrum, 119thermal agitation, 120as white noise source, 119See also Noise

Thin film resistors. See TFR resistorsThird-generation (3G) cellular technology, 16Time domain multiple access (TDMA), 14,

15, 22Transistor dummy cells, 64–65Transistor structures

InGaP/GaAs HBT, 43–45SiGe HBT, 71–78

Traveling-wave tubes (TWTs), 1, 2, 3

UUltrahigh vacuum chemical vapor deposition

(UHV/CVD), 72Ultrawideband (UWB) transmission, 18–19

concept, 18–19EVM metric, 146physical layer standards, 23standards, 19as wireless USB standard, 18

Upconverting mixersblock diagram, 197Gilbert cell, 215, 216See also Downconverting mixers; Mixers

VVaractor diodes, 242–48

abrupt-junction, 243–48capacitance and resistance relationship, 244capacitance change, 245, 248doping profile, 244–45electric field behavior, 243frequency tuning curve, 246GaAs, 247at low reverse voltage, 244noise sources, 263space-charge density, 243structure, 242tuning, 280

voltage controllable, 242Varactor resonator, 275Varactor-tuned VCOs, 21, 267

differential, 280, 281negative-resistance, 278power output, 281schematic diagram, 280

VBIC model, 45–46dc IV curve generation, 48dc IV curve simulation, 49large-signal, 48S-parameter simulation, 49

Vertical Bipolar Industrial Committee(VBIC), 8

VGA saturation, 39–40, 41Voltage-controlled oscillators (VCOs),

6, 241–81biopolar technology design, 295design, 10, 241–81differential, 95, 272–78electronic tuning and, 279–81electronic tuning range, 265feedback circuit topologies, 252–61figure of merit (FOM), 278–79frequency-temperature stability, 261–62IC, 251low-phase-noise, 9negative-resistance, 278, 280negative-resistance concepts, 248–51phase noise, 263–65quadrature phase, 30quadrature phase-shifting networks, 266resonator types, 252RF circuits, 241ring oscillators, 267–72SiGe, 9tuning port, 241varactor diodes, 242–48varactor-tuned, 21, 267, 280–81

WWhite noise, 119Wideband gain block Darlington amplifier,

154–64WiFi, 16–17

Bluetooth standards and, 18equipment, 17EVM metric, 146OFDM modulation, 17physical layer standards, 23–24receivers, 38

Wilkinson power combiner/splitter, 99–102

316 Index

schematic diagram, 100S-parameters, 101

WiMax, 19–20Wireless local-area networks (WLANs), 16–17

YYIG-tuned oscillators (YTOs), 21

in Ku band, 267magnetic structure, 271negative-resistance-type circuit, 267output power simulation, 271

silicon bipolar transistors, 267Yttrium iron garnet (YIG), 241–42, 262

ZZero IF receivers, 37–41

block diagram, 37defined, 37disadvantages, 38effectiveness, 40See also Receivers

ZigBee, 23

Index 317