Designing an Operating System for a Heterogeneous Reconfigurable SoC

© imec 2003

Designing an Operating System for a Heterogeneous Reconfigurable SoC

Vincent Nollet,P. Coene, D. Verkest, S. Vernalde, R. Lauwereins

IMEC, Belgium

© imec 2003 Vincent Nollet – IMEC - RAW'03

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What is this all about ?

RTOSISP

+

Reconfigurable Logic

Create an Operating System that supports the use of Reconfigurable Logic.


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Outline

OS introductionWhat ? Why ? How ?

Related workWho ? What ?

OS support implemented in hardwareWhat ? Why ? How ?

Operating System componentsOperating System Structures

Inter-task Communication

Task Scheduling & Task Relocation

Kindergarten Components

Implementation details

Conclusions & future work


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Kindergarten components



Outline


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OS Introduction

What ?A management infrastructure that enables a system to handle multiple, concurrently executing heterogeneous applications

Why ?Heterogeneous applications should be able to benefit from the same OS abstractions/functionality as regular software applications

Managing the available computing resources

Providing a suited environment

How ?By extending an existing Operating System

RTOSISP Reconfigurable Logic

Hardware Abstraction Layer

OS for Reconfigurable Systems (OS4RS)


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Outline











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Related Work

Burns et al.Having a set of run-time support functions commonly used by all applications: reconfigure the FPGA, reserve a chunk of FPGA area and the ability to transform a circuit.

Wigley et al.Java based OS, linked to Xilinx JBits

Describe their fundamental OS services to manage the FPGA: resource allocation, application placement and routing

Simmler et al.Preemptive multitasking on FPGAs through bitstream manipulation

Controlled by “hardware manager software”

No use of Tetris-like circuit transformations

Use of hardware support to implement these services

Task preemption/relocation based on cooperative scheduling


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Outline











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What ?It is quite common for contemporary microprocessors to have built-in Operating System support.

Hardware support enables/facilitates certain OS functions

Why ?Facilitate/accelerate the basic FPGA management functions like resource allocation, task placement and routing

How ?By putting an extra layer of abstraction on top of the ‘bare FPGA’

OS support implemented in hardware

FPGA

Hardware Abstraction LayerHardware OS support structure

RTOS

ISP

OS4RS

InterConnection Network (ICN)


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OS support implemented in hardware

The Interconnection Network (ICN)

Source: T. Marescaux

On-FPGA packet switched network

Communication is done through the fixed ICN-Tile interface by means of message passing

Provides a number of fixed sized hardware tiles that can be reconfigured by means of partial reconfiguration

Communication is handled by ICN routers, controlled by routing tables provided by the Operating System


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Outline











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OS4RS Structures

Processor Information StructureRepresents an OS4RS computing resource (ISP, ICN Tile,…)

Allows the OS4RS to manage and monitor the computing resources

Enables support for Hot-Pluggable computing resources

Task information structure Required to store OS4RS information

List of available task representations

Info about the task state (e.g. assigned, relocating, …etc)

…etc

Linked to the processor-local task structure


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Global

task pool

OS4RS Task Scheduling

Task SchedulingTwo level scheduling

Top Scheduler is responsible for processor assignment

Processor local schedulers handle local temporal scheduling

ICN Tile1 task pool

ICN Tile1 local scheduler

ICN Tile2 task pool

ICN Tile2 local scheduler

ISP task pool

ISP local scheduler

Top Scheduler

ICN Tile1

One task only

ICN Tile2

One task only


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Heterogeneous Task Relocation

What ?Relocating a task at run-time from one type of processor to another one (e.g. from reconfigurable logic to ISP) with minimal interference

Why ?Optimal/Fair use of computing resources (e.g. according to a QoS)

How ?Cooperative scheduling by means of switchpoints (i.e. dedicated points of preemption inserted by the application designer).

FPGA

switch signal

OS4RS

switch

ISP


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Inter-task communication

Uniform Inter-Task CommunicationWhat ?

Uniform communication scheme for all tasks Based on message passing

Why ? Relocating a task should not affect communication Message passing is natively supported by the ICN

How ?

ISPP1

P2

PN FPGA

PA

PB

HAL

Communication API

PC

P3

OS4RS


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Application Binary InterfaceDescribes how a (binary) application gains access to the Operating System services

How can tasks running on the FPGA make a system call ?

How to incorporate and manage multiple binaries of the same task in a file ?

OS security ?Still a need to enforce the classic OS protection mechanisms

Allowing foreign hardware results in new security issues

The OS4RS should be more than just a hardware loader


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Outline











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OS4RS manages a proof-of-concept platform


StrongARM-1110 ISP

Xilinx Virtex II FPGA

OS4RS implementation detailsBuild as an extension to RTAI 24.1.9 for StrongARM

Extension that creates a RTOS underneath Linux

Minimal changes into RTAI (~ 150 lines source code)

OS4RS is build using several (Linux) modules

OS4RS core extensions are about 150kB

OS4RS task setup: ~108 ms (ICN tile) ~100 s (ISP)

The applications…3D game: two ISP tasks, one heterogeneous task.

Video decoding: two ISP tasks, one heterogeneous task.


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Outline











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And to conclude …

What we have …The Operating System for Reconfigurable Systems provides an environment where heterogeneous applications can execute concurrently, with minimal interference between them, but with support for inter-task communication.

Build as an extension to an existing OS

Heterogeneous task scheduling/relocation

Uniform inter-task communication

…the show goes on…Continue development on the present OS4RS modules

Raise the kindergarten modules

Heterogeneous task design issues

…

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Designing an Operating System for a Heterogeneous Reconfigurable SoC

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