1 1 Design Verification Mike Butts Synopsys Prof. Kurt Keutzer Dr. Serdar Tasiran EECS UC Berkeley Mike Butts Kurt Keutzer 2 Design Process Design : specify and enter the design intent Implement: refine the design through all phases Verify: verify the correctness of design and implementation
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Design Verification
Mike Butts
Synopsys
Prof. Kurt Keutzer
Dr. Serdar Tasiran
EECS
UC BerkeleyMike Butts
Kurt Keutzer 2
Design Process
Design : specify and enter the design intent
Implement:refine the design through all phases
Verify:verify the correctness of design and implementation
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Kurt Keutzer 3
Design Verification
RTLSynthesis
HDL
netlist
logicoptimization
netlist
Library/modulegenerators
physicaldesign
layout
manualdesign
specification
Is the design
consistentwith the originalspecification?
Is what I think I wantwhat I really want?
Kurt Keutzer 4
Implementation Verification
RTLSynthesis
HDL
netlist
logicoptimization
netlist
Library/modulegenerators
physicaldesign
layout
manualdesign
Is the implementation
consistentwith the originaldesign intent?
Is what I implemented
what Iwanted?
a
b
s
q0
1
d
clk
a
b
s
q0
1
d
clk
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Manufacture Verification (Test)
RTLSynthesis
HDL
netlist
logicoptimization
netlist
Library/modulegenerators
physicaldesign
layout
manualdesign
Is the manufactured
circuitconsistent
with the implemented
design?
Did theybuildwhat I
wanted?
a
b
s
q0
1
d
clk
a
b
s
q0
1
d
clk
Kurt Keutzer 6
Design Verification
RTLSynthesis
HDL
netlist
logicoptimization
netlist
Library/modulegenerators
physicaldesign
layout
manualdesign
specification
Is the design
consistentwith the originalspecification?
Is what I think I wantwhat I really want?
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Kurt Keutzer 7
Verification is an Industry-Wide Issue
Intel: Processor project verification: “Billions of generated vectors”“Our VHDL regression tests take 27 days to run. ”
Sun: Sparc project verification: Test suite ~1500 tests > 1 billion random simulation cycles“A server ranch ~1200 SPARC CPUs”
Bull: Simulation including PwrPC 604“Our simulations run at between 1-20 CPS.” “We need 100-1000 cps.”
Cyrix : An x86 related project“We need 50x Chronologic performance today.”“170 CPUs running simulations continuously”
Kodak: “hundreds of 3-4 hour RTL functional simulations”Xerox: “Simulation runtime occupies ~3 weeks of a design cycle”Ross: 125 Million Vector Regression tests
Design Teams are Desperate for Faster SimulationDesign Teams are Desperate for Faster Simulation
Kurt Keutzer 8
Verification Gap
1
Log
ic T
rans
isto
rs p
er C
hip
(K)
Prod
uctiv
ityT
rans
./Sta
ff -
Mo.
10
100
1,000
10,000
100,000
1,000,000
10,000,000
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000Logic Tr./ChipTr./S.M.
58%/Yr. compoundComplexity growth rate
21%/Yr. compoundProductivity growth rate
Source: SEMATECH19
81
1983
1985
1987
1989
1991
1993
1995
1997
1999
2003
2001
2005
2007
2009
xxx
x xx
x
2.5µ
.10µ
.35µVerification Gap
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logic_transistors
chipX
lines_in_design
logic_transistors
bugs
line_of_designX
=bugs
chip
Why the Gap?
Kurt Keutzer 10
logic_transistors
chipX
lines_of_design
logic_transistors
bugs
lines_of_designX
10,000,000 trs
chipX
1
10
1
10,000X
=100 bugs
chip
Filling in Reasonable Numbers
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logic_transistors
chipX
lines_of_design
logic_transistors
bugs
lines_of_designX
10,000,000 trs
chipX
1
100
1
10,000X
=10 bugs
chipthis year!!
Raising the Level of Abstraction
Kurt Keutzer 12
logic_transistors
chipX
lines_of_design
logic_transistors
bugs
lines_of_designX
100,000,000 trs
chipX
1
100
1
10,000X
=100 bugs
chipwithin 5 years!!
Moore’s Law Implies More Bugs
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The Verification Bottleneck
Verification problem grows even faster due to the
combination of increased gate count and increased vector count
1990
1996
2002
1M
100M
10B
100k 10M1M
10,0
00x
mor
e V
ecto
rsR
equi
red
to V
alid
ate
100 x 10,000 = 1 million times more Simulation Load
• Maintains schedules of events• Enables sub-cycle timing
Advantages
– Timing accuracy – Handles asynchronous
Disadvantage - performance and data management
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Event versus cycle-based simulation
ComboLogic
Q
QN
Ddata
clock
clock
clock
Q
QN
D
Q
QN
D
Event-Driven Simulator:• Simulates Function• Tracks event activities and timing
clock
data
Cycle Based Simulator:• Simulates Function• Accurate at Clock boundaries
data
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Software Simulation
– Application of simulation stimulus to model of circuit
Hardware Accelerated Simulation
– Use of special purpose hardware to accelerate simulation of circuit
Emulation
– Emulate actual circuit behavior - e.g. using FPGA’sRapid prototyping
– Create a prototype of actual hardwareFormal verification
– Model checking - verify properties relative to model
– Theorem proving - prove theorems regarding properties of a model
Approaches to Design Verification
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Gate-level Event-driven Sim Acceleration
HW implementation of gate-level event-driven algorithm
– Full timing, many states– Exploits low-level parallelism (pipelining)
Design partitioned for high-level parallelism
– Limited: irregular topology, event distribution
– Much work in the 1980’s: order 10X, not 100X
Performance
– 5G/eval * 100 MHz * 10 procs @ Max. 5Beps
– “7-25X HDL simulator”, “500 to 5K cps” (NSIM)
Usability
– Easy to use, quick compilation– Full timing and states
Event Detector
Event Scheduler
Primitive Evaluators
Netlist Fanout
Event Detector
Event Scheduler
Primitive Evaluators
Netlist Fanout
Event Interconnect
M. Butts - Synopsys
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Gate-level Event-driven Simulation Accelerator
Just one: Ikos NSIM
– 4-input table primitives, RTL synthesis front -ends– 8 to 64 processors, 0.5M to 15M gates
Value
– Much faster than unaccelerated simulators– Not quite fast enough to run much code on the design
Competition
– Modern compiled or cycle-based SW on standard multi-processor platforms
– Gate-level event-driven HW accelerator usually isn’t enough better
• Today’s GP multiprocessors exploit low and high-level parallelism
Conclusion: Limited future
M. Butts - Synopsys
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Gate-level Cycle-based Acceleration
Levelized compiled simulation in massively parallel hardware form
– All gates evaluate every cycle– No run-time data dependencies, so processors and IPC network
are scheduled at compile timeSevere design constraints
– No asynchronous feedback, latches, etc.– No timing: multiple related clock domains only by LCD slowdown– Commonly OK for microprocessors, much less so in general
Compilation
– Given design constraints, relatively easy to use– Fast: 2M gates per hour (CoBALT)
– Simulation farms have similar $/cycle/sec for regression vector sets
– FPGA-based rapid prototyping for validation, SW execution
Good solution for large projects that can afford it
Ultimately the basic concept is limited by IC packaging
M. Butts - Synopsys
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Software Simulation
– Application of simulation stimulus to model of circuit
Hardware Accelerated Simulation
– Use of special purpose hardware to accelerate simulation of circuit
Emulation
– Emulate actual circuit behavior - e.g. using FPGA’sRapid prototyping
– Create a prototype of actual hardwareFormal verification
– Model checking - verify properties relative to model
– Theorem proving - prove theorems regarding properties of a model
Approaches to Design Verification
Kurt Keutzer 42
Rapid System Prototyping Environment
Debug Environment
Aptix System Explorer™MP3C or MP4
Aptix System Explorer™ Development Software
Sun, HP
Ethernet
uu Need lowNeed low--cost, instrumentcost, instrument--like system prototyping environmentlike system prototyping environmentuu Must be wellMust be well--integrated into overall componentintegrated into overall component--based flowbased flow
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Rapid Prototyping of ASICs and SoCs
Target-specific tools
– ASIC/core+FPGA: Philips/VLSI Velocity, ARM ($5K)
Rapid prototyping is a rapidly growing verification technology
Do-it-Yourself: Get some FPGAs, build a prototype board
– Synopsys FPGA Compiler II accepts dc_shell scripts
– Synplicity/VeriBest Certify “RTL Prototyping”• Automatic partitioning of ASIC, synthesis into FPGAs, automatic PCB netlist
• “Gary Smith of Dataquest said the tool very likely will pose a threat to Aptixand may even ruffle feathers at Quickturn and Mentor.” -- EE Times 10/4/99
Rapid Prototyping of ASICs and SoCs
M. Butts - Synopsys
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Software Simulation
– Application of simulation stimulus to model of circuit
Hardware Accelerated Simulation
– Use of special purpose hardware to accelerate simulation of circuit
Emulation
– Emulate actual circuit behavior - e.g. using FPGA’sRapid prototyping
– Create a prototype of actual hardwareFormal verification
– Model checking - verify properties relative to model
– Theorem proving - prove theorems regarding properties of a model
Approaches to Design Verification
Kurt Keutzer 46
How to make it smarter: Intelligent Simulation
Simulationdriver
Simulationengine
Monitors
Symbolicsimulation
Coverageanalysis
Diagnosis ofunverifiedportions
Vectorgeneration
Conventional
Novel
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How to make it smarter: Intelligent Simulation
Simulationdriver
Simulationengine
Monitors
Symbolicsimulation
Coverageanalysis
Diagnosis ofunverifiedportions
Vectorgeneration
Conventional
Novel
CLOSED FEEDBACK LOOP
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Symbolic Simulation Simulationdriver
Simulationengine Monitors
Symbolicsimulation
Coverageanalysis
Diagnosis ofunverifiedportions
Vectorgeneration
IDEA: One symbolic run covers many runs with concrete values.
Some inputs driven with symbols instead of concrete values•2(# symbols) equivalent binary coverage
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Symbolic Simulation
INNOLOGIC:BDD-based symbolic Verilog simulators
l ESP-XV: For processor and networking applications
l ESP-CV: For memory verification and sequential equivalence checking
l Monitors can have symbolic expressions
l Can symbolize time, e.g., event occurring after time T, 10 < T < 20.
l If bug is found, computes actual values exercising it