Design, Simulation and Fabrication of a Self-Aiigned SiGe Base Heterojunction Bipolar Transistors For Low Power Operation A thesis submitted to the Faculty of Graàuate Studies and Raevfh In partial fulfiIlment of the requirtments for the degree of Master of Engineering in Electronics Ottawa-Carieton Institute for Mectrical and Computer Engineering Department of Electmnics, Faculty of Engineering Carleton University Otîawa, Ontario Canada June 1999 O AA Hussain 1999, Oîiawa, Canada
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Design, Simulation and Fabrication of
a Self-Aiigned SiGe Base Heterojunction Bipolar Transistors
For Low Power Operation
A thesis submitted to the
Faculty of Graàuate Studies and R a e v f h
In partial fulfiIlment of the requirtments for the degree of
Master of Engineering
in Electronics
Ottawa-Carieton Institute for Mectrical and Computer Engineering
Department of Electmnics, Faculty of Engineering
Carleton University
Otîawa, Ontario
Canada
June 1999
O AA Hussain 1999, Oîiawa, Canada
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This thesis describes the design, fabrication and electrical characterization of a novel
self-aligned SiGe base heterojunction bipolar transistor optimized for low-power
operation. A theoretical analysis is presented reveahg that the exnitter-base junction
capacitance dominates F, in this operathg regime. Guided by this initiai analytic
modeuing, the device simulator BIPOLE3 was used to optimize doping profiles and other
structurai parameters. A @ed Ge profile with a peak Ge content of 10% was assumecl.
Relatively light base and collecter doping is required to optimize low power performance.
Experimental devices were fabricated by modiving an existing commercial process flow
for silicon BJTs. New process modules were developed for field polysiliwn formation,
SiGe base deposition, and local intercomect formation. The SiGe base was formed by a
UHVKVD process. EIectricai test r d t s on the fmt expeimental devices are very
encouraging. DC characteristics are generally goai, although F, is approxirnately 3096
lower than predicted by BIPOLE3.
Acknowledgements
1 wish to convey sincere and deep appreciation to my thesis supervisor Dr. N.G. Tarr for
his encouragement, support and for many helpful discussions and suggestions during the
course of this work.
1 would also iike to thank the technical staff of the fabrication laboratory at Carleton
University: Mr. Lyaii Bemdt for wafer diffusiodannealing praiessing; Mrs. Carol Adams
for wafer pre-diffusion cleaning: Mr. Christopher Pawlowicz for direct write electron-
beam iithography and etchmg. I would also like to express my gratitude to the professors,
technical staff and students at the department of electronics for their help during the
course of this work Special thanks to Dr. DJ. Walkley for several consultations and help
with difficulties 1 encomterd
Many mernbers of the technical staff at Gemum Corporation certainly deseme
recognition for their help and consultations: Mr. Andrew Cervin-Lawry for his
supervision during the layout of the devices and fabrication; Mrs. Myriam Buchbinder for
her help during fabrication and valuable comments: Dr. J. Kendall for AC measurements
and useful discussions, and Mrs. W. Gustafson for wafer processing. Special thanks goes
to Mr. D. Lynch for his valuable suggestions during the weekly meetings at Gennum.
Most irnportantly, I am deeply indebted to my forbearing wife and children, especially
my daughter Berak and my son Belai during the preparation of this thesis. This work is
dedicated to them.
Finally, I would like to thank, the department of Electronics at Carleton University,
OSAP from the Ministry of Education and Training, Gerinum Corporation of Buriingüm,
Ontario and Micronet for their financial support. 1 extend my thanks to the Canadian
Marconi Company for their bursaries.
Table of Contents
Abstract Acknowledgemcnts Table of Contents List of Figures List of Tables List of Symbols
CHAPTER 1. : INTRODUCTION
1.1 Basics of SiGe HBT Technology 1.2 Objective of the Present Work
CHAPTER 2. : SiGe HBT PHYSICS AND TECHNOLOGY
2.1 Physics of the SiGe HBT 2.2 Growth of SiGe on Si Substrate 2.3 The UHV/CVD Process 2.4 Surface Cleaning 2.5 SiGe Film Growth 2.6 Polycrystalline Silicon 2.7 Transit Times in Bipolar Transistors 2.7.1 One-Dimensional (Vertical) Anaiy sis 2.7.2 Two-Dimensional (Lateral) Analysis
CHAPTER 3, : DEVICE ARCHITECTURE
3.1 Transistor Structures 3.2 Device Layout
CHAPTER 4, : DEVlCE SIMULATIONS AND ANALYSIS
4.1 Introduction 4.2 Electrical Performance Specifications 4.3 Calculation of the Extrinsic Base of the NSA Devices
4.3.1 Model 1 (Overestimates Base Resistance) 4.3.2 Model 2 (Undereshates Base Resistance)
4.4 Delay Times Contributing to the Transition Frequency 4.4.1 Prebinary Calculations 4.4.2 Simulation Results
iv v
vi viii
X
xii
4.4.2.1 Effect of Doping Levels on the Delay Times 4.4.2.1.1 Vertical Analysis 4.4.2.1.2 Lateral Analysis
4.4.2.2 Effect of Transistor Size on the Delay Times 4.4.2.2.1 Vertical Analysis 4.4.2.2-2 Lateral Analysis
4.5 Effect of Doping Levels on the Elecaical Characteristics 4.5.1 Emitter Doping Level 4.5.2 Epitaxial Collecter Doping Level
4.6 Influence of Device Scaling on the Electricai Characteristics 4.7 Simulation Results of an Si-Base Device 4.8 General Tram is tor Characteristics
CHAPTER 5.: DEVICE FABRICATION AND CHARACTERIZATION 69
5.1 Introduction 5.2 Test Wafer Layout 5.3 Short Loop Experirnents 5.4 Field Poly Module 5.5 SiGe Base Deposition Module 5.6 Local Intercomect Module 5.7 Rapid Thermal Emitter Annealing 5.8 Device Characteristics and Discussion
5.8.1 DC Characteristics 5.8.2 AC Characteristics
CHAPTER 6. : CONCLUSIONS AND RECOMMENIDATIONS 96
6.1 Conclusions 6.2 Recomrnendations For Future Work
APPENDIX A. : 102
A. 1 The pn OneSided Step Junction A.2 Depletion Layer Capacitance
APPENDIX B. : 104
B.1 Tables 104
vii
List of Figures
Figure
2.1
2.2
3.1
3.2
3.3
3-4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5.1
5.2
5.3
a:Energy band diagrams of a Si bipolar transistor (solid line)
and SiGe HBT (dotîed Line). b:Doping profde of Ge across
the base region
Representation of the strained and relaxed structures of SiGe
on Si substrate
Cross-sectional view of the self-aiigned HBT structure
Cross-sectionai view of the non-self aligned HBT structure
Self-aligned HBT with twO base contacts
Non-self aligned HBT with two base contacts
Extrinsic base cross-section
Model 1 for the NSA device
Model 2 for the NSA device
Typical simulated impurity profile for SAlX and NSAlX of
SiGe HBT
Typical simulated Gurnmel plots of base and coiiector currents
for SA1 X and NSAlX of SiGe HBT
Typical simulated &-Va characteristics for SAlX and NSAlX
of SiGe HBT
Simulated F, and Fm as a function of I, for SiGe HBT
Schematic cross-section of the field poly process sequene
of the SiGe HBT
Schematic cross-section of the SiGe process sequence
of the SiGe HBT
Schematic cross-section of the LOC-DIT proces sequence
of the SiGe HBT
vüi
Experimental collector and base curtents versus base-emitter
bias for the SiGe HBT 91
Experimental coiiector current versus esnitter-collecter bias
for different base c m n t s for the SiGe HBT 92
Measured transition frequency versus collector currents for
a SiGe HBT 94
Table
4.1
4.2
5.1
5.2
B.l Partl
B. 1 Part2
B.2 Partl
B.2 Part2
B.3 fart1
B.3 Part2
Description
Mask dimensions of the vertical SiGe riBTs
Effect of doping Ievels on the delay times obtained from
vertical anaiysis
Effect of doping leveis on the delay times obtained from
lateral andysis
Effect of a tramistor size on the delay h e s obtained from
vertical anaiysis
Effect of a transistor size on the delay tirnes obtained from
lateral analysis
Heavy emitter doping
Light emitîer doping
Light emitter doping, light EPI doping
Heavy emitîer doping, Iight EPI doping
Delay times for Si-base devices obtauled from vertical
andysis
Delay thes for Si-base devices obtained from lateral
analysis
Summary of the field poly results
Variation of sheet resistance with temperature
Heavy emitter doping, various geometries
Heavy ernitîer doping, various geometries
Light ernitter doping, various geometries
Light emitter doping, various geometries
Light ernitter doping, Iight EPI doping, various geometries
Light emitter doping, Light EPI doping, various geometries
Heavy ernitter doping, light EPI, various geometries
List of symbols
Base-cokctor junction area
Emitter-base junction area
CoUector-emitter breakdown voltage
Diffusion capacitance
Base-coilector junction capacitance
Emitter-base junction capacitance
Substrate capacitance
Electron diffusion constant in the base
Barrier height at a heterojunction
Band gap grading across the neutral base region
Band gap reduction at the emitter-base depietion edge
Band gap reduction at the base-coUector depletion edge
Epitaxial coiiector layer
Grading coefficient
Maximum osciUation frequency
Peak value of the maximum oscillation frequency
Transition tkequency
Peak value of the transition frequency
Transition frequency for Si-base
Transition frequency for SiGe-base
Grading factor
Tramconductance
Base current
Colleetor current
Value of wiiector current giving highest F,
Integrated circuits
Coiiector current density
Boltzmann constant
Ionized acceptor dopant concentration
Effective density of states in conduction band
Ionized donor dopant concentration
Intrinsic canier concentration
Effective density of states in valence band
Electronic charge
Total base resistance
Intrinsic base resistance
Extrinsic base resistance
Undepieted dector resistor
Vertical resistance under the collecter contact
Diffusion resistance
Sheet resistance
Absolute temperature
Epitaxial layer thickness
Delay time due to sidewail injection electron concentration into the base
region outside the active base region
Smail signal delay t h e due to integral of rninoriy carrier charge in the
whole of active region
Base-transit time
Transit t h e for Si-base
Transit time for SiGe-base
Time constant for charging the base-coiiector capaciwce through the
collecter resistance
Basecoiiector junction capacitance charging t h e
Neutrai emitter region charging t h e
xiii
Emitter-base junction chargkg time
Emitter to collecter transit time
Delay time due to minority carrier charge in the emitter-base space charge
layer
Oxide thickness
Heatpulse preset temperatwe
Delay time due to free camer charge in emitter-base space-charge layer
Delay the due to C,= and total series resistance
Delay time due to (kT/q)(CE+CJc)
Collector space charge layer transit cime
Delay tirne due to (C, u p ) Total delay tirne in a tarodimensional analysis
W afer temperame
b l y voltage
Early voltage for Si-base
Early voltage for SiGe-base
Base-collecter voltage
Bdt-in voltage at the base-coilector region
Built-in voltage at the emiüer-base region
Themal voltage
Collecter-emitter voltage
Emitîer-base voltage
Saturateci carrier velocity
Emi tter deph
Collector depletion width
Width of the exnitter-base junction
Metallurigical junction depth at the emitter-base region
Metallurigical juaction depth at the base-collecter region
Permittivity of free space
xiv
Penniîtivity of siiicon
Current gain
Ratio of the position-average density of States product (N, N,) berneen
SiGe-base and Si-base transistors
Base-collecter junction coefficient constant
Emitser-base junction coeffkient wnstant
Wafer sheet resistance
Ratio of the position-average minority carrier mobility in the base of a
SiGe HBT compared to a Si BJT
CHAPTER 1
INTRODUCTION
1.1 Basics of SiGe HBT TechnoIogy
Silicon bipolar transistor technology is abwt a haif century old. For the past five decads,
the speed of silicon bipolar junction transistors (BJTs) has gradually increased as a result
of the decrease in their dimensions. Whether siliwn devices have reached theoretical
lirnits or not, the introduction of SiGe devices illustrates a discontinuity on the path to
faster siiicon [Il. Scientists and engineers at severai institutions [l-31 have been studying
new semiconductor materials for many years. One direction in these studies was to add
srna11 amounts of germanium (Ge) to silicon in order to create a new stable aUoy (Si,.,
G c , where x represents the mole fraction, often writîen SiGe for simplicity). This
material is of considerable interest as it offers the potential to deiiver impmved
performance compared to the conventional si!kru! divices.
The introduction of SiGe into conventional Si technology has attracted much attention
because of the potential to obtain high device perfomance at low cost for many
applications such as optical and WireLess communication system, I d area networks and
high speed digital circuits. High transition frequencies, F,, high maximum oscillation
frequencies Fm and high current gains can be achieved using SiGe heterojunction bipoiar
transistors (KBTs) raîher than Si BJTs. Additional benefits such as bigher Early voltages
and lower sheet resistance can also be achieved when SiGe is introduced in the base of
the transistor. These high performance devices are ideal for meeting the requkements of
the high-speed analog circuits required for RF and microwave applications [4,5].
Several groups have reported the transistor transition frequencies of SiGe-HBTs in excess
of 100 GHz [6-81 with graded, narrow bases. Firnhermote, the maximum oscillation
frequency was increased to 160 GHz by minimizing both the total base resistance RB and
base-coLlector junction capacitance C,, [9]. Minimizing RB and C , is crucial to
mawimizing the Fm. Until recently, these performance levels were only achievable with
the most advanced GaAs technology.
Transistors that are built in silicon gexmanium can run substantiaily faster than their pure
silicon counterparts, and can be made at lower cost with greater opportunity for
integration with standard Si processes than can high speed GaAs devices. GalLium
arsenide processes exhibit excellent performance characteristics but suffer fmm higher
pricing resulting from higher wafer costs, plus costs for epitaxy material and low device
yields. SiGe opens the door to merging logic and RF on one die. and thus cornpetes
favorably with GaAs in performance across the range of frequencies where GaAs is now
dominant. That merger stems from SiGe's ability to let bipolar and CMOS coexist on a
single silicon wafer [IO].
Adding Ge to the base of the transistor influences the band gap energy, band
2
discontinuities, scattering processes d electron-hole recombination processes. Ge
reduces the band gap, lowering the barrier for electron injection into the base, which in
tum aliows heavier base doping to be used, lowering base resistance. Band gap grading
introduces a drift field to aid the transport of electrons across the neutrai base. The
electron mobility in SiGe is about two to three times higher than that in pure Si, allowing
more rapid electron transport across the base.
SiGe has the same crystallographic stn~cture as Si [3] but its latrice constant is larger by
about 4% for pure Ge. When SiGe is grown epitaxiaily on Si substrate in such a way that
the film and substrate adopt a cornmon lattice constant while maintaining perfect
crystailinity across the growth interface* the composite film undergoes strain. One
immediate concem is the effect of s h e d - l a y e r epitaxy . For any given Ge content, there
is a critical thickness of SiGe above which starts to relax toward its bulk latîice spacing
and can generate defects which can devastate device perfomance. One possible solution
to this problem is to prepare SiGe using ultra-high vacuum chernical vapor deposition
UHV/CVD at relatively low temperature. This technique, which was developed by
Meyerson and his coworkers (11 at IBM, was pmven to be a successful technique to
overcoming the above mentioned difficulties. This issue and related ones will be
addressed in chapter two.
1.2 Objective of the -nt Work
The main objective of this thesis is the design, simulation and fabrication of a vertical
3
SiGe base heterojunction bipolar transistor optimized for low power operation. While
previous researchers have concentrated on maximizing the speed of SiGe HBTs
irrespective of power co~lsumption, this wotk attempts to utilize the SiGe base to enhance
performance at low power levels. To realize the goal of high speed operation at low
power, a novel self-aligned device stmcture is introduced.
The work describeci hem is collaborative with Gennum Corporation of Burlington.
Ontario. In partîcuiar, the novel self-aligned SiGe base device was developed by
modifying an existing commercial process developed at Gennum. The author's
contri'bution to the project included design of optimum doping and composition p r o f i
for the new device using the BIPOLE3 slmilaîor, modification of an existing L-Edit
layout environment to include the new layers requirrd for SiGe devices, design of a suite
of test transistors, and development of several key process techniques related to SiGe
base formation, and analysis of electrical characteristics of completed devices. Most
device processing was carried out at Gennum, with some key steps completed at the
National Research Councii and Carleton University. To pmtect the co~~llllercid interests
of Gemurn, no details are given here on îhe baseline proces on which the SiGe base is
grafted-
The thesis is organized as follows. In chapter 2, a bnef introduction to SiGe HBT
technology and theoretical background are given. Chapter 3 presents device architectures.
BIPOLE3 simulation results are presened in chapter 4. In chapter 5, details of the new
developed process flow, fabrication techniques and electrical characterization results for
cornpleted devices are presented. nie conclusions of this study are presented in chapter 6.
CHAPTER 2
SiGe HBT PHYSICS AND TECHNOLOGY
2.1 Physics of the SiGe HBT
The advantage of the SiGe heterojunction bipolar transistor (HBT) lies in the ability to
modify the band gap of ordinary silicon serniconductor material for higher performance.
Band gap engineering is a powerfd tool used for creating faster transistors. Conventional
silicon devices have an effectively fi& band gap of 1.12 eV which b i t s switching
speed, compareci to HBTs fabricated on III-V compound materiab such as GaAs. With
the addition and gnding of the Ge (which has an energy gap of 0.66 eV [Il])
concentration across the base region of a BJT, it is possible to modify the band gap and
consequentl y enhance the performance of the silicon transistor.
The main difference between the SiGe HBT and Si BST is iiiustrated in the energy band
diagram of Fig.2.la of a linearly graded Ge doping profde in Fig.2.lb (121. Figure 2. l a
shows schematic energy band diagrams of Si BIT (soiid iine) and SiGe HBT (dottecl he)
showing a band gap modification [12]. aE, is the band gap difference between Si and
SiGe: ~ S ~ ~ ( x = û ) and nE,,(x=WJ represents the amount of band gap reduction at the
eminer-base and base-cuiiector depletion edges in the neu id base, respectively.
aE,,@de) = AE~,,(X=WJ - aE,,(x=û) represents the band gap grading aaoss the
Base
Figure 2.1 a: Energy band diagrarns of a Si bipolar transistor (solid Line) and SiGe HBT (dotted line). b: Doping profie of Ge across the base region [ l t ]
neutral base region. This band gap grading introduced into the base region of a SiGe HBT
induces a drift field which aids minority carrier transport through the base, d t i n g in
higher frequency operation [12]. This means that the base band gap of SiGe HBTs can be
engineered to enhance device performance? thereby making it suitable for a wide range of
high speed analog and RF applications. Harame et al [12] fomd in SiGe HBTs. the Ge
introduced into the base region duces the base band gap by about 75 meV per 10% Ge
compared to a Si BJT. Ii is this reduced band gap of SiGe strained layers cornpanxi to Si
that is directly exploited in the SiGe heterojunction bipolar transistor. The aE, is
detennined not only by the Ge concentration but dso by the saain creaîed between the
SiGe and Si substratet For identically constructeci devices, the ratio of the current gain P
between a SiGe HBT and Si BIT is given by [12],
a ratio which is larger than unity for finite Ge content. q represents the ratio of the
position-averaged minonty Camer mobility in the base region of a SiGe HBT compared
to a Si BTT, y represents the ratio of position-averaged density of states pduc t ( N, N,)
between the two transistor^, k is B o l t z m a ~ constant, and T is the absolute temperature.
Equation 2.1 indicates that the smaiier base band gap in a SiGe HBT exponentially
increases the number of minority carriers injected into the base, causing an increase in the
coiiector current for the same forward-bias.
As mentioned above, quaiitatively, the grading of the Ge a t m actoss the quasi-neutral
base induces a drift-field in the base which accelerates the electrons injected from the
emitter to the collecter, thereby decreasing the base transit time wmpared to a Si BJT.
Harame et al [12] found for a constant base doping and using the theoretical equation
derived by Kroemer [13] for the base transit time, the ratio of base transit tirne for SiGe
kt:*) and Si (s,,) devices is
which, for finite Ge grading, is les than unity, and thus enhances the transition frequency
F, . Since the basetransit time s, is usually a major component in the F, equation,
An additional benefit of using a graded-Ge profile in a SiGe HBT is an enhancement in
the Early voltage VA - a measure of ease with which the majonty d e r profile in the
base is depleted by an applied base-coiiector bias. Rinz and Sturm [14] developed an
anaïytical mode1 to explain the higher values of the product PV, in Si/SiGe/Si HBTs. The
output conductance (Iience & y voltage) is a rneasure of how much the neutral base
profde can be depleted with reverse bias on the collecter-base junction, and is manifested
in the rise of the coliector current density Jc with collecter bias at fixed base-emitter
voltage. The ratio of Eariy voltage in the SiGe HBT to that of the Si BJT is given by 113)
Equation 2.4 indicates that for f i t e grading across the quasi-neutral base, the
exponential dominates the hmctional dependence on Ge content, and the d o in eq.2.4 is
larger than unity. yieldmg an improvement for a SiGe HBT comparai to a Si BJT. In
other words, the base region becornes harder to deplete than for the comparably doped
silicon transistor. Large Early voltage means the transistor has high output resistance,
which is useful for analog design applications such as RF communications.
From the above discussion, we can see that p, F, and VA are increased significantly when
SiGe is htroduced in the base region of the HBT, and this leads to improvernent in the
device performance.
High transition frequency F, and high oscillation frequency Fm are simultaneously
requued for both digital and analog ICs. The reiationship between F, and Fm is given by
IlSI,
F, = [ F, 1(8 x RB CJ3J", (2.5)
where RB is the total base resistance and Crc is the collecter-base capacitance. SiGe HBTs
have high Fm comparai to Si BJTs since the base in the former transistors can be heaviiy
doped whüe maintainhg a high injection efficiency due to the band gap difference
between silicon and strained SiGe. This means that the high current gain in the SiGe base
of the HBT can be traded off for higher base doping without comprornising device
performance.
2.2 Growth of SiGe on Si Substrate
The nature of the crystal stmcture resulting from the growth of SiGe on the Si &strate
9
plays an important role on the device performance. There is a mismatch between the
lattice constant of the Ge (5.658 A) and Si (5.431 A) (16). which is equal to about 4%. As
a result of the mismatch between the lattice of the SiGe f i h and Si substrate, two
distinct classes of growth are possible: pseudomorphic growth and dislocated growth.
Figure 2.2 shows two dimensional representations of the two classes of growths inchding
the Si substrate and the relaxeci SiGe layer. Below is a qualitative description of the such
growths, and the details can be found in several references [l, 17,181.
In class one pseudomorphic (incornensurate) growth, a compressive strain will be
developed as a result of the lanice mismatch between the epitaxial SiGe and the Si
substrate. Consequently, the la& constant of the SiGe wiii be tetragonaliy rlistorted, to
match the in-plane la& constant as shown in Fig.2.2~. Pseudomorghic growth of SiGe
on Si can continw for a thickness determined primarily by the mismatch of the relaxed
lattice constants of the SiGe and Si, and the substrate temperature. If the SiGe thickness
exceeds a cenain value or the substrate is exposed to sufficiently high temperatures for
long p e n d of tirne, at which the pseudornorphically grown layer is no longer
thermodynamically stable, the iattice constant relaxes to its original value. This means
that the strain in the SiGe layer wiii be relaxed and misfit dislocations will form at the
interface between the silicon and SiGe, as illustrateci in Fig.2.U. One disadvantage of the
shain relaxation in hetemjunction bipolar transistors is that it lowers the band gap
difference between the Si and SiGe resuiting in a degradation in injection efficiency and a
reduction in current gain. as iiiustrated in eq.2.1. Also misfit dislocations that acmmpany
10
(a) Si- Substraie (b) Reiaxed SiGe
Relaxcd SiGe
Misfit dislocation
Fig.2.2 Representation of the strained and relaxed structures of SiGe on Si substrate
strain relaxation can lead to leakage andor recombination at the interfaces where there
are a hi@ density of dislocations [19].
It appears from the above discussion that the SiGe strained layer is thennodynamidly
stable to the formation of unwanted film defects only when the Ge content is kept below a
specific upper bound Increasing the Ge content will decrease the critical thickness of the
SiGe. Shce Ge is rquired oniy in the base region of the transistors, and since many of
the pmperties of bipolar transistors depend exponentially on changes in the band gap,
only a small Ge conceutration is required. In the present work a maximum concentration
of 10% will be used during formation of the transistor base. This means that SiGe
stability constraints are satisfied in the fabricated devices. Since the base thickness is l e s
than lûûû A, the devices are stable under îhe Mathews-Blakeslees criterion [20].
2.3 The UHV/CVD Pmxss
SiGe alloy layers tnay be grown on Si epitaxially by severai techniques [121-24) that
compte in terms of cost, ease of thickness and dopant control, flexibility, scalability and
contamination by impurities. The most common ones are molecular bearn epiiaxy (MBE),
low pressure chernicd vapor deposition (LPCVD), atmoapheric pressure and dtra-
high vacuum chernical vapor deposition (UHV/CVD). The challenge of p w i n g SiGe
ailoys is currentiy met by ail of the above-mentioned methods, with UHVKVD king the
most widely used and the most amenable to high-volume production. This technique was
fmt demonstrated by Meyerson [21]. More specifically, Meyenon and CO-workers at
12
IBM [Il combined the ultra-high vacuum of MBE and a conventional CVD process by
exploiting the role of hydrogen in teguiaihg the chemistry at the Si and SiGe growth
interface.
The UHV/<ND developed by Meyerson 11,211 offers several advantages over other
g r o h techniques, such as low temperature ( 4 5 0 O C ) deposition, in siîu ptype doping,
highiy precise film thickness, composition and dopant concentration profiles that can be
produced of almost hitrary abruptness. The result has k e n the ability to produce a hi@
performance SiGe hetemjmction bipolar transistor.
2.4 Swf'ace Cleaning
The UHV/CVD technique is dependent on a simpk yet vitally important s d a c e cfeaning
and preparation procedure to avoid the growth of native oxide which would hterfere with
epitaxy. Fuli details on this clearting technique have been given elsewhere [1.22]. The
technique relies on hydrogen passivation of the bare silicon surface. This passivation is
accomplished by irnrnersing the substrates in diiute hydrofluric acid and then removing
them without any subsequent rinse. Photoemission spectroscopy studies [25] shows that
HF etching renders the silicon surface passive, free of oxide, and stabiiized by the
presence of a layer of chernisorbecl atomic hydrogen. The hydmgen adlayer formed by an
HF dip reduces the reactivity of water vapor Mth the silicon surface by ppproximately
thirteen orders of magnitude [1,25]. The hydrogen adlayer acts as a chernical banier to
recontamination. This means that in UHV/CVD there is no "native oxide" to be removeci
13
from a siIicon surface prior to epitaxial growth, provided the temperature/time history of
the load sequence prevents hydrogen desorption until growth is initiated.
2.5 SiGe F i Growth
After the Si wafer surfaces wefe hydrogen passivated, they were placed in a quartz wafer
boat and inserted into the load lock chamber, which is pumped to below lx104 torr [l]. A
hydrogen flow at a corresponâing pressure in excess of 200 mtorr was used during wafer
boat transfer into the main chamber. This prevents the cross-contamination resulting from
residual gas in the load chamber. Hydrogen flows terminated when the main chamber was
isolated from the load chamber. Growth is then initiateci imrnediately. Gaseous sources
employed are silane (SiHJ, gemume (GeHJ and diborane (BZH& using helium as a
diluent of dopants to produce films of desired chernical content. Deposition of SiGe
ailoys is perfomed at a temperature of about 525 O C and a total operathg pressure of 1.0
mtorr. With appropriate control and rapid pumping of the gas mixture mentioned above,
high quality of SiGe with a e . W o chernical uniformity and film thickness b e r than
Il . W o have been demonsErated [1,25].
2.6 Polycrystalline Silicon
Polycrystalline silicon (polysiiicon) is an important material in integrated circuit
technology, because of its high-temperature compatibüity with single-crystal Si and its
semiconducting pmperties. For almost three decades, polysilicon has ben used in metai
oxide serniconductor and bipolar technologies [26,27]. It may be used as the gate in MOS
14
devices, as the emitîer, base contact or collecter contact in bipolar junction transistors,
and also in onchip resistors and capacitors, and interconnect Lines [26-291. In bipolar
transistors using polysilicon emitter contact technology, control of the interface between
polysilicon and a siliwn substrate is one of the key parameters to insure repeatability
performance [30].
Polysilicon is so usefui because it foms an adherent oxide, absorbs and re-emits dopants,
has good step coverage if depsiteci by CVD. matches mechanical propetth of Si single
crystai. is compatible with HF, and many other properties, which are beyond the scope of
the present work. These properties make polysilicon uniquely suited to be a prirnary local
intercomect material, and its ability to fom silicides extends that application to longer
intercomect lines. In the present work the polysilicon wiU be used to form the emitter of
both the self-aligned and non-self aligned HBT. and the external base for the non-self
aligned HBT. Another advantage of the polysilicon in the present work, is to protect the
field isolation from HF attack during the passivation process.
2.7 Traasit T i in Bipolar Transistors
2.7.1 One-Dimensional (Vertical) halysis
The figure of merit cornmonly used to characterize the high-frequency behavior of a
bipolar transistor is the cut-off or transition frequency Fr This is the frequency at which
the transistor incrernental current gain drops to imity. The tocal transit time, t,, from the
emitter contact to the coliector contact of the onedimensionai bipolar transistor is related
15
to the transition frequency by [15,16].
F, = 1/(2.rc r,),
t, is made up of six deiay components conespondhg to different regions of the
transistor. The physical formula of each component is given as foiiows [15,16].
1. Neutml e m i w region chargrirg time T,
where W, and Wb are the emitter depth and neural base width respectively, F, is a
grading coefficient (typically between 1 and 5). and D,, is the elecûm diffusion constant
in the base.
2. EmmLtter-basejunciion chargihg time t,
This is the deiay t h e due to emitter-base junction capacitance, Cm times the 'diffusioli
resistance' r, (=l/&. where is the transconductance, g, = & NT, where I, and V, are
collector current and thermal voltage respectively),
3. me-transit tirne t,
For a Si device having uniforni doping, simple theory [31,32] predicts that for a given
base width, rb is given by
According to eq.2.2, there is a drift field resuiting from the grading of the Ge across the
quasi-neutrai base. This means that the first term of eq.(2.9a) shouid be multiplieci by
such a grading factor G,, in this case eq.(2.9a) should be read as,
canier velocity and the rernaining parameters have their usual meaning.
I, =200@ XJ, = 0.05 pm SV, = 7.5 V Vk = 1.0 V XJ2=0.1359 un SVh = 19.2 V ED = 3.0 x1O2' Wb = 0.045 p Reach through = 1.92 V BD = 1.0 x10 l8 cm-3 TEP1 = 0.59 pm Ge =IO% EPI = 1.0~10 l6 cm'3
* Underestimates base resistance
Parameters
F, (GHz)
Fm (GHz)
Rb (a) Rbex <a> CE (fF)
CJC (fF)
C,, (fF)
(m, (GB)
(F,), (GHz)
O p (PA)
P
+ Si-base doping profdes: ED = 3.0 xlOm cm" XIl = 0.05 pm SV,, = 9.6 V BD = 4.0 x10 l8 cm3 XJ2 =0.1398 pm SV,, = 21.0 V EPI =1.0 x1016 cme3 Wb = 0.07 pm Reach through = 4.19 V
TEPI=O.59 pm
SAlX SiGe
18
23
190
250
20
2.99
12.3
21.9
25.9
331
841
NSAlX SiGe
18
14.5, 17.1*
190
1300,dOW
20
2.99
12.3
21.9
16.1, 19.W
331
841
SA1X' Si
14.1 1
17.4
620
150
17.93
2. 9
10.8
17
20-3
597
127
(2) There is an appmiable increase in the Fm of the NSA devices due to the change in iîs
main components, CJc and the total base resistance (%+L). The decrease in the base-
collecter capacitance CJc can be amibuted to the increase in the depletion Mdih at the
coilector junction X, The increase in the total base resistance (%+L) of the NSA
devices is expected. It starts from the edge of the emitter poly and extends above the field
oxide up to the base contact.
(3) The breakdown voltage BV, is sispificantly increased from 5.7 V to 7.5 V, whereas*
the reach through voltage is decreased from 4.79 V to 1.92 V as a result of the decreasing
in the doping level of the EPI layer. Wolf [41] indiateci that when the epitaxiai layer
thickness is too small, under increasing reverse-bias voltage the depletion region of the
C-B junction wiil entirely penetrate the epitaxial layer before the predicted BV, voltage
has been reached. If the voltage is increased beyond this point, the depletion region must
enter the heavily doped buried layer, resulting in BV,, values smaller than those
predicted merely by the doping in the EPI layer.
(4) The percentage of the increase and decrease in the F,. Fm, P and other transistor
parameters fluctuating from one transistor to another depends mainly on the size of the
transistor. The most sensitive areas which affect the performance of the device are the
length and width of the field poly and the length and width of the emitter stripe mask.
Table B.2 (Appendix B) indicates that when there dimensions becorne smaller, the
performance of the device improves. because the parasitic capacitances and r e s i s m
54
are reduced. Furthermore, the mail geometq devices may nm at higher nirrent density
for a given collecter m e n t .
Table 4.9 shows another doping profile, where the doping levels in the coilector and the
base are similar to that presented in Table 4.8 except the doping level in the emitter was
increased from 3.0x1@'/crn3 to 6.0x1@%m3. The simulation results indicated that the
performance of the devices shown in Table 4.9 is siightiy improved, but is insignifiant.
It should be noted that the values of the current gain P depicted in al l tables are high.
According to Roulston [42], the author of the BIPOLE3 program, the values of should
be srnalier after fabrication than the numericaliy caiculated by BIPOLE3, partly because
the control parameters of the SiGe in the BIPOLE3 program were not fully established.
Also to be noted that, the cunent gain is strongly dependent on the minority carrier
lifetime in the emitter and surface recombination velocity [15], which is ciifficuit to
predict. because it is processing dependent.
There are rwo extra parameters left, which are not included in dl tables, the Early voltage
(VA) and the pinch sheet base resistance. Early voltages calculatecl h m BIPOLE3
simulations were fomd to be between 87-14 V. The fluctuations in the values of the VA
are due to the actual variation in the doping levels used during the simulations. For
example, the Early voltage of al1 the devices shown in Tables 4.7 and B.2 was found to be
87 V, whereas for the devices in Tables 4.8 and B.3, VA =140 V. Early voltage for
Si-base devices was found to be equal to 28 V. The pinch sheet resistance for al1 the
55
Table 4.9 Heavy ernitîer âoping, light EPI doping
I, =ZOO@ XJr = 0.05 pn BV,, = 7.7 V V, = 1.0 V XJ2=0.1362 pm BV, = 19.2 V ED = 6.0x10m cm-' Wb = 0.045 pn Reach through = 1.92 V BD = 1.0 x10 l8 cme3 TEPI = 0.59 pn Ge =lWo EPI = 1.0 x10 l6 cm-3
Table B. 1 Part2 Heavy ernitter doping, various geometries
The BVh and the reach through of the foiiowing devices are slightly different h m the devices listed in Table B.l partl, and their magnitudes are given below: SV, = 19.0 V Reach through = 5.17 V
NSAlL5X25 EMW=125 pnY
EMG-1.5 p l FPW =275 pn
Table B.2 Part 1. Light exnitter doping, various geomeaies
XJ, = 0.05 pm SV, = 5.7 V XJ,= 0.1381 pm BV, = 19.0 V Wb=0.045 prn Reach through = 4.79 V
I, =200pA v, = 1.0 v ED = 3.0 xlOa cmJ BD = 1.0 x10 l8 cm-3 EPI = 1.0 x10 l6 cm-3
FR GHz
NSAI25Xl25 EMW=125 pm E M S 1 2 5 pl FPW = t 7 5 pm
NSAlSXlS EMW=15 pm EMG- 1 5 pm FPW =3.0 pro
SA- 1 X' EPW=lS pl FPW=3.0 pm
Table B.4 Heavy emitter dopiog, light EPI doping. various geometries
I, =2ooM v, = 1.0 v ED = 6.0 xlOa cm" BD = 1.0 x10 l8 cm-' EPI = 1.0 x10 l6 cmm3
* Underestimaies base resistance
+ Si-base doping profiles: ED = 3.0 x10 XJ1 = 0.05 pn BV, = 9.6 V BD = 4.0 x10 cm'J XJ,=0.1398 p BVcbo=21-0V EPI = 1.0 x1Ol6 cm-' Wb = 0.07 pm Reacb through =4.19 V
TEP1 = 0.59 pm
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