Design of secure digital communication systems using chaotic modulation, cryptography and chaotic synchronization Tsun-I Chien a,b , Teh-Lu Liao a, * a Department of Engineering Science, National Cheng Kung University, Tainan, 701, Taiwan, Republic of China b Department of Electronics Engineering, Kao Yuan Institute of Technology, Kaohsiung County 821, Taiwan, Republic of China Accepted 14 September 2004 Communicated by Prof. M. Wadati Abstract This paper presents a secure digital communication system based on chaotic modulation, cryptography, and chaotic synchronization techniques. The proposed system consists of a Chaotic Modulator (CM), a Chaotic Secure Transmitter (CST), a Chaotic Secure Receiver (CSR) and a Chaotic Demodulator (CDM). The CM module incorporates a chaotic system and a novel Chaotic Differential Peaks Keying (CDPK) modulation scheme to generate analog patterns corre- sponding to the input digital bits. The CST and CSR modules are designed such that a single scalar signal is transmitted in the public channel. Furthermore, by giving certain structural conditions of a particular class of chaotic system, the CST and the nonlinear observer-based CSR with an appropriate observer gain are constructed to synchronize with each other. These two slave systems are driven simultaneously by the transmitted signal and are designed to synchronize and generate appropriate cryptography keys for encryption and decryption purposes. In the CDM module, a nonlinear observer is designed to estimate the chaotic modulating system in the CM. A demodulation mechanism is then applied to decode the transmitted input digital bits. The effectiveness of the proposed scheme is demonstrated through the numerical simulation of an illustrative communication system. Synchronization between the chaotic circuits of the transmitter and receiver modules is guaranteed through the Lyapunov stability theorem. Finally, the security features of the proposed system in the event of attack by an intruder in either the time domain or the frequency domain are discussed. Ó 2004 Elsevier Ltd. All rights reserved. 1. Introduction Since the pioneering work of Carroll and Pecora [1] in the field of chaos control in 1991, digital communication tech- niques based on chaotic systems have been the subject of intensive study. A literature review reveals a large number of related studies, including chaotic coding [2–9], chaotic modulation/demodulation [10–14], and multiple-access commu- nications [15–21]. In conventional digital communication systems, the data to be transmitted must first be mapped into a weighted sum of analog sample functions (e.g. sine and cosine) and then transmitted in the public channel via RF 0960-0779/$ - see front matter Ó 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.chaos.2004.09.009 * Corresponding author. E-mail address: [email protected](T.-L. Liao). Chaos, Solitons and Fractals 24 (2005) 241–255 www.elsevier.com/locate/chaos
15
Embed
Design of secure digital communication systems using chaotic
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Chaos, Solitons and Fractals 24 (2005) 241–255
www.elsevier.com/locate/chaos
Design of secure digital communication systems usingchaotic modulation, cryptography and chaotic synchronization
Tsun-I Chien a,b, Teh-Lu Liao a,*
a Department of Engineering Science, National Cheng Kung University, Tainan, 701, Taiwan, Republic of Chinab Department of Electronics Engineering, Kao Yuan Institute of Technology, Kaohsiung County 821, Taiwan, Republic of China
Accepted 14 September 2004
Communicated by Prof. M. Wadati
Abstract
This paper presents a secure digital communication system based on chaotic modulation, cryptography, and chaotic
synchronization techniques. The proposed system consists of a Chaotic Modulator (CM), a Chaotic Secure Transmitter
(CST), a Chaotic Secure Receiver (CSR) and a Chaotic Demodulator (CDM). The CM module incorporates a chaotic
system and a novel Chaotic Differential Peaks Keying (CDPK) modulation scheme to generate analog patterns corre-
sponding to the input digital bits. The CST and CSR modules are designed such that a single scalar signal is transmitted
in the public channel. Furthermore, by giving certain structural conditions of a particular class of chaotic system, the
CST and the nonlinear observer-based CSR with an appropriate observer gain are constructed to synchronize with each
other. These two slave systems are driven simultaneously by the transmitted signal and are designed to synchronize and
generate appropriate cryptography keys for encryption and decryption purposes. In the CDM module, a nonlinear
observer is designed to estimate the chaotic modulating system in the CM. A demodulation mechanism is then applied
to decode the transmitted input digital bits. The effectiveness of the proposed scheme is demonstrated through the
numerical simulation of an illustrative communication system. Synchronization between the chaotic circuits of the
transmitter and receiver modules is guaranteed through the Lyapunov stability theorem. Finally, the security features
of the proposed system in the event of attack by an intruder in either the time domain or the frequency domain are
discussed.
� 2004 Elsevier Ltd. All rights reserved.
1. Introduction
Since the pioneering work of Carroll and Pecora [1] in the field of chaos control in 1991, digital communication tech-
niques based on chaotic systems have been the subject of intensive study. A literature review reveals a large number of
related studies, including chaotic coding [2–9], chaotic modulation/demodulation [10–14], and multiple-access commu-
nications [15–21]. In conventional digital communication systems, the data to be transmitted must first be mapped into
a weighted sum of analog sample functions (e.g. sine and cosine) and then transmitted in the public channel via RF
0960-0779/$ - see front matter � 2004 Elsevier Ltd. All rights reserved.
The mapping of every two input bits into an analog symbol prior to transmission across the public channel is gen-
erally performed using either the QAM or QPSK modulation scheme. In the present study, every eight information bits
plus two synchronization bits are mapped into appropriate analog chaotic patterns in accordance with the results of the
self-learning process described previously in Section 2. In the self-learning process, the time evolution of one state var-
iable can be selected as the source for obtaining the chaotic patterns and can be observed from the free running chaotic
circuit in the CM. The local peak values of the selected state are recorded, and bits of either �0� or �1� are subsequentlyassigned to them in accordance with a specified encoding scheme. In the present study, if it is detected that the following
positive/negative peak value is greater than the current positive/negative peak value, this condition is marked as bit �1�,otherwise it is marked as bit �0�. Fig. 2 illustrates the proposed encoding method, in which P1, P2, P3, and P4 are the
positive peak values of state x3, while N1 and N2 are the negative peak values of state x3. Alternatively, if the intention
is to consider the effects of channel noise, the condition P2–P1 > a > 0 can be encoded as bit �1� and P2–P1 < b < 0 en-
coded as bit �0�, where a and b are noise threshold parameters. A similar operation can also be performed when encod-
ing the negative peak values. The characteristics of the proposed chaotic modulation scheme lend this scheme its name
of Chaotic Differential Peaks Keying (CDPK). The detailed procedures of the CDPK (off-line self-learning) can be sum-
marized as follows:
1. Enable the self-learning process.
2. Sample data from all states of the free running chaotic circuit in the CM.
3. Digitize these sampled data and detect local peak values of the selected output state and store these values in the
buffer.
4. In accordance with the encoding rule described in Fig. 2, match each N + 1 consecutive peak value with the appro-
priate N � s bit binary code from the buffer.
5. Store the first peak value of the consecutive series obtained in Step 4 and the digitized values of the other sampled
states at this moment in the CM�s memory.
6. Repeat from Steps 2 and 5 until all 2N�s binary codes have been found.
7. Disable the self-learning process and commence data transmission.
In Step 4, N and s denote the bit number of the transmitted symbol with synchronization bits and the bit number of
synchronization, respectively. During data transmission, the input bits are supplied to the proposed communication
system. The bit stream is divided into several bit sets comprising s synchronization bits followed by N � s information
bits. Fig. 3 illustrates the example of a chaotic pattern corresponding to two synchronization bits (�10�) combined with
eight information bits (�00111001�) for the case where state x3 is selected as the modulating signal. In this example,
N = 10 and s = 2. Having established the chaotic patterns corresponding to the input information bits, the peak values
392.23 400 405-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
Time
Amplitude
P1 P2
1 01 0
03x
03x
P3< < P4
>
>
N1 N2>
Fig. 2. The proposed encode/decode method.
392.23 400 405 410 415 420 -1.5
-1
-0.5
0
0.5
1
1.5
2One of Chaotic patterns(11 00111001) using state x3
Time
Am
plitu
de
0111 0
Sync. Sync.
1 1 0 0 1
Fig. 3. One of Chaotic patterns (11 00111001) using state x3.
where x denotes the dynamic estimate of the state x. Moreover, the constant vector L 2 Rn is chosen such that
(A � LCT) is an exponentially stable matrix, which is possible since the pair (CT, A) is observable.
By allowing the state error e ¼ x� x and the output error e1 ¼ y � y, the error dynamics can be expressed as follows:
_e ¼ _x� _x ¼ ðA� LCTÞe;e1 ¼ CTe:
ð3Þ
Since the matrix A � LCT is exponentially stable, it can be easily verified that the error dynamics exponentially con-
verge to zero for any initial condition eð0Þ ¼ xð0Þ � xð0Þ. Consequently, the dynamics of the chaotic drive system of Eq.
(1) and the driven system of Eq. (2) are synchronized at the rate of convergence: exp�kminðA�LCTÞ, where kmin(D) denotes
the minimum eigenvalue of the matrix D.
4.2. Design of CST and CSR
As shown in Fig. 1, the CST and CSR modules comprise four chaotic systems for cryptographic and chaotic syn-
chronization purposes. The main transmitter and Slave System 2 in the CST are designed to mask the transmitted
ciphertext and to generate the confidential key, K, used by the encryption algorithm, respectively. Meanwhile, the main
receiver and Slave System 4 in the CSR are designed to recover the plaintext and to generate the confidential key, bK ,
required by the decryption algorithm.
The main transmitter is a chaotic system described by a slightly modified form of Eq. (1), i.e.
_x ¼ Axþ f ðy01Þ þ Bðd þ hTgðy01ÞÞ þ Ls;
y01 ¼ CTxþ s ¼ y1 þ s;ð4Þ
where s 2 R is the ciphertext, which is obtained by designing Slave System 2 and the encryption function described
below. Furthermore, the chaotically transmitted signal, which simultaneously drives the main receiver and Slave System
4 for chaotic synchronization, is given by the sum of the output of the main transmitter and the ciphertext, y01 2 R.Employing the state observer design, the main receiver is constructed as follows:
where x denotes the dynamic estimate of the state x, and the constant vector L 2 Rn is chosen such that (A � LCT) is an
exponentially stable matrix, which is possible for the reason described in the preceding section.
By involving the plaintext signal p(t), which is the output of the CM, the ciphertext is obtained by
sðtÞ ¼ senðpðtÞ;KðtÞÞ; ð6Þ
where sen(Æ) is a generic encryption function which makes use of a confidential key signal, K(t).
Since only the output of the main transmitter is available, the keys are generated by means of other chaotic systems,
as demonstrated by He [26]. The keys K(t) and bK ðtÞ are determined from
KðtÞ ¼ KðzðtÞÞ and bK ðtÞ ¼ K ðzðtÞÞ; ð7Þ
where K :Rn ! R, and z and z are the state variables of Slave Systems 2 and 4, respectively.
Furthermore, according to Fig. 1, the ciphertext is recovered by
sðtÞ ¼ y01ðtÞ � y1ðtÞ ¼ y1ðtÞ þ sðtÞ � y1ðtÞ: ð8Þ
Given the recovered ciphertext, sðtÞ, and the key bK ðtÞ, the plaintext is then recovered by
pðtÞ ¼ sdeðsðtÞ; bK ðtÞÞ; ð9Þ
where sde(Æ) is the decryption function [26,34].
By applying symmetric algorithms, the confidential keys and the ciphertexts converge asymptotically, i.e.bK ðtÞ ! KðtÞ and sðtÞ ! sðtÞ as t! 1, which, in turn, implies that the asymptotical convergence of the plaintexts is also
Close examination of Eq. (4) reveals that the proposed communication scheme combines chaotic masking and
chaotic modulation functions. The masked signal, y01, is used simultaneously for synchronization purposes and as
the information-bearing signal. In conventional chaotic masking methods, the receiver is driven by the sum of the
information signal and the output of the transmitter, whose dynamics are autonomous. However, in this work, the
ciphertext and the transmitted signal are also fed back to the transmitter. Hence, the dynamics of the main transmit-
ter are driven by the time-varying signals y01ðtÞ and s(t), thereby implying that the transmitter is a non-autonomous sys-
tem, which is generally more complicated. However, in order to maintain the chaotic behavior of the systems, the
amplitude of the ciphertext, s(t), must be carefully designed. Furthermore, the keys generated from chaotic Slave Sys-
tems 2 and 4 are random-like signals and are independent of the transmitted signal. An intruder cannot easily attack the
plaintext by using the transmitted signal only, and hence the security of the proposed communication system is
enhanced.
5. Design of Chaotic Demodulator (CDM)
As shown in Fig. 1, the output of the CSR is supplied to the CDM. A nonlinear observer for estimating the chaotic
modulating system in the CM is designed and a demodulation mechanism (bit detector) is then applied to decode the
transmitted input digital bits. As has been derived in Section 4, the synchronizations between the CST and CSR mod-
ules and between the CM and CDM modules are ensured by adopting the observer technique, and hence the transmit-
ted information bits can be recovered by measuring the chaotic circuit�s output and assigning bits of either �0� or �1� inaccordance with the decoding rule in Fig. 2. The demodulation procedure can be summarized as follows:
1. Sample data from the output of the CDM�s chaotic circuit.
2. Digitize these sampled data and store them in Buffer 1, designated as the digitized sample data buffer.
3. Determine two successive local peak values from the sample data in Buffer 1 and then store them in Buffer 2, des-
ignated as the peak values buffer.
4. Read out the data in Buffer 2 and assign bits of �0� or �1� in accordance with the decoding rule in Fig. 2. Store this bit
in Buffer 3, designated as the output buffer.
5. Repeat Steps 1–4 until all N bits have been stored in the output buffer.
6. Output all bits in the buffer other than the initial s synchronization bits and clear up all buffers.
7. Repeat Steps 1–6 until the transmission is terminated.
Remark. Synchronization between the input bits and the received bits can be maintained by establishing a
communication protocol between the transmitter and the receiver. Sending a pilot signal is a potential treatment for
this synchronization issue. Additionally, the CDM�s chaotic circuit can be removed if the modulating signal comprises
only the output of the CM�s chaotic circuit. The input bits can then simply be recovered by observing the output
of the CSR. Note that if the modulating signal is a state other than the output state of the CM�s chaotic circuit,
the CDM�s chaotic circuit cannot be omitted because these two chaotic circuits must be synchronized if the input bits
are to be recovered from the modulating signal. In other words, it is possible to select a modulating signal which
differs from the output of the chaotic system such that the modulation signal cannot be retrieved directly form the
output of the chaotic system. This also increases the security of the communication system against attack by
intruders.
6. An illustrative communication system and simulation results
To verify the proposed secure digital chaotic communication system, this section of the paper develops an illustrative
system and performs numerical simulations of its operation.
As described in Sections 2 and 3, in order to transmit digital input bits through the proposed system, an off-line self-
learning process is executed prior to the transmitting period in order to acquire the peak values of the modulating signal
at the beginning of the chaotic patterns corresponding to the input bit sets. Subsequently, every eight information bits
can be transmitted by retrieving the corresponding peak value sets from the memory and supplying these value sets to
the CM�s chaotic circuit to perturb the signal of the circuit. In the CM, a chaotic Rossler-like system with six terms and
one nonlinearity adopted from Case S of 19 distinct simple examples of chaotic flows presented in [38] is described as
Herein, the confidential keys are chosen as K(t) = z1(t) and bK ðtÞ ¼ z1ðtÞ. The ciphertext is then obtained by the fol-
lowing encryption algorithm:
sðtÞ ¼ 0:01ðpðtÞ þ ð10z1ðtÞÞ mod ð13ÞÞ ð21Þ
The following decryption algorithm is dedicated to recover the plaintext:
pðtÞ ¼ 100sðtÞ � ð10z1ðtÞÞ mod ð13Þ: ð22Þ
If circuit complexity is a major issue in designing a communication system, using a fixed confidential key to replace
Slave Systems 2 and 4 might be an option. However, without loss of generality, the present example demonstrates
the proposed system shown in Fig. 1, which includes Slave System 2 and 4 rather than a fixed confidential key.
By defining the state error ex ¼ x� x ¼ x1 � x1 x2 � x2 x3 � x3½ �T, where xi � xi denotes the error between the ith
state of the main transmitter and the ith state of the main receiver, and ez ¼ z� z ¼ ez1 ez2½ �T ¼ z1 � z1 z2 � z2½ �T,where zi � zi denotes the error between the ith state of Slave System 2 and the ith state of Slave System 4, the error
From the viewpoint of synchronization, ex denotes the synchronization error between the main transmitter and the
main receiver. And, ez denotes the synchronization error between Slave System 2 and Slave System 4 for generating the
encryption key and the decryption key, respectively. If ez converges to zero asymptotically, then the confidential keys
will be synchronized, i.e. bK ðtÞ ! KðtÞ. To guarantee the stability of the error dynamics (23), the Lyapunov approach is
applied. Consider the Lyapunov function as follows:
V ¼ 1
2ðeTx P eex þ eTz ezÞ; ð24Þ
where the positive symmetric matrix Pe ¼ PTe is a solution of the following Lyapunov equation:
ðA� LCTÞTPe þ PeðA� LCTÞ ¼ �I : ð25Þ
Differentiating V with respect to time and along with the error dynamics yields
_V ¼ �eTx ex � e2z13
4ðz1 þ z1Þ2 þ
1
4z1 � z1Þ2
� �� 8e2z2 6 0 ð26Þ
According to the Lyapunov stability theorem, the error dynamics are globally asymptotically stable. Thus, the main
transmitter and the main receiver are synchronized. Moreover, Slave Systems 2 and 4 are also synchronized. Therefore,
as shown in the preceding section, the confidential keys and ciphertexts converge asymptotically, i.e. bK ðtÞ ! KðtÞ andsðtÞ ! sðtÞ as t! 1, and the plaintext can be recovered, i.e. pðtÞ ! pðtÞ as t !1. Once the plaintext is presented cor-
rectly at the input of the CDM, by means of the proposed modulation scheme of Fig. 2, the input bits can be restored
providing that synchronization between the chaotic circuits of the CM (Eq. (12)) and the CDM (Eq. (13)) is achieved.
The error dynamics between Eqs.(12) and (13) are given as
_em ¼ _x� _x ¼ ðAm � LmCTmÞem: ð27Þ
Since the matrix Am � LmCTm is exponentially stable, it can be easily verified that the error dynamics exponentially
converge to zero for any initial condition emð0Þ ¼ xð0Þ � xð0Þ. As mentioned in Section 3, the dynamics of the chaotic
circuits, Eqs. (12) and (13), are synchronized at the rate of convergence: exp�kminðAm�LmCTmÞ.
As a numerical simulation, the input bit set (�00111001�) is transmitted from the transmitter to the receiver in the
proposed communication system. Fig. 4 presents both the encryption key and the recovered key for the bit set
0 5 10 15 20 25 30 35 40 45-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
Time
Am
plitu
de
The encryption key(dashed) and the recovered one(dash dot)
Fig. 4. The encryption key (dashed) and the recovered one (dash–dot).
0 5 10 15 20 25 30 35 40 45-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
Time
Am
plitu
de
The ciphertext(dashed) and the recovered ciphertext(dash-dot)
Fig. 5. Ciphertext (dashed) and recovered ciphertext (dash–dot).
There are two attack methods described in [41], which are power analysis attack and generalized synchronization
attack. These two methods have been shown the effectiveness to break the chaotic parameters modulation system such
as CSK, which transmits bit �0� or �1� by means of switching a parameter�s set to another. Since the power difference is
quite obvious during transmitting data in the above system, it is possible to extract data directly from the transmitted
signal through detecting this power difference. In the generalized synchronization attack, it is assumed that the attacker
knows what kind of chaotic circuits in the transmitter, but still without knowing of its exact parameters and initial con-
ditions. As mentioned in [41], the synchronization error of attacker�s receiver will be calculated firstly. Next, the syn-
chronization error is multiplied by the transmitted signal. Then, this signal is filtered by a low-pass filter. Finally, a
binary quantizer is used to recover the plaintext. However, in this paper, the chaotic parameters modulation scheme
is not used in the proposed communication system. Hence, the power analysis attack and generalized synchronization
attack are intuitively ineffective to our system. Also, the simulation results shown in Fig. 9 and Fig. 10 demonstrate this
viewpoint.
Furthermore, the fourth attack method proposed in [42], the filtering attack, will be introduced. In some chaotic
masking communication systems, if the plaintext is an analog narrow band signal, it is possible to locate the plaintext�sband by spectra analysis. Then, the plaintext will be simply extract from the transmitted signal just by using a filter. Fig.
0 50 100 150 200 250 300-2
-1
0
1
2
3
4
5
6
Time
Am
plitu
de
The Plaintext (dashed) and The recovered plaintext (dash-dot) using the power analysis attack
Fig. 9. The transmitted plaintext (dashed) and the recovered plaintext (dash–dot) using the power attack method.
0 5 10 15 20 25 30 35 40 45 50-1.5
-1
-0.5
0
0.5
1
1.5
2
Time
Am
plitu
de
The Plaintext (dashed) and the recovered plaintext (solid) using the generalized synchronization attack
Fig. 10. The transmitted plaintext (dashed) and the recovered plaintext (solid) using the generalized synchronization attack method.
0 50 100 150 200 250 300 350 400 450 500-40
-30
-20
-10
0
10
20
30
40Frequency content of the transmitted signal
frequency (Hz)
Sig
nal p
ower
(db
)
Fig. 11. The spectra diagram of the transmitted signal (the output of CST).
synchronize and to generate confidential keys, which are totally random-like signals and are independent of the trans-
mitted signal. An illustrative system has been presented to demonstrate the effectiveness of the proposed scheme. The
synchronization and stability of the overall system is guaranteed by the Lyapunov approach. Although this study has
considered low-dimensional chaotic systems, the proposed scheme can also be extended to hyperchaotic systems. Since
the CST�s main transmitter is a non-autonomous system and confidential keys are used, the security of the proposed
communication system is greatly enhanced. We also discussed four attack methods to verify the security of the pro-
posed communication system. In addition, a scalar transmitted signal is used in the proposed communication system,
hence overcoming the limitations of previous studies, in which it was necessary to send two signals.
It is acknowledged that this paper has only presented theoretical results. The effects of channel noise and parameter
mismatches between the chaotic circuits and hardware implementation considerations will be addressed in a future
study.
Acknowledgment
This research was supported by the National Science Council, Republic of China, under Grant NSC 92-2213-E-006-
006.
References
[1] Carroll TL, Pecora LM. Synchronizing chaotic circuits. IEEE Trans Circuits Systems I 1991;38:453–6.
[2] Schimming T, Hasler M. Coded modulations based on controlled 1-D and 2-D piecewise linear chaotic maps. In: Proceedings of
the 2003 International Symposium ISCAS �03, 2003. p. III-762–III-765.[3] Marino IP, Lopez L, Miguez, J, Sanjuan MAF. A novel channel coding scheme based on continuous-time chaotic dynamics. In:
14th International Conference on Digital Signal Processing, 2002. p. 1321–4.
[4] Chen B, Wornell GW. Efficient channel coding for analog sources using chaotic systems. In: GLOBECOM �96. Communications:
The Key to Global Prosperity, 1996. p. 131–5.
[5] Frey DR. Chaotic digital encoding: an approach to secure communication. IEEE Trans Circuits Systems II: Analog Digital Signal
Process 1993;40:660–6.
[6] Barbulescu SA, Guidi A, Pietrobon SS. Chaotic turbo codes. IEEE Int Symp Inform Theory 2000:131–5.
[7] Chambers WG, Frey D. Comments on ‘‘Chaotic digital encoding: an approach to secure communication and reply’’. IEEE Trans
Circuits Systems II: Analog Digital Signal Process 1999;46:1445–8.
[8] Frey DR. On chaotic digital encoding and generalized inverses. IEEE Int Symp Circuits Systems 1995:893-6.
[9] Aislam T, Edwards JA. Secure communications using chaotic digital encoding. Electron Lett 1996;32:190–1.
[10] Dedieu H, Kennedy MP, Hasler M. Chaos shift keying: modulation and demodulation of a chaotic carrier using self-
synchronizing Chua�s circuits. IEEE Trans Circuits Systems II: Analog Digital Signal Process 1993;40:634–42.