DESIGN OF RADIX-8 BOOTH MULTIPLIER USING ...

DESIGN OF RADIX-8 BOOTH MULTIPLIER USING

PARALLEL PREFIX ADDERS

Mr.G.Ravi 1, Ch.Darsini Ram, 2, V.Divya 3, E.Teja Sri 4.

1 Asst Prof., ECE Department, ALIET, JNTUK,Vijayawada, Andhra Pradesh , India.

2 Student, ECE Department, ALIET, JNTUK,Vijayawada, Andhra Pradesh , India.

3Student, ECE Department, ALIET, JNTUK,Vijayawada, Andhra Pradesh , India.

4 Student, ECE Department, ALIET, JNTUK,Vijayawada, Andhra Pradesh , India.

E-mail: [email protected] , E-mail: [email protected]

E-mail:[email protected] , E-Mail: [email protected],.

ABSTRACT As we are moving ahead and the technology is increasing day by day we are mainly aiming on power consumption, area utilization and time delay. Multiplication is most familiar in arithmetic operations and mathematical applications. If the number of multiplier and multiplicand bits are increasing the complexity of the multiplication increases. So in order to reduce the complexity we are mainly focusing on reducing the partial products. If we lessen the number of partial products then automatically we can dwindle the power consumption, area utilization. In this multipliers have been designed for Radix-8 Booth multiplier using PPA. Results will display a change in area, power consumption and delay. Here we can take large number of bits and easily calculate the multiplication. Keywords: PPA, Radix-8 Booth multiplier, Parallel Prefix Adders.

1.INTRODUCTION The performance of the device mainly depends on the performance of the processor. It is becoming most popular in industrial markets.For attaining high performance operations like addition, subtraction and multiplication is used in digital circuits to enhance computational speed. Generally multiplier is very slow in arithmetic operators because it consists of partial products. The partial products increases as number of bits increases. The multiplier is having more power dissipation and area consumption which gradually dwindles the efficiency of the system. Multipliers are used in many applications such as scientific applications, image processing, machine learning and image processing applications such as, Fast Fourier Transform(FFT), convolution, correlation, filtering and in ALU of microprocessors. To increase the performance of the multiplier we have utilized many power reduction algorithms and also different multipliers. To utilize

Science, Technology and Development

Volume XI Issue VI JUNE 2022

ISSN : 0950-0707

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less power we are using booth recoding algorithm.Different types of booth multipliers are present but Radix booth multiplier is having unique architecture.Here to reduce the partial products we are having two types of adders.They are serial adders and parallel adders. The multiplication has two important steps they are

(i) Generating the partial products (ii) Adding the partial products Multiplication speed can be improved by reducing the partial products. A good multiplier should have the following parameters such as (a) Precision:An efficient multiplier

should give accurate results. (b) Rapidity:Multiplier should perform

high speed operation. (c) Size:A multiplier should utilize as

much as less number of gates and look-up tables. Parallel or serial multiplier can be utilized on the type of application. It is possible to demolished multipliers into 2 parts. 1)By multiplying multiplier and multiplicand we will produce the partial products. 2)We have to reduce the number of partial products. 3)Finally we have to add. For the multiplication of an n-bit multiplicand with an m bit multiplier, m partial products are generated and product formed is n + m bits long.

2.Booth Algorithm

The algorithm was invented by Andrew Donald Booth in 1950 while doing research on crystallography atBirbeck in Bloomsbery, London. Booth's multiplication algorithm is a multiplication algorithm that multiplies two signed binary numbers in two’s complement notation.Booth’s algorithm helps in reducinng the number of partial products.It helps in fast computation.

Fig:block diagram of Radix

The above block diagram represents the block diagram of booth algorithm. It will multiply 2 signed or unsigned Binary digits in 2’s compliment form.

Radix-8 booth algorithm: Radix-8 Booth algorithm helps in dwindling the number of partial products to n\3.Radix-8 booth algorithm helps in comparing the for bits at a time using booth encoding table.Due to this the computation will become easy and simple.



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Radix-8 Booth algorithm Encoding table:

Table 1: Radix-8 Booth algorithm Encoding table

Here we will compare 4 bits at a time and use the radix-8 booth encoding table to multiply the two numbers.

3. Parallel Prefix Adders

The parallel prefix adders is similar to carry look ahead adder. Generally the partial products in multipliers produces the delay. The carry look ahead adders are serial adders which will take one by one bit and adds it in an serial manner. The parallel prefix adders are parallel adders which will simultaneously add the partial products and reduces the delay. The parallel prefix adders is also called fast multipliers. The parallel prefix adders are also known as Logarithmic delay adders . The process of addition in parallel prefix adders takes place in 3 stages:

a) Pre-computation stage.

b) Intermediate stage.

c) Final computation stage.

Fig:Block Diagram Process of parallel prefix adder

Fig : Structure of Parallel prefix adder using Koggestone adder.

The propagate function are specified by the logical equation,



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P = Ai XOR Bi Where the Ai and Bi are the inputs which consist of XOR logic.

The generate function are specified by the logical equation,

G = Ai AND Bi Where the Ai and Bi are the inputs which consist of AND logic.

As the propagate and generate are produced during parallel addition there will be no increase in area consumption but the time delay depends on the total length of bits.If the number of bits increases then automatically the delay inncreases.

In the intermediate stage mainly carry generaton and carry propagation takes place.The carry generation helps in producing delay products.

The final stage helps in adding the inputs and generating the final products.

Fig:Block diagram of Radix-8

4. RESULTS:

The results after implementation have been shown below. The time analysis, power analysis reports, RTL Schematic diagrams are been showed. By which we can state the speed of the system and the area is given by stating the number of device utilization summary.

4.1 Results of the RTL Schematic:

fig: RTL schematic of Radix-8

4.2 Time delay of Radix-8:

Fig:Time Delay Of Radix-8



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4.3 Simulation results of Radix-8:

Fig:Simulation Results Of Radix-8

4.4 Power consumption of Radix-8:

Fig:Power Consumption Of Radix-8

5.CONCLUSION:

In this project we have designed a Radix-8 booth multiplier using parallel prefix adders. In this paper, an efficient high speed Radix-8 Booth multiplier using 32-bit kogge stone adder is designed successfully using Xilinx Vivado software and Xilinx ISE. By using Radix-8 booth recoding algorithm we have reduced the number of partial products generation by n/3 and also decreased the addition operations by which we have achieved less area consumption and better performance. The parallel prefix adders helped in reducing the delay which is a great advantage.

The 32-bit kogge stone adder in our proposed design shown significant decrease in the delay and power consumption. The synthesis report shows that among the kogge stone adder the radix-8 booth multiplier using 32-bit achieved less delay and less area consumption. This work can be extended for higher number of bits.

REFERENCES:

W. –C. Yeh and C. –W. Jen, “High Speed Booth encoded Parallel Multiplier Design,” IEEE transactions on computers, vol. 49, no. 7, pp. 692-701, July 2000.

Leandro Z. Pieper, Eduardo A. C. da Costa, Sergio J. M. de Almeida,“Efficient Dedicated Multiplication Blocks for2´s Complement Radix-2m Array Multipliers,” JOURNAL OF COMPUTERS, VOL. 5, NO. 10, OCTOBER 2010.

https://turcomat.org/index.php/turkbilmat/article/view/2242

M. Macedo, L. Soares, B. Silveira, C. M. Diniz, Eduardo A. C. da Costa, "Exploring the use of parallel prefix adder topologies into approximate adder circuits” in 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017. https://doi.org/10.1109/icecs.2017.8292078

2242-Article Text-4230-1-10-20210409.pdf



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Authors:

Mr G Ravi present working as a Asst Professor in Andhra Loyola Institute of Engineering & Technology, ECE Department, Vijayawada, Andhra Pradesh, India.

CH. DARSINI RAM presently pursuing B. Tech in the branch of Electronics and Communication Engineering at Andhra Loyola Institute of Engineering & Technology, Vijayawada, Andhra Pradesh, India

V.DIVYA presently pursuing B. Tech in the branch of Electronics and Communication Engineering at Andhra Loyola Institute of Engineering & Technology, Vijayawada, Andhra Pradesh, India

E.TEJA SRI presently pursuing B. Tech in the branch of Electronics and Communication Engineering at Andhra Loyola Institute of Engineering & Technology, Vijayawada, Andhra Pradesh, India.



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DESIGN OF RADIX-8 BOOTH MULTIPLIER USING ...

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