University of Southampton School of Electronics and Computer Science Design of PVT Tolerant Bandgap Reference Circuit for Low Noise and Low Current By Manraj Singh Gujral msg1g10 22 nd September, 2011 Project supervisor: Dr. Peter R Wilson Second Examiner: Dr. Koushik Maharatna A project report submitted for the award of Master of Science in System‐on‐Chip
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Design of PVT Tolerant Bandgap Reference Circuit for Low Noise and Low Current
This project deals with the design of one the most common blocks used in almost all system‐ on‐chip designs, a Bandgap Reference circuit. A reference signal or a voltage source which is the first signal generated on a chip that and then can be used for biasing, generating other signals across the chip etc. The design focuses on the Noise performance and its effect on the other systems connected to it. A detailed step‐by‐step approach is presented in this report towards an ultra low noise performance. The Bandgap is tested for worst case industrial Corners, is laid out, extracted and finally verified with Schematic vs. Extracted checks.
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University of Southampton
School of Electronics and Computer Science
Design of PVT Tolerant Bandgap Reference Circuit for
Low Noise and Low Current By
Manraj Singh Gujral msg1g10
22nd September, 2011
Project supervisor: Dr. Peter R Wilson Second Examiner: Dr. Koushik Maharatna
A project report submitted for the award of Master of Science in System‐on‐Chip
Manraj Singh Gujral msg1g10 University of Southampton 2
AbstractWith each new process technology, essentially driven by digital electronics, the transistor
sizes are being shrunk to their limits so that they can be packed in millions in a small silicon
area. This increases the complexity for analogue circuits which are required to produce an
accurate output despite increased performance‐degrading parameters, over a range of
conditions like temperature, voltage fluctuation and process errors. Therefore, with every
leap in process technology, more and more intelligent ways of implementing the analogue
and mixed signal circuits are being sought after.
This project deals with the design of one the most common blocks used in almost all system‐
on‐chip designs, a Bandgap Reference circuit. A reference signal or a voltage source which is
the first signal generated on a chip that and then can be used for biasing, generating other
signals across the chip etc. The design focuses on the Noise performance and its effect on the
other systems connected to it. A detailed step‐by‐step approach is presented in this report
towards an ultra low noise performance. The Bandgap is tested for worst case industrial
Corners, is laid out, extracted and finally verified with Schematic vs. Extracted checks.
AcknowledgmentsI would like to thank Dr Peter Wilson, my supervisor, for encouraging me to take on this
project.
Also, I would thank Dr Ke Li for offering me his time and assistance whenever I got stuck.
Special thanks to Mr. Ajaib Hussain, UK Engineering Manager, Rakon UK Ltd., for providing
me a chance to work on this project in Rakon with industrially acceptable specifications and
performance criteria.
I would also like to thank the Design Team in Rakon UK Ltd., Mr. Kevin Aylward (Principal IC
Designer), Mr. Karl Ward (Principal Design Engineer), Mr. Ravi Ramakrishna (Sr. IC Design
Engineer) , Mr. Robbie Robinson (Sr. Layout Engineer) & Mr. Mark Broad (Sr. Layout
Engineer) for their constant feedback and support throughout this project.
Manraj Singh Gujral msg1g10 University of Southampton 3
The values coming out of this bandgap are much better in terms of Noise performance.
Industrially the Noise due to bandgap is in the range of several 10’s of nV at 10kHz. This
circuit comes quite close to the industrial standards and serves as the base from which
further improvements can be made.
This Bandgap was tweaked about and worked upon in various ways to get to these low
output noise levels. From the given library of IBM7WL, all resistors were tested for the least
amount of noise at the output.
Table 6: Bandgap output Noise with different types of resistors and their sheet resistance
Resistor Type nV/√Hz (at 1 Hz) Sheet Resistance Ω/
oprppcres 631 260
oprrpres 2751 1600
oppdres 431.9 105
opndres 438 72
nwrrpres 2751 1600
nwrppres 631 260
nwppcres 660 NA
k1res 437 61
Manraj Singh Gujral msg1g10 University of Southampton 27
The readings in table 6 were obtained during the design of the bandgap when I was looking
to lower the noise of the whole system. Hence the values are not as per the output
performance shown in the figure 34. The Sheet resistance was referred from the IBM Design
Manual for their IBM7WL process.(6)
Two parameters were considered, firstly, and with a higher priority, was to achieve a low
output noise by changing the type of resistor. It can be seen that the Noise at the output
ranges from a minimum of 431.9 nV/√Hz to 2751 nV/√Hz. That is roughly 8 mes apart.
Therefore before changing the circuit topology it was prudent to change the type of
resistance which would provide the lowest resistance.
Secondly, with lower priority, the size of resistances. As can be seen from Table 6 the Noise
due to k1res (metal resistor) is fairly low, but the sheet resistance is extremely low. That
would mean a resistance in the range of several kΩ is not practical in this circuit.
Also, nwrrpes type of resistor have the highest sheet resistance, i.e., taking up least space in
the layout. But this has a very high output noise affect on the Bandgap when used as the
main resistors which lie in the signal path, i.e., R1 or R2 in Equation 22. In the startup circuit,
for Bandgap ‐3, the resistance value is in the range of MΩ and it does not lie in the signal
path, i.e., not affecting the output noise. In this case, the resistance is then used as the
nwrrpres type. This enables us to have the highest resistance in the minimum possible area
with no effect on the noise.
It is interesting to see the noise distribution inside the bandgap.
Table 7: Noise Summary for Bandgap‐3.
Spot Noise Summary (in V^2/Hz) at 1K Hz Sorted By Noise Contributors
Total Summarized Noise = 1.04402e‐14
Device Noise Contribution % of Total
I0.RP0.rma 1.88E‐15 18.01
I0.RP0.rmb 1.88E‐15 18.01
I0.Q20.q 8.59E‐16 8.22
I0.Q19.q 8.36E‐16 8.01
I0.Q1.q 8.32E‐16 7.97
The highest noise contributor is the Resistance RP0 (in Cadence Schematic), or R3 in
Equation 22. Another adjustment which was made was to make this resistance very thick in
size. I.e., the width of the resistance was set to 3µm and the equivalent length of the
Resistance depending on its resistance value was set. We can see that 3µm, serves the
purpose by being just big enough to have low 1/f noise and being small enough to have a
fairly low contribution in area when laying out.
Manraj Singh Gujral msg1g10 University of Southampton 28
The general Bandgap output is given by the equation
1 1 2 2
Equation 21
Which implies addition of a CTAT Voltage slope to a PTAT voltage slope to finally give an
output which is temperature independent?
In this bandgap circuit the output can be written as
∆ 1
Equation 22
Since the temperature dependence of VBE1, as given in Equation 6, if we assume n and r are
both equal to 1, then
0.087 /
Equation 23
And from equation 5 we can see that the,
1.3 /
Equation 24
Therefore from equation 22 and 23, it can be seen that the Bandgap‐3 is made to work with
α1 =1
V1 = VBE1 , which forms the CTAT part of the equation
α2 = (R2/R1 +1)
and, V2 = ΔVBE , which forms the PTAT part of the equation
Therefore to match the slope of both these parts, we need to ensure
2 1
Equation 25
Expanding α2 = (R2/R1 +1) in the above equation
2
31 1
Equation 26
Equation 26 is now the foundation of our bandgap. This not only sets the slope of the VREF
but also shows us how to set it.
We can adjust the slope in two ways.
1. Varying Resistor Ratio, R1 and R2, to make sure (R2/R3 +1) x 0.087 x 10‐3 = 1.3 x 10‐3.
As seen in the previous section, one of major noise contributor is the resistance
itself. Therefore to some extent, we have to increase the resistance value but there
is a limit up to which it starts impacting on the noise. Therefore increasing the
resistance value might not serve the purpose.
Manraj Singh Gujral msg1g10 University of Southampton 29
2. Varying the to make 1 . Where ln , r
being the ratio of the bipolar size.
There are further two ways of performing this:
a. By varying the size ratio of transistor size, r. This also has its practical limits.
Similar to Figure 18, the diode connected transistors have to be matched
during layout. So in theory we might be able to increase the ratio r to any
value we want, however in practise there is only up to a certain ratio at which
we can ideally march. Some of the acceptable ratios are 1:8, 1:16, 1:32 and
1:64. Beyond this it becomes difficult to match.
b. Another technique used for ultra low bandgaps is known as the stacking
Figure 35 : Block Diagram to illustrate the ΔVBE stacking(7)
To avoid large transistor ratio, r, the concept of ΔVBE addition can be used. The circuit
shown in figure 35 uses this approach presented in a thesis report from Mr William T
Holman, which helps lowering the noise since dependence on the resistance ratio is reduced
considerably. The author simulated this concept and measured the output noise in the level
of 30nV/√Hz (at 10kHz)
A patent on a similar concept was filed by Sander Gierkink (8)
This technique could be further used to reduce the noise to ultra low levels in bandgap‐ 3
aswell.
Manraj Singh Gujral msg1g10 University of Southampton 30
Chapter4:CornerSimulationsforBandgap‐3
Bandgap‐3 circuit is now selected to be used for next stage, to perform the worst case
corner simulation. These corners are industry based actual samples from Rakon. The
following points explain the setup.
1. Temperature : ‐45 to 90C (Although ‐45 to 125 is also successful for Typical Model)
2. Supply Voltage , Vdc : 1.6V ,1 .8V, 2.0V (Vdc has been tested for 1.5V to 2.2V for a
Typical Case)
3. Strong & Weak characteristics for the following Model files (Also simulated for the
Nominal/Typical Corner):
a. Bip.scs : npn Bipolar devices
b. Bipp.scs: pnp Bipolar devices
c. Nmos.scs : NMOS devices
d. Pmos.scs: PMOS devices
e. Rescap.scs : All Resistances and Capacitances in the IBM7Wl library.
4. Total Number of Corners , therefore 3(Vdc) x 2 (bip) x 2 (Bipp) x 2x(Nmos) x 2 (Pmos)
X 2(ResCap) + Nominal = 97
5. Simulation Type = 3σ
Figure 36 : Bandgap Output Voltage across all Corners
Manraj Singh Gujral msg1g10 University of Southampton 31
Table 8 ΔV Values across all corners
Deviation from Mean
ΔV (negative) ΔV (Positive)
Best Corner ‐5.73m 0
Max. Positive Deviation Corner ‐20.5m 9.68m
Max. Negative Deviation Corner ‐14.8 3mV
Worst ΔV among Corners |ΔV/2| 53mV
General Industrial standard before trimming the output is 5% of absolute value. Our
Bandgap supplies a Raw voltage of 1.18V therefore a range of +/‐ 60 mV. We have a
deviation of +/‐ 53mV from the mean for worst case corners
Any further accuracy can be implemented by adding trimming circuits to the bandgap.
Figure 37 :Output Noise of the Bandgap (measured at Vref in figure1)
Table 9 Noise Values across all corners
Across All 96 Corners
Min Noise Typical Noise Max Noise units
at 1Hz 142 305.9 1385 nV/√Hz
at 10 kHz 92 101 114 nV/√Hz
Manraj Singh Gujral msg1g10 University of Southampton 32
Figure 38 : PSRR
Table 10 PSRR Values across all corners at 1 Hz
Max Typical Min units
‐121.7 ‐83 ‐76 dB
Figure 39 : The Bandgap starts working at about 1.3V. the corner simulations were tested for 1.5V
Manraj Singh Gujral msg1g10 University of Southampton 33
Figure 40 : Current Output from Bandgap
Figure 41 : BGR Output Currents corners
This Design was transferred from the current Rakon machine to the University system and a
sample run was performed with the University Models for tt, sf, ss at 1.6V , 1.8V and 2.0 V
(i.e., a total of 9 corners). The University wave is shown in Figure 42 below.
Manraj Singh Gujral msg1g10 University of Southampton 34
Figure 42 : BGR Output Currents for university corners
ΔV across all corners, for worst case = 5.9mV.
Manraj Singh Gujral msg1g10 University of Southampton 35
Chapter5:Layout&Extraction
5.1TheoryAfter we fixed a schematic design the next step is to Lay it out. In this exercise we continue
to use the tools by Cadence IC design Suite, and have used Cadence Layout XL. The Layout
techniques which have been listed below are techniques based on this specific layout and
each circuit will have its own priorities when laying it out.
1. In the Schematic of any Design there will be PMOSes and NMOSes closer to the VDD
and GND/VSS. A good tip to begin layout will be to move the PMOSes up and NMOSes
down.
Figure 43 Basic layout techniques attempted
2. In this exercise initial routing was done as per the standard practice of M1 and Metal
3 in Vertical and Metal 2 and Metal 4 in Horizontal , but later modified to reduce the use of
Metal 3 in the layout, thereby reducing the effective cost of fabrication. Although this is a
very small design, it highlights the use of designer’s choice in order to have the same layout
in different ways.
All the elements supposed to
be connected to VDD
All the elements supposed to
be connected to vss
Diode Connected Transistors in a 3x3
matrix
Manraj Singh Gujral msg1g10 University of Southampton 36
Figure 44 : Routing using Metal 3 in Revision 1 of Layout
Figure 45 : Routing reduced to Metal 2 in Revision 2 of Layout
Metal‐3 (Vertical)
Metal‐2 (Horizontal)
M3 – M2 Taps
Metal‐1 ( 0.75 µm Wide)
Metal‐1 (Horizontal)
Metal‐1 ( 0.35 µm Wide)
No Taps
Metal‐2 (Vertical)
Manraj Singh Gujral msg1g10 University of Southampton 37
Figure 46 : Routing using Metal 3 in Revision 1 of Layout, 2nd Example
Figure 47 : Routing using Metal 2 in Revision 2 of Layout, 2nd Example
This has enabled us to reduce a metal layer without increasing the area of the layout,
however one has to be careful while attempting to do this since it can cause routing
problems later in the Layout stage or might increase the metal track lengths to achieve the
same connection. Therefore it comes down to designer’s judgement.
3. The MIM Capacitor (metal‐insulator‐metal) is relatively small for the same
capacitance, therefore is a big advantage if looking for a smaller footprint.
M1 – M3 Taps
Metal‐3 (Vertical)
M1 – M2 Taps
Metal‐2 (Vertical)
Manraj Singh Gujral msg1g10 University of Southampton 38
(a)
(b)
Figure 48: Layouts (a) with 1pF MIM Capacitor, and (b) with 1pF vncap capacitor.
Therefore using this seems a much better option, without degrading the performance.
4. “Mimhk” type capacitors, unlike regular capacitor are formed on the top layers in
the process.
MIM Capacitor
vncap Capacitor
Manraj Singh Gujral msg1g10 University of Southampton 39
(a)
(b)
Figure 49: 1pF Capacitor used in the design (a) as a component (b) split up in different layers
This means that the space beneath the capacitors can be used to place the component.
Therefore this is the second advantage with this type of capacitor, that components using
up to M3 can be placed underneath it, thereby saving area.
Since this component uses the top two layers in a process, this also changes the wiring
scheme. Unlike conventional capacitor, this is not formed with poly‐gateoxide‐nWell but is
formed at the top level metals. Also the two terminal are supposed to be pulled from the
same highest layer, to prevent dielectric breakdown (9)
LAYER: E1
(dwg)
LAYER: MT (dwg)
Manraj Singh Gujral msg1g10 University of Southampton 40
Figure 50 A test circuit to be used for MIM Layout
Figure 51 Layout for a test circuit to be used for MIM Layout
Figure 46 and 47 explain the concept of wiring to MIM capacitor with a sample circuit.
5.2ExtractionThe bandgap was extracted and cleared for all the DRC, LVS and Floating Gate and NWell
Errors. The following figures shows the full laid out circuit and additional features
incorporated to clear all the design rules.
MT to E1 VIA before connecting
to VSS Pin
M1 to E1 (Through M2‐M3‐M4‐
MT layers) VIA for connecting to
the top Plate of the Capacitor
Manraj Singh Gujral msg1g10 University of Southampton 41
Figure 52 Extracted view of the Bandgap‐3. Size of 100x131µm2.
NWELL
Protective Diode
ConnectionVDD
Figure 53 NWELL Protection
NWELL
P Substrate
VDD
Reversed Biased Diode
VSS
Figure 54 NWELL Protection Schematic
Manraj Singh Gujral msg1g10 University of Southampton 42
P-Substrate Taps
Polysilicon Gate
Protection
Figure 55 Gate Protection
Size of the cell could further be reduced by about 5% to 10% with proper laying out of
components.
5.3CurrentSourcesfortheOutputStage1. Ideally, the currents coming out of the current mirrors are precise and Drain‐source
voltage independent. As the design moves towards more practical models these
non‐Ideal effects start to creep in and depending on the Output Nets voltage (and its
swings) the output current derived might not be as per theoretical calculations.
Figure 56 Output Stage current sources for the Bandgap Reference
Bandgap Voltage
Manraj Singh Gujral msg1g10 University of Southampton 43
2. In figure 11, we can see the outputs are labelled as :
a. vdd_10u
b. vdd_20u
c. vdd_40u
d. vdd_100u
These outputs were tested for constant VDD conditions. Depending on the usage of
these current references, e.g.: a Tail Current bias for an OpAmp, or an output Stage
Bias, etc., the desired accuracy will change and also the Voltage across these nMOS
devices will vary. Therefore these circuit level changes can either be acknowledged
and the required amount of accuracy in the output current can be implemented, or
less stringent accuracy levels can be accepted.
3. Possible ways to improve the accuracy :
a. One of the conventional ways would be to provide a high output impedance
for these current mirrors. Either by a cascode or using an enhancement type
MOS.
b. Adding extra resistor on the Source.
4. To finish the trial within the given time frame a considered decision was taken to
make changes in the Width of the Transistors , and leave out the other options
enumerated in Point 3 above. In order to match the output currents, parameterized
simulations of width were run to find out the approximate widths that would supply
the best output current over the entire Temperature range. The result is we have
Width ratios as:
a. W0:W1 = 2 : 2
b. W0:W2 = 2 : 3.9
c. W0:W3 = 2: 7.64
d. W0:W4 = 2: 18.9
Where W0, W1, W2, W3 and W4 are the corresponding widths of the
Transistors TN0, TN1, TN2, TN3, and TN4 in figure 1.
5. This meant that the conventional matching in the Interlocking Fingered way, as
shown in Figure 12 and Figure 13 wouldn’t work.
Figure 57 Conventional Inter fingered matching as DDCABCDD. Transistors A(TN0) and B(TN1) are of the same size.
Manraj Singh Gujral msg1g10 University of Southampton 44
Figure 58: Zoomed in view between TN2 TN0 highlighting the errors due to notches. Transistors A(TN0) and B(TN1) are of the same size. Scale shown in Microns
6. In conventional matching this would not be a problem since the Transistors sizes are
an integral multiple of each other and such notches are therefore avoided.
7. Since I had already made the schematic without realizing the Layout issues, I can
either make the Widths Integral multiples, for example W0:W4 = 2:20 instead of
2:18.9, or try to lay them compromising the effective matching.
8. I am currently working on a slightly unconventional Layout. Since the Lengths of all
the transistors are same, I plan to stack them vertically instead of horizontally.
Figure 59 Transistors Stacked on their Gates, instead of Drain and Sources
PolyPoly
RX RX
Since Transistor Lengths are constant. They have
been stacked vertically
Metal‐1
(Commo
n DRAIN
Or
SOURCE
)
Manraj Singh Gujral msg1g10 University of Southampton 45
The Matching technique for this design is described below, were we have 5 set of transistors
to match. Figure 60 and 61 presents the matching diagrams
Figure 60 Present Transistors Matching representation, A and A0 represent the same W/L Transistor
A
B
C
C
D
D
D
D
D
A0
B
C
C
D
D
D
D
D
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Figure 61 Another Matching scheme that can be used, A and A0 represent the same W/L Transistor
Using the same concept as in figure 60 we stack the transistors on top of each other and
connect the same transistor with their respective Vdd’s. A zoomed in version of the
matching used in this exercise is shown below in figure 62
Manraj Singh Gujral msg1g10 University of Southampton 46
Figure 62 Transistors Stacked on their Gates, instead of Drain and Sources
The overall layout of both the Current sources and the Band Gap are shown below in figure
63.
(a) (b)
Figure63: (a) Layout for Current Sources 17µm X 81µm, (b) placed alongside Bandgap Reference
Common Gate
Common Source Connection,
VSS
VRef
Vdd_10u
Vdd_20u
Vdd_40u
Manraj Singh Gujral msg1g10 University of Southampton 47
The layout of the Output current sources, Figure 63 (a), is made lengthwise also because it
can easily be stacked next to the main bandgap reference circuit. Although a much tighter
packing of these two structures was possible, it was not attempted to go beyond this
current one. Since the area is not a major concern in this exercise more emphasis was given
to the Matching and overall accuracy than the size.
The size of the Output current sources comes out to be 17µm X 81µm, and the size of the
Bandgap circuit is about 131µm X 100µm.
We will check these extracted models for their accuracy in the next chapter.
Manraj Singh Gujral msg1g10 University of Southampton 48
Chapter6:Schematicvs.ExtractedBandgapSimulations(withuniversitycorners)The following figures show the tests conducted for Schematic vs. Extracted bandgap circuits and compare the output to see it still matches the
specifications. The Test setup is shown below in figure 64
Figure64: Schematic vs. Extracted Circuit
Bandgap reference ‐
Schematic Bandgap reference ‐
Extracted
Current Sources ‐
Schematic
Current Sources ‐
Extracted
Voltage source (vdc_out) sweep to test
the output Impedence of the 10µA
current sources on both the schematic
and Extracted circuit
Manraj Singh Gujral msg1g10 University of Southampton 49
Figure 65 Output Voltage from ‐45 to 90 °C, with VDD varying from 1.6V to 2.1V
The maximum ∆Vout (across all waveforms = 5.9mV)
Figure 66 PSSR Wave from 1 Hz to 10G Hz.
Min ‐76.8dB, Max = ‐125dB
Manraj Singh Gujral msg1g10 University of Southampton 50
Figure 67 Output Noise Wave
Noise at 10k Hz = 101.9V, Noise at 1Hz = 308.53Hz
Figure 68 Quiescent Current
Manraj Singh Gujral msg1g10 University of Southampton 51
Figure 69 Output Currents for Simulated and Extracted circuits.
Table 11 Output Current Results (Units in µA)
(at 25°C) 100µA Source
40µA Source
20µA Source
10µA Source
Simulated 101.81 40.1 19.97 10.041
Extracted 94.78 38.3 19.57 10.041
Figure70: Output Impedance for Simulated and Extracted circuits. Worst Case 2.5MΩ
Manraj Singh Gujral msg1g10 University of Southampton 52
Chapter7:Summary
SpecificationComplianceMatrix
Table 12 Specification Compliance Matrix
Specification Simulation (Rakon Corners,96No.s)
Extracted (University Corners, 9 No.s)
Parameter Min Nom Max Min Nom Max Min Nom Max Units
Power supply, Vdd 1.7 1.8 1.9 1.6 1.8 2.0 1.6 1.8 2.0 V
Manraj Singh Gujral msg1g10 University of Southampton 53
Chapter8:NoiseAnalysis
A Noise producing elements pass on the noise to connected elements. The final output
noise of a system can be affected either by certain types of noise profiles, from certain types
of elements, or a noise producing element can affect the final system noise at particular
frequencies.
A typical connection of a BGR associated circuit is shown in figure 71.
Figure 71 : Typical Noise Producing Elements in an example system
The power supply noise can be expected to have an effect on the final oscillator noise. Since
the oscillator is connected to multiple units, such as the Crystal itself, the Control supply to
adjust the frequency of operation, and the LDO output the effect of the oscillator noise
might be different from different sources.
In this exercise we examine the effects of different noise sources on our main output.
Similar to the scheme shown figure 71, we will use a circuit equivalent in a schematic editor.
These are the actual circuits provided by Rakon UK Ltd. and the simulations were carried out
to understand the noise flow through their system. In this case the Bandgap was assumed to
be an Ideal Voltage source, i.e., with no Noise, and the remaining circuit was tested.
The purpose of the test was to analyze the circuit with different noise producing elements
and how it affects the final output noise.
Figure 72 shows the circuit under test where we use the Industrial LDO, Oscillator and its
oscillator control circuit.
This test bench is pre‐arranged so that the output frequency of the Oscillator = 26MHz.
Manraj Singh Gujral msg1g10 University of Southampton 54
Figure 72 Noise analysis circuit
Vcontrol
Manraj Singh Gujral msg1g10 University of Southampton 55
1. As a tool: In Cadence a Noise can be simulated by
a. Either placing noisy elements , such as a Resistor (for Flat band
Noise/Thermal Noise)
b. By placing MOS devices to add 1/f noise etc.
c. Uploading a Noise profile .txt file can be added onto an ideal voltage source
2. In the Initial test conducted Analogue library Sources were used to give us an
estimate of the performance of system in an Ideal case. This result can then be used
to compare the results obtained with actual Noisy elements.
(a) (b)
Figure 73 (a) Output Phase Noise of the Oscillator and (b) Periodic steady state of the Oscillator output.
a. Here the Noise at 1Hz = ‐62.4 dBc
b. Noise at 10kHz = ‐ 147 dBc
[dBc is the Noise w.r.t to the carrier frequency]
Manraj Singh Gujral msg1g10 University of Southampton 56
Vcontrol is the input to the Oscillator Tuning Circuit shown in figure 72, which is responsible
for setting the oscillator operating frequency. Keeping all other sources Ideal, a Noise profile
was added on top of Vcontrol and the Phase Noise at the output of the Oscillator was
measured.
Figure 74 Phase Noise due the addition of a typical Noise profile (/ravi/noise.txt1) on Vcontrol.
A difference of 5.18 dBs can be seen at 1 Hz frequency, in figure 74. This noise affects the
lower frequency (1/f) region of the noise slope.
Similarly a test for VLDO was performed , keeping every this else Ideal added to see the Noise
at the Oscillator output
Figure 75: Phase Noise due the addition of a typical Noise profile (/ravi/noisel.txt2) on LDO Output (fig 72).
1 noise.txt file was an actual noise profile for Control supplied by Mr Ravi , IC Design Engineer in Rakon 2 noisel.txt file was an actual noise profile for LDO supplied by Mr Ravi , IC Design Engineer in Rakon
Output Noise due
to noise in LDO
Output Noise due to
noise in the Control
Supply
Output Noise
performance of
the Oscillator due
to Ideal Voltage
Sources
Manraj Singh Gujral msg1g10 University of Southampton 57
In this case the Noise affects the higher frequencies region of the Noise slope. A difference
of almost 2 dB is observed between the Ideal case and the Noise addition at about 300kHz.
At this instance we are interested in finding out the region of slope at which the deviation
starts due to LDO Noise and due to Control Noise.
8.1LDOPhaseNoiseA series of simulation runs were carried out to see the affect of additional LDO Noise over
Ideal Source and corresponding frequency beyond which the effects were pronounced.
The typical Noise profile file for the LDO, noisel.txt was modified to have a range of noise
values. The values of Noise were changed so that the tests could be performed with
increasing severity of noise as:
Ideal Case, Noise, 10x Noise, 100xNoise and 1000xNoise.
A sweep of this was carried out to see the affect of these on the output performance.
Figure 76: Phase Noise profiles at the Output of the Oscillator. Each wave is represented by the Noise X
<value> in the same corresponding order.
This output performance was then analysed to see at what frequencies the deviation is
maximum. The Noisy waveforms were each subtracted from the ideal waveform to see their
differences w.r.t frequency.
Manraj Singh Gujral msg1g10 University of Southampton 58
Figure 77: Standard output Phase Noise for different profiles, and the difference of each wave from the ideal
one.
As can be seen from waveforms in Figure 77, the Effect of LDO Noise reaches a peak just
before 104 Hz and reaches a second peak just after 105Hz. These waves are the levels of
Noise over the ideal performance.
It can also be seen that the affect of LDO noise starts impacting as soon as 102Hz. At this
point there is a sharp rise in its value until it reaches the first peak.
Another set of waveforms is plotted which shows the rate of change of noise w.r.t the ideal
curve in figure 78. This helps us identify the place from where the noise starts to rise and
how fast.
Figure 78: a 2x Noise and 10xNose wave differential of noise (difference from the Ideal )wave .
It can be seen that the peak occurs between 102 and 103 Hz. After which, although the
absolute error remains, it starts to decelerate and after 104Hz becomes almost constant.
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Figure 79: : A summary of output phase noise performance for different LDO input noise levels.
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8.2ControlSupplyPhaseNoiseSimilarly Control Supply Phase Noise was added onto an ideal system to observe the
Oscillator output noise.
The levels of noise added can be seen in the waveforms below in figure 80. Similar to LDO
Phase Noise Analysis, a difference of Output Noise performance for different Control Supply
noise vs. the Ideal case were plotted to observe the relative magnitudes.
Here again, the Noisy waveforms were each subtracted from the ideal waveform to see the
difference between w.r.t frequency.
Figure 80: (top)Oscillator Output Phase noise for different levels of noise at control supply.
(bottom) Difference between output noise waves w.r.t Ideal wave
In this case, we can see that the Phase Noise on Control Supply affects the lower
frequencies more. The difference starts appearing at 1 Hz noise.
This difference then peaks between 102 and 103 Hz and begin to drop to almost 0 at about
105Hz.
Here also, we can see the rate at which the difference occurs, in figure 82 : The summary of
waveforms.
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Figure 81: A summary of output phase noise performance for different Ctrl input noise levels.
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From figure 81 it can be observed that the rate of change of Noise is maximum at lower
frequencies and the rate of change becomes almost constant beyond a few 100Hz.
8.3Experiment‐1:LowPassFilterA small experiment was carried out based on the findings of figure 13 to try and reduce the
output noise from LDO by passing it through a low‐pass filter. The highest rate at which the
error starts to pick up lies at very low offset frequencies, in the region of 10Hz.
Ideal Voltage Source
Oscillator
Ctrl Supply
Oscillator Output + noise
+
filter
Figure 82: an experimental setup by adding a filter in front of the Ctrl supply noise
Now since the control supply voltage source, with its specific Noise Profile, affects at low
offset frequencies, a Low Pass filter, for these low frequencies were added to see if the
noise can be further removed.
Figure 83: Waveforms for Output Phase Noise of the Oscillator with Low Pass filter at the input Ctrl Supply line
Although the noise is pulled closer to the Ideal curve, the value of capacitance and
resistance involved increased quite significantly. The capacitance values, marked in circles,
increase to very high values in scales of nF.
Ideal Noise Profile of
the Oscillator
Noise Profile without a
Filter
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8.4LDOandControlSupplyPhaseNoiseRegionsAt this point another set of tests were performed to see at which frequencies (or a range of
frequencies) the effect of LDO Noise and Control supply noise begins to impact the
Oscillator Output Phase Noise.
If we get an idea at what range of frequencies below certain level only Control supply Noise
affects more , and above a certain frequency LDO Noise Starts to dominate we can adjust
the noise performance of these units accordingly, to give an overall Oscillator Output noise
which is controllable.
Figure 84: Oscillator O/P Phase Noise waves for Ctrl voltage source noise from Ideal to 1000 Times its std noise
profile & LDO Source Noise from Ideal to 1000 Times the std noise Profile.
In this bunch of waves, we have the control supply noise affecting at lower frequencies, and
LDO supply noise affecting at higher frequencies. We intend to find out the tipping point
where the dominance of Ctrl Supply ends and LDO noise beings.
For this we subtract the noise due to Ctrl Supply from the noise due to LDO supply and see
the difference.
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Figure 85: Output Phase Noise dominance between Ctrl Supply and LDO supply.
From figure 85 a clear point on frequency scale can be seen between 30kHz and 40kHz
where the Noise due to Ctrl Supply and LDO becomes almost equal, and hence their
difference becomes zero.
It can be inferred that if the Oscillator output Noise is to be targeted for lower offset
frequencies ‐then the adjustments in Control supply will have a higher impact. Similarly, if
the target is at higher offset frequencies beyond 30kHz then the LDO circuit will have a
higher impact.
Ctrl Supply
Dominance
LDO supply
dominance
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Chapter9:Conclusion
A thorough description of bandgap principles were discussed and critical components used
in analogue and mixed signal designs were look at . Several important tests were carried out
to understand the parameters in these building blocks and how these could be tailored to
meet a designer’s needs. The results of these tests were used to design a Bandgap circuit
which went through a design cycle keeping the required specification in mind.
A low Noise Bandgap circuit was developed and simulated for stringent Industrial Corners,
supplied by Rakon UK Ltd., as well as University specified corners for the same IBM7WL
process. The lowest noise levels achieved were in the range of 100nV/√Hz and the accuracy
matched the specifications. A detailed compliance matrix is shown in Chapter 7, Table 12.
9.1ScopeofImprovement Although the Bandgap reaches the target specification in terms of Noise
Performance which is industrially acceptable, it can be lowered even further by using ΔVBE
Techniques. ΔVBE stacking theory explains the concept in making a bandgap relying less on
the Resistances and using the property of Bipolar, which are low noise devices, to attain the
same Reference voltage.
This concept is also presented in a Thesis by Mr William T Holman (7) on which several
patents have also been filed, for example Sander Gierkink Patent(8).
The output performance of a Bandgap is usually accepted if it performs at an output
of +/‐5% of reference Voltage. This 5% deviation is then adjusted through trimming circuits.
Usually in the topology that has been presented in Bandgap‐3, section 3.3 in Figure 32,
these trimming circuits would be applied to the resistance values so as to enable the taped‐
out chip to have control over output voltage. These resistance values can be adjusted to
finally allow a very high degree of accuracy even in the worst case corner. Also trimming
circuits can be used to regulate the output supply. (10)
These features on top of a low noise bandgap circuit can provide a low noise, highly
accurate, user specific voltage reference.
The Output Resistance of the Current Mirrors at the output stage of the Bandgap,
Chapter 5.3 Figure 56, can be further increased by using Cascode as shown in Chapter 2.2
Figure 19 and Figure 20. That would need a Bias Circuitry to go along with it. Although a
Cascode would mean a headroom problems with minimum VDD. This can be worked around
with low voltage cascades and also because we see a head room of about 0.3 V as shown in
the Chapter 4: Corner Simulations for Bandgap‐2, Figure 39.
During Layout, although Common centroid techniques were used to minimize the
mismatch, Dummy structures were not placed due to time constraint. Considering we need
very high matching in this Bandgap it is advisable to implement the dummy structures.
Manraj Singh Gujral msg1g10 University of Southampton 66
Section 5.3, Figure 61 and 62, explains some of these concepts but were not implemented in
this design.
These are some of the obvious scopes of improvements which can be implemented to this
circuit.
References1. Sansen, Willy. Bandgap and current reference circuits. [book auth.] Willy M.C. Sansen. Analog Design
Essentials. Catholic University , Leuven Belgium : Springer, 2006.
2. Zenhbroeck, B. Van. Chapter2: Semiconductor Fundamentals. Principles of Semiconductor Devices. s.l. :
Department of Electrical , computer and Energy Engineering, University of Colorado at Boulder, 2011.
3. Behzad Razavi, Design of Analog CMOS Integrated Circuits, Chapter 11 Bandgap References. s.l. : TATA
McGraw‐Hill, 2002.
4. IBM Corporation. BiCMOS‐7WL Model Reference Guide. 2011, Vol. V1.8.1.0, 11.4. Page 183.
5. Redman‐White, Prof. W. Analogue & Mixed Signal CMOS Design. s.l. : Dept. of Electronics and Computer
Science, University of Southampton, 2011.
6. Aylward, Kevin. Low Area, Low Power Startup Circuit. Analogue Design, Kevin Aylward, B.Sc.,. [Online]
October 2006. http://www.kevinaylward.co.uk/ee/zeropowerstartup/zeropowerstartup.html.
7. IBM Corporation. IBM Design Manual. ES#70P3341 BiCMOS7WL Design Manual. 25 January 2011.
8. Holman, William Timothy. A Low Noise CMOS Voltage Reference. Georgia Institute of Technology , USA.
1994. p. 176.
9. Gierkink, Sander. Low Noise Bandgap. US007242240B2 USA, 10 July 2007. United States Patent.
10. IBM Corporation. BiCMOS 7WL Training Manual. 2007, Vol. Revision 6.2, p. 309. Page 52.
11. Martinez Brito, J.P. Bampi, S. Klimach, H. Kimach, A 4‐Bits Trimmed CMOS Bandgap Reference with an
Improved Matching Modeling Design.. June 2007, IEEE International Symposium on Circuits and Systems, 2007