Design of Accelerators with Constraints Design of Processor Accelerators with Constraints Christophe Wolinski 1 , Krzysztof Kuchcinski 2 , Kevin Martin 3 , Erwan Raffin 3,4 and François Charot 3 1 Rennes University I/IRISA, France 2 Dept. of Computer Science, Lund University, Sweden 3 INRIA, Centre Rennes-Bretagne Atlantique, France 4 Thomson R&D, Rennes, France Wolinski & Kuchcinski 1(19)
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Design of Processor Accelerators with Constraints · Design of Accelerators with Constraints Design of Processor Accelerators with Constraints Christophe Wolinski1, Krzysztof Kuchcinski2,
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Design of Accelerators with Constraints
Design of Processor Accelerators with Constraints
Christophe Wolinski1, Krzysztof Kuchcinski2,Kevin Martin3, Erwan Raffin3,4 and François Charot3
1Rennes University I/IRISA, France2Dept. of Computer Science, Lund University, Sweden
/* Sample C code */ void fir(const int x[], const int h[], int y[]) { int i, j, sum; for (j = 0; j < 100; j=j+1) { sum = 0; for (i = 0; i < 8; i=i+1) sum += x[i + j] * h[i]; sum = sum >> 15; y[j] = sum; } }
Identification of computational patterns for instructionsSelection of a subset of instructions for implementationSequential or parallel execution scenariosPattern merging to build reconfigurable cell
Goal:Get speed-up of an application with minimal hardware cost.
Wolinski & Kuchcinski 4(19)
Design of Accelerators with Constraints
Main Problems
Identification of computational patterns for instructionsSelection of a subset of instructions for implementationSequential or parallel execution scenariosPattern merging to build reconfigurable cell
Goal:Get speed-up of an application with minimal hardware cost.
Other standard constraints (number of inputs/outputs, criticalpath, etc.)Methods based on constraints
Pattern generation- purely based on constraintMatch identificationPattern selection and schedulingPattern merging
Wolinski & Kuchcinski 6(19)
Design of Accelerators with Constraints
Pattern Generation
n0 n1 n2
nsn3
n4
n5
n6 n7
n8
Pattern 3 inputs2 outputs
allsucc(Ns) = {n4,n5,n6,n7,n8}
Seed node
∀n ∈ Np ∧ n 6= ns ∃path(Pns , n, ns)
∀n ∈ (N − (allsucc(ns) ∪ ns)) : nsel = 1 ⇒X
m∈succ(n)
msel ≥ 1
∀n ∈ (N − (allsucc(ns) ∪ ns)) :X
m∈succ(n)
msel = 0⇒ nsel = 0
∀n ∈ allsucc(ns) : nsel = 1 ⇒X
m∈(pred(n)∩(allsucc(ns )∪ns ))
msel ≥ 1
∀n ∈ allsucc(ns) :X
m∈(pred(n)∩(allsucc(ns )∪ns ))
msel = 0 ⇒ nsel = 0
Wolinski & Kuchcinski 7(19)
Design of Accelerators with Constraints
Pattern Generation
n0 n1 n2
nsn3
n4
n5
n6 n7
n8
Pattern 3 inputs2 outputs
allsucc(Ns) = {n4,n5,n6,n7,n8}
Seed node
∀n ∈ Np ∧ n 6= ns ∃path(Pns , n, ns)
∀n ∈ (N − (allsucc(ns) ∪ ns)) : nsel = 1 ⇒X
m∈succ(n)
msel ≥ 1
∀n ∈ (N − (allsucc(ns) ∪ ns)) :X
m∈succ(n)
msel = 0⇒ nsel = 0
∀n ∈ allsucc(ns) : nsel = 1 ⇒X
m∈(pred(n)∩(allsucc(ns )∪ns ))
msel ≥ 1
∀n ∈ allsucc(ns) :X
m∈(pred(n)∩(allsucc(ns )∪ns ))
msel = 0 ⇒ nsel = 0
Wolinski & Kuchcinski 7(19)
Design of Accelerators with Constraints
Pattern Generation
n0 n1 n2
nsn3
n4
n5
n6 n7
n8
Pattern 3 inputs2 outputs
allsucc(Ns) = {n4,n5,n6,n7,n8}
Seed node
∀n ∈ Np ∧ n 6= ns ∃path(Pns , n, ns)
∀n ∈ (N − (allsucc(ns) ∪ ns)) : nsel = 1 ⇒X
m∈succ(n)
msel ≥ 1
∀n ∈ (N − (allsucc(ns) ∪ ns)) :X
m∈succ(n)
msel = 0⇒ nsel = 0
∀n ∈ allsucc(ns) : nsel = 1 ⇒X
m∈(pred(n)∩(allsucc(ns )∪ns ))
msel ≥ 1
∀n ∈ allsucc(ns) :X
m∈(pred(n)∩(allsucc(ns )∪ns ))
msel = 0 ⇒ nsel = 0
Wolinski & Kuchcinski 7(19)
Design of Accelerators with Constraints
Pattern Generation
n0 n1 n2
nsn3
n4
n5
n6 n7
n8
Pattern 3 inputs2 outputs
allsucc(Ns) = {n4,n5,n6,n7,n8}
Seed node
∀n ∈ Np ∧ n 6= ns ∃path(Pns , n, ns)
∀n ∈ (N − (allsucc(ns) ∪ ns)) : nsel = 1 ⇒X
m∈succ(n)
msel ≥ 1
∀n ∈ (N − (allsucc(ns) ∪ ns)) :X
m∈succ(n)
msel = 0⇒ nsel = 0
∀n ∈ allsucc(ns) : nsel = 1 ⇒X
m∈(pred(n)∩(allsucc(ns )∪ns ))
msel ≥ 1
∀n ∈ allsucc(ns) :X
m∈(pred(n)∩(allsucc(ns )∪ns ))
msel = 0 ⇒ nsel = 0
Wolinski & Kuchcinski 7(19)
Design of Accelerators with Constraints
Pattern Generation (cont’d)
DIPS ← ∅for each ns ∈ N
TPS ← ∅CPS ← FindAllPatterns(G, ns)for each p ∈ CPS
if ∀pattern ∈ TPS : p 6≡ patternTPS ← TPS ∪ {p},NMPp ← | FindAllMatches(G, p) |
NMPns ← | FindAllMatches(G, ns) |for each p ∈ TPS
if coef · NMPn ≤ NMPpDIPS ← DIPS ∪ {p}
return DIPS
Wolinski & Kuchcinski 8(19)
Design of Accelerators with Constraints
Pattern Selection
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// Inputs: G=(N,E)-- application graph,// DIPS-- Definitively Identified Pattern Set// Mp-- set of matches for pattern p,// M-- set of all matches,// matchesn-- set of matches that could cover the node n,
M ← ∅for each p ∈ DIPS
Mp ← FindAllMatches(G, p)M ← M ∪ Mp
for each m ∈ Mfor each n ∈ m
matchesn ← matchesn ∪ {m}
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Wolinski & Kuchcinski 9(19)
Design of Accelerators with Constraints
Pattern Selection
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// Inputs: G=(N,E)-- application graph,// DIPS-- Definitively Identified Pattern Set// Mp-- set of matches for pattern p,// M-- set of all matches,// matchesn-- set of matches that could cover the node n,
M ← ∅for each p ∈ DIPS
Mp ← FindAllMatches(G, p)M ← M ∪ Mp
for each m ∈ Mfor each n ∈ m
matchesn ← matchesn ∪ {m}
m0 m1 m9n0n
*
all matches
all n
od
es n2
m2m3 m4m5 m6m7m8
n5
n3n4
n1
n6
* * * * * *
***
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Wolinski & Kuchcinski 9(19)
Design of Accelerators with Constraints
Pattern Selection
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*4
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+10
*5
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*6
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+11
*7
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+26
+12 +13
+27
*14 *16 *17*15
+18 +19
*22 *20 *21*23
+24+25
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// Inputs: G=(N,E)-- application graph,// DIPS-- Definitively Identified Pattern Set// Mp-- set of matches for pattern p,// M-- set of all matches,// matchesn-- set of matches that could cover the node n,
Constraint makes it possible to explore solutions that is difficultto examine using specific algorithms.Constraints provide flexibility of defining different conditions.(Sub-)graph isomorphism constraints offer easy way to definedesign problems.Experimental results are very encouraging.
Wolinski & Kuchcinski 18(19)
Design of Accelerators with Constraints
Further Reading
Ch. Wolinski and K. Kuchcinski.Automatic selection of application-specific reconfigurable processorextensions.In Proc. Design Automation and Test in Europe, Munich, Germany, March10-14, 2008.
Ch. Wolinski, K. Kuchcinski, K. Martin, E. Raffin, and F. Charot.How constrains programming can help you in the generation of optimizedapplication specific reconfigurable processor extensions.In Proc. of The Intl. Conference on Engineering of Reconfigurable Systemsand Algorithms, Las Vegas, USA, (Invited paper), July 13-16, 2009.
K. Martin, Ch. Wolinski, K. Kuchcinski, A. Floch, and F. Charot.Constraint-driven identification of application specific instructions in theDURASE system.In SAMOS IX: International Workshop on Systems, Architectures, Modelingand Simulation, Samos, Greece, July 20-23, 2009.