DESIGN OF POWER EFFICIENT DIFFERNTIAL AMPLIFIER USING 1 …

ISSN 2277-2685 IJESR/August 2019/ Vol-9/Issue-8/1-7 Naveen IG et. al., / International Journal of Engineering & Science Research

*Corresponding Author www.ijesr.org 1

DESIGN OF POWER EFFICIENT DIFFERNTIAL AMPLIFIER USING 1 UM AND 180 NM TECHNOLOGY

Naveen IG*1, Dr. Savita Sonoli2 1Asst. Prof, Dept. of ECE, Sir M.V.I.T, Bangalore, India.

2Prof & Head, Dept of ECE, RYMEC, Ballari , India.

ABSTRACT

Differential amplifiers play a very important role in the analog circuit design because of their excellent performance as input amplifiers and the straightforward application with the possibility of feedback to the input. The classical differential amplifier faces the disadvantage of the nonlinearity of the transfer characteristic, especially for large values of the differential input voltage amplitude. The differential amplifier circuit characterized in terms of self-bias capability, common-mode rejection, voltage gain, and the gain-bandwidth product. In this paper we report a new model forpower efficient and high performance CMOS differential amplifier. The proper selection of device parameters has been playing an important role in the design of differential amplifier. The Circuit is designed using 1um and 180nm CMOS/VLSI technology with Cadence virtuoso tool.

Keywords: Common Differential Amplifier, Differential pair, CMRR, Trans conductance, Current Sink.

1. INTRODUCTION

The differential amplifier is one of the most versatile circuits used in analog circuit design. These are widely used in the electronics industry and are generally preferred over their single-ended counterparts because of their better common-mode noise rejection, reduced harmonic distortion, and increased output voltage swing [1-3]. Differential amplifiers are used to amplify analog as well as digital signals, and can be used in various implementations to provide an output from the amplifier in response to differential inputs. It is also very compatible with integrated circuit technology and serves as the input stage to most of operational amplifier [3-7]. They can be readily adapted to function as an operational amplifier, a comparator, a sense amplifier and as a front-end buffer stage for another circuit.

The differential amplifier is often a building block or sub-circuit used within high-quality integrated circuit amplifiers, linear and nonlinear signal processing circuits, and even certain logic gates and digital interfacing circuits. In recent years, there has been an increasing demand for a system-on-chip configuration (SOC) and reduction of power consumption, in response to which the CMOS has been widely used [4, 8, 9-11].

CMOS differential amplifiers are used for various applications because a number of advantages can be derived from these types of amplifiers, as compared to single-ended amplifiers. Differential amplifiers are used where linear amplification having a minimum of distortion is desired. A fully differential amplifier circuit is a special type of amplifier that has two inputs and two outputs. This device amplifies input signals on the two input lines that are out of phase and rejects input signals that have a common phase such as induced noise. The common mode feedback is accomplished by the use of a common mode feedback circuit that monitors the two differential amplifier output lines and provides a feedback signal that adjusts the amplifier's bias current, thereby rejecting the unwanted common mode signals on the amplifier's output.

The sensitivity is an important specification target for differential amplifier design. Component is matching and their drift induces the extra output differential voltage, which is indistinguishable from the signal being processed. The extra output differential voltage limits the minimum detectable differential voltage level. Also, such mismatching could convert the common mode input signal to the differential output, which is treated as the desired signal by the subsequent stages.

Naveen IG et. al., / International Journal of Engineering & Science Research

Copyright © 2019 Published by IJESR. All rights reserved 2

Fig. 1: Differential Amplifier Symbol

2. CIRCUIT DESCRIPTION

It is an analog circuit with two inputs and and one output in which the output is ideally proportional to the difference between the two voltages.

Vout = A( V+ - V-) --------------------------(1)

A = Gain of amplifier

The objective of the differential amplifier is to amplify only the difference between two different potentials regardless of common mode value. It is characterized by its CMRR and its offset voltage. In ideal differential amplifier, the common mode gain should be zero and thus CMRR should be infinite, also the input offset voltage should be zero [12, 13, 14, 15, 17].

In real differential amplifier, the output offset voltage is the difference between the actual output voltage and the ideal output voltage when the input terminals are connected together. If this offset voltage is divided by the differential voltage gain of the differential amplifier then it is called the input offset voltage. Figure 1, shows the basic differential amplifier that uses n-channel MOSFETs M1 and M2 to form a differential amplifier. M1 and M2 are biased with a current sink Iss connected to the sources of M1 and M2.This configuration of M1 and M2 is often called a source-coupled pair. The current sink Iss is implemented using M5 an M6.

The transistors M1 & M2 are perfectly matched and always worked in saturation region

3. DESIGN STEPS

(1) Design of Differential amplifier starts with listing the given parameters.

· Slew Rate(SR) = 5V/µs

· VDD = 1.8V

· Av ≥ 100, i.e. 40 dB

· CL = 10pF

· ICMR+ = 1.6V

· ICMR- = 0.8v

· Power Dissipation(PD) = < 0.3mW

· GBW = 5MHz

· µn*Cox = 300µ

· µp*Cox = 60µ

· Vthn = 0.45V

· Vthp = -0.5V



(2) Now draw the rough structure of differential amplifier and name the MOSFETS.

Calculate the ‗Id‘ current using formula ID = SR/ CL ---------------------(2)

(3) Using ICMR+ calculate Vgs of PMOS.

(4) Using Id and µn*Cox, Vgs and Vth calculate the (W/L) ratio of pMOS‘s i.e M3and M4.

(5) Now calculate Gm of nMos M1 and M2 using formula Gm =GBW/ 2ΠCL -----------(3)

(6) Using above Gm calculate (W/L) ratio of nMos i.e M1 and M2 using below formula

(W/L) = Gm 2 / 2 ID µn Cox ------------------(4)

(7) Using ICMR- calculate Vdsat of M5.

(8) Using Vdsat in below formula calculate (W/L) of M5 and M6

(W/L) = 2 ID / µn Cox Vds 2 --------------------(5)

(9) Finally round-off the decimal values to near upper integer values

Fig. 2: Differential amplifier Schematic

4. SIMULATION RESULTS

The transient response for differential Amplifier is shown in figure 3 and figure 4 for 1u am and 180 nm technology respectively. This result shows the voltage at input terminal (V2) is amplified at output terminal Vout in differential mode and in common mode it is almost zero which shows that the amplifier has very high CMRR.

The ac analysis plots the input and output noise of the circuit as shown in figure 5and figure 6. This result shows that the circuit works properly up to 10 KHz frequency and 100 Khz frequency for 1um and 180 nm technology respectively. After this frequency the performance of circuit is poor.

AC gain for 1um technology is 41.1268dB and for 25.4897dB for 180 nm technology.



Figure 6 and figure 7 shows the Power dissipation in differential amplifier for 1 um and 180 nm technology. The static power dissipation is 32.225µW and 32.230µW for 1um and 180 nm technology respectively. The dynamic power dissipation is 100.246 µW and 100.225 µW for 1um and 180 nm technology respectively.

The differential mode curve is linear for input voltage between -3.14 volts to +3.14 volts. So the present circuit is suitable for low voltage applications, where as in common mode configuration the graph is non linear and noisy but in the range of nano volts. This shows that in common mode configuration, the output voltage is very small which also confers that the CMRR is very high. So this circuit can be used in design of low voltage high CMRR operational .amplifier.

Fig. 3: Transient Response for 1 um technology

Fig. 4: Transient Response for 180nm technology



Fig. 5: AC Analysis for 1 um technology

Fig. 5: AC Analysis for 180 um technology

Fig. 6: Power Dissipation for 1 um technology



Fig. 7: Power Dissipation for 180 nm technology

The differential amplifier is designed for 1 um and 180 nm technology table shows the comparison between both the technology for various design parameters.

Table 1: Comparison between 1 um and 180 nm technology

Parameter 1µm Technology 180nm Technology (W/L)1,2 7 4 (W/L)3,4 84 52 (W/L)5,6 9 14 Vin 200µv Peak-Peak 200µv Peak-Peak Vout 7376.6µv 3318.6µv Gain 41.1268dB 25.4897dB Dynamic Power dissipation

100.246µW 100.225µW

Static Power dissipation 32.225µW 32.230µW

5. CONCLUSION

In this paper a power efficient CMOS differential amplifier circuit has been proposed using 1um and 180nm technology. This circuit best suited for low power,low voltage and high common mode rejection ratio (CMRR) applications. The circuit can be used in design of low voltage and CMRR operational amplifiers, Operational transconductance amplifiers, Voltage controlled oscillators (VCO).

REFERENCES

[1] Sackinger E, Guggenbuhl W. Design of Fully Differential CMOS Amplifier for Clipping Control Circuit. World Applied Science Journal 2008; 3(1) 110-113.

[2] Popa C. Linearity Evaluation Technique for CMOS Differential Amplifier. Proc. 26th International Conference on Microelectronics (MIEL 2008), NIŠ, SERBIA, 11-14 MAY, 2008.

[3] Chi Baoyong HS, Zhihua W. A Novel Off set2Cancellation Technique for Low Voltage CMOS Differential Amplifiers. Chines ournal of semiconductors 2006; 27(5): 778-782.

[4] Grasso AD, Pennisi S. High-Performance CMOS Pseudo-Differential Amplifier. Circuits and Systems, ISCAS 2005. IEEE International Symposium on, 23-26 May 2005; 1569 – 1572.

[5] Liu Z, Bian C, Wang Z. Full Custom Design of a Two-Stage Fully Differential CMOS Amplifier with High Unity-Gain Bandwidth and Large Dynamic Range at Output. 48th IEEE International Midwest Symposium on



Circuits and Systems, Cincinnati, Ohio, U.S.A., 7-10 August, 2005.

[6] Butkovic Z, Szabo A. Analysis of the CMOS Differential Amplifier with Active Load and Single-Ended Output. IEEE MELECON, May, 12-15, 2004; 417-420.

[7] Corsi F, Marzocca C. An Approach to the Analysis of the CMOS Differential Stage with Active Load and Single-Ended Output. IEEE Trans. Educ. 2003; 46: 325-328.

[8] Sun R, Peng L. A gain-enhanced two-stage fully-differential CMOS op amp with high unity-gain bandwidth. Proc. IEEE International Symposium on Circuits and Systems 2002; 2: 428–431.

[9] Jiang R, Tang H, Mayaram K. A Simple and Accurate Method for Calculating the Low Frequency Common-Mode Gain in a MOS Differential Amplifier with a Current-Mirror Load. IEEE Transactions on Education 2000; 43(3): 362-364.

[11] Salama KN, Soliman AM. CMOS operational transresistance amplifier for analog signal processing. Microelectronics Journal 1999; 30(9): 235-245.

[12] Chen JJ, Tsao HW, Chen CC. Operational transresistance amplifier using CMOS technology. Electronics Letters 1992; 28(22): 2087-2088.

[13] Hosticka BJ. Improvement of the Gain of CMOS Amplifiers. IEEE Journal of Solid-State Circuits 1996; SC-14(6): 1111-1114.

[14] Razavi B. Design of analog CMOS Integrated circuits, McGraw-Hill, New Delhi 2002.

[15] Allen PE, Holberg DR. CMOS analog circuit Design, II edition, Oxford University Press, New York 2002.

[16] Maloberti F. Analog Design for CMOS VLSI Systems, Kluwer Academic Publishers, New York 2001.

[17] Tsividis YP. Operation and Modeling of MOS Transistor, McGraw-Hill 1987.

[18] Sedra AS, Smith KC. Microelectronic Circuits, 4th ed.,Oxford University Press, 1998.

[19] Gray PR, Hurst PJ, Lewis SH, Meyer RG. Analysis and Design of Analog Integrated Circuits, 4th ed., John Wiley & Sons, 2001.

[20] Tiwari RK, Mishra GR. Simulation Studies of CMOS current Mirror, presented in National Seminar on “Nano-Bio and Information Technology Integration organized by SIEM Mathura, India, March 2007.

[21] Tiwari RK, Mishra GR. A comparative study of CMOS and BJT Current Mirror Circuit. Bulletin of Pure and applied Sciences 2008; 27D (1): 47-53.

DESIGN OF POWER EFFICIENT DIFFERNTIAL AMPLIFIER USING 1 …

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