Page 844 Design of Performance Adiabatic Dynamic Differential Logic (PADDL) for Secure Integrated Circuits Venkata Lakshmi B M.Tech D.Rajendra Prasad Assistant Professor Abstract: In the modern world secure data transfer and privacy is becoming a major problem. Smart cards and other embedded devices use an encryption technology for secure data transfer. To design successful security- centric designs, the low-level hardware must contain built-in protection mechanisms to supplement cryptographic algorithms, such as advanced encryption standard and triple data encryption standard by preventing side-channel attacks, such as differential power analysis (DPA). Dynamic logic obfuscates the output waveforms and the circuit operation, reducing the effectiveness of the DPA attack. For stronger mitigation of DPA attacks, we proposed this design and analysis using high-performance adiabatic dynamic differential logic (PADDL) for secure integrated circuit (IC) design. Such an approach is effective in reducing power consumption. Index Terms: Adiabatic logic, differential power analysis (DPA) attacks, forward body biasing, reversible logic. I. INTRODUCTION: SMART cards are small integrated circuits (ICs) embedded onto plastic or tokens, and are used for authentication, identification, and personal data storage. They are used by the military, in automatic teller machines, mobile phone subscriber identity module cards, by schools for tracking class attendance, and storing certificates for use in secure web browsing. They are also used internationally as alternatives to credit and debits cards by Euro pay, MasterCard, and Visa. They are application specific, so their size and software overhead may be minimized. In addition, smart cards use tamper-resistant secure file cryptosystems. They are more difficult to forge than tokens, money, and government-issued identification cards. They can be programmed to deter theft by preventing immediate reuse, making them more effective than cards with magnetic strips. Due to their emphasis on security at both the software and hardware levels, smart-card technology is emerging as the platform of choice in key vertical markets. Smart- card technology is moving toward multiple applications, higher interoperability, and multiple interfaces, such as TCP/IP, near-field communicators, and contactless chips. Due to their recent proliferation, smart cards are targets of attacks motivated by identity theft, fraud, and fare evasion. Despite their secure software design, smart cards may still be susceptible to side-channel attacks, which are based on correlations of leaked secondary information and the IC output signals. In smart cards, these include electromagnetic emanations (EM leakage), measuring the amount of time required to perform private-key operations, and analysis of noisy power consumption. One of the most effective attacks is a differential power analysis (DPA) attack, where the attacker analyzes the power consumption in the IC and compares it to the ICs output signals. The leaked side-channel information is due to the presence of entropy gain in the system.
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Page 844
Design of Performance Adiabatic Dynamic Differential Logic
(PADDL) for Secure Integrated Circuits
Venkata Lakshmi B
M.Tech
D.Rajendra Prasad
Assistant Professor
Abstract:
In the modern world secure data transfer and privacy is
becoming a major problem. Smart cards and other
embedded devices use an encryption technology for
secure data transfer. To design successful security-
centric designs, the low-level hardware must contain
built-in protection mechanisms to supplement
cryptographic algorithms, such as advanced encryption
standard and triple data encryption standard by
preventing side-channel attacks, such as differential
power analysis (DPA). Dynamic logic obfuscates the
output waveforms and the circuit operation, reducing
the effectiveness of the DPA attack. For stronger
mitigation of DPA attacks, we proposed this design
and analysis using high-performance adiabatic
dynamic differential logic (PADDL) for secure
integrated circuit (IC) design. Such an approach is
effective in reducing power consumption.
Index Terms:
Adiabatic logic, differential power analysis (DPA)
attacks, forward body biasing, reversible logic.
I. INTRODUCTION:
SMART cards are small integrated circuits (ICs)
embedded onto plastic or tokens, and are used for
authentication, identification, and personal data
storage. They are used by the military, in automatic
teller machines, mobile phone subscriber identity
module cards, by schools for tracking class attendance,
and storing certificates for use in secure web browsing.
They are also used internationally as alternatives to
credit and debits cards by Euro pay, MasterCard, and
Visa. They are application specific, so their size and
software overhead may be minimized. In addition,
smart cards use tamper-resistant secure file
cryptosystems. They are more difficult to forge than
tokens, money, and government-issued identification
cards. They can be programmed to deter theft by
preventing immediate reuse, making them more
effective than cards with magnetic strips. Due to their
emphasis on security at both the software and
hardware levels, smart-card technology is emerging as
the platform of choice in key vertical markets. Smart-
card technology is moving toward multiple
applications, higher interoperability, and multiple
interfaces, such as TCP/IP, near-field communicators,
and contactless chips.
Due to their recent proliferation, smart cards are
targets of attacks motivated by identity theft, fraud,
and fare evasion. Despite their secure software design,
smart cards may still be susceptible to side-channel
attacks, which are based on correlations of leaked
secondary information and the IC output signals. In
smart cards, these include electromagnetic emanations
(EM leakage), measuring the amount of time required
to perform private-key operations, and analysis of
noisy power consumption. One of the most effective
attacks is a differential power analysis (DPA) attack,
where the attacker analyzes the power consumption in
the IC and compares it to the ICs output signals. The
leaked side-channel information is due to the presence
of entropy gain in the system.
Page 845
These attacks are effective, since most modern
computing technology is CMOS based, and the power
consumption tendencies of these devices are well
studied. Reducing the power consumption of the
circuit makes a DPA attack more difficult. Reversible
logic is a promising design paradigm for the
implementation of ultralow power computing
structures with minimal entropy gain. This is because
quantum mechanics principles govern the physical
limitations of computing devices. These systems
dissipate energy due to bit erasure within their
interconnected primitive structures, which is an
important consideration as transistor density increases.
Adiabatic logic is an implementation of reversible
logic in CMOS where the current flow through the
circuit is controlled such that the energy dissipation
due to switching and capacitor dissipation is
minimized. This is accomplished by recycling circuit
energy rather than dissipating it into the surrounding
environment.
This is beneficial for CMOS implementations, since
the input and output charges are kept separate.
Adiabatic logic implementations of CMOS have been
used to improve power consumption in comparison to
pass transistor logic. In this paper, we propose the use
of body-biased adiabatic dynamic differential logic
(BADDL) for reducing the effectiveness of DPA
attacks on CMOS-based secure IC devices. In Section
II, we present the motivation and background for low-
power secure IC design. First, the methods for
implementing a DPA attacks are discussed. Next, we
review the benchmarks of previous methods of
mitigating these attacks, such as wave differential
dynamic logic (WDDL) and secure differential
multiplexer logic using pass transistors (SDMLp) and
a taxonomy of previous works is provided in Fig. 1. In
Section III, we present design and analysis using high-
performance adiabatic dynamic differential logic
(PADDL) for mitigating DPA attacks, which is a novel
universal cell that performs AND, NAND, OR, NOR,
XOR, and XNOR operations.
The average power, instantaneous power, and
differential power of the PADDL cell are compared
with the same metrics of conventional NAND, NOR,
and XNOR gates. Then, PADDL is compared with
WDDL and SDMLp. In Section IV, body biasing of
nMOS transistors in PADDL is used to improve the
operating frequency and differential power of ultralow
power devices.
II. MOTIVATION AND BACKGROUND:
A. Secure Integrated Chip Design:
Smart cards consist of a secure integrated chip, which
contains the main processor, arithmetic logic unit,
processing registers, random access memory for
arithmetic processing, read-only memory (ROM) for
storing the operating system, and electrically erasable
programmable ROM for data memory. The operating
system controls data access and implements the
cryptographic security algorithms. The international
standard for contact-based smart cards electronic
identification cards is the ISO/IEC 7816 [12], and the
contactless smart card is the ISO/IEC 14443 [53]. In
this standard, smart cards use the triple data encryption
standard (DES), and the standard operating frequency
is 13.56 MHz.
B. DPA Attacks:
Since the design of smart cards has been standardized,
and their development is moving from single issuer
models to cooperative private–public sector
partnerships, a two-prong approach to smart card
security is required: software-systems security and
hardware-oriented security. Even though smart cards
utilize operating systems with cryptographic kernels,
the memory devices used to store them are not isolated
in perfectly tamper-proof locations. As a result,
analysis of a chip’s operation metrics, such as
differential power consumption, total execution time ,
magnetic field values, and radio frequencies allows
attackers to gain sensitive user data. The effectiveness
of these side-channel attacks was demonstrated in [5].
Page 846
Kocher demonstrated i that attackers may be able to