Neha Goel Ashutosh Nandi Dept. of Electronics and Comm. Engg. National Institute of Technology Kurukshetra, India [email protected], [email protected]Design of Optimized FIR Filter Using FCSD Representation Keywords— FIR Filter, CSA, Barrel shifter, FCSD. Abstract—This paper presents the design and implementation of an eight order efficient FIR filter for wireless communication system. In this work, factored canonical signed digit representation (FCSD) is used for representing the filter coefficients in order to reduce the design complexity, area and delay of the FIR filter. Complexity of the system has been reduced by replacing binary coefficients with FCSD representation. Further area and delay has been improved by replacing multiplication operation with add and shift method where carry save adder (CSA) is used for addition of two numbers and barrel shifter is used for shifting the data words. Representation of coefficient in the FCSD format along with fastest adder and shifter improves the performance of the system. FIR filter has been designed using an equiripple method in MATLAB and further synthesized on Spartan 3E XC3S500E target FPGA device. Simulation results show that optimized FCSD based FIR filter offers a less number of slices, look up tables (LUTs) and flip-flops as compared to CSD and conventional FCSD based FIR filter, in addition to enhanced performance. I. INTRODUCTION Digital FIR filter is one of the essential components in Digital Signal Processing (DSP) and communication system. With an explosive growth in mobile computing and multimedia applications, demand for low power and high speed DSP system has seen a tremendous growth [1]. Digital filters are used to modify the attributes of signal by removing noise from the original signal and shape the spectral characteristics of the resulting signal [2]. Digital filters are very superior in level of performance as they are highly stable, accurate and versatile as compared to analog filter [3]. Moreover, Portable applications require digital filter which operates at high data rate and low power consumption as high power consumption reduces battery lifetime, affecting device reliability and increasing cool cost [4]. Due to this reason, the requirement of a digital filter with optimized area, power and delay is a challenging task. DSP applications require a large order FIR filter. However, the complexity increases with increase in filter order because of requirements of larger mathematical computations [5]. Therefore, real time implementation of this filter with precise value is posing as a serious challenge. In order to achieve efficient digital filter, order of FIR filter must be as small as possible. This paper focuses mainly on the FIR filter due to its absolute stability and linear phase response [6]. On the basis of hardware implementation, digital filter can be classified into two categories: multipliers based and memory based [7]. The main components of digital filter consist of registers to save the samples of signals, adders to carry out sum operations and multiplier for multiplication of the filter coefficients with signal samples [8]. Despite the fact that designing of digital filter seems simple, but the design bottleneck is its multiplier block for speed, area and power consumption [9]. Complexity is mainly dominated by coefficient multiplication operation [10,11]. In order to reduce complexity, the filter coefficients are represented in FCSD representation which requires the least number of adders [12]. The filter can be further optimized by using CSA and a barrel shifter to achieve the operation of multiplication [13]. The rest of the paper is organized as follows: an overview of FIR filter is given in section II. Section III consists of modules for FIR filter. Section IV describes the proposed work for filter optimization. In section V, simulation results are discussed. Finally, section VI concludes the paper by summarizing the main contributes. Multipliers based design includes multiple constant multiplication (MCM) with add and shift operations.MCM based FIR filter uses transposed structure which increases the speed of the system.The area can be further saved by optimizing coefficient with quantization technique. Memory based design are divided into two approaches: distributed arithmetic (DA) and Look Up table (LUT) method. The DA based approach computes the inner product by accumulating bit level partial results in the FIR filter. The LUT based approach stores odd multiple of input signal in ROM to realize constant multiplications in MCM [7]. II. FIR FILTER FIR filter is also known as non-recursive digital filters as they don’t have feedback [6]. Output of the FIR filter can be described by the following difference equation FIR filters are digital filter with finite impulse response which involves convolution operation given by equation [2]: Y[n] = X[n]*H [n] (1) 3 NITTTR, Chandigarh EDIT-2015 Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
4
Embed
Design of Optimized FIR Filter Using FCSD Representation
This paper presents the design and implementation of an eight order efficient FIR filter for wireless communication system. In this work, factored canonical signed digit representation (FCSD) is used for representing the filter coefficients in order to reduce the design complexity, area and delay of the FIR filter. Complexity of the system has been reduced by replacing binary coefficients with FCSD representation. Further area and delay has been improved by replacing multiplication operation with add and shift method where carry save adder (CSA) is used for addition of two numbers and barrel shifter is used for shifting the data words. Representation of coefficient in the FCSD format along with fastest adder and shifter improves the performance of the system. FIR filter has been designed using an equiripple method in MATLAB and further synthesized on Spartan 3E XC3S500E target FPGA devi
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Design of Optimized FIR Filter Using FCSD Representation
Keywords— FIR Filter, CSA, Barrel shifter, FCSD.
Abstract—This paper presents the design and implementation
of an eight order efficient FIR filter for wireless communication
system. In this work, factored canonical signed digit
representation (FCSD) is used for representing the filter
coefficients in order to reduce the design complexity, area and
delay of the FIR filter. Complexity of the system has been
reduced by replacing binary coefficients with FCSD
representation. Further area and delay has been improved by
replacing multiplication operation with add and shift method
where carry save adder (CSA) is used for addition of two
numbers and barrel shifter is used for shifting the data words.
Representation of coefficient in the FCSD format along with
fastest adder and shifter improves the performance of the system.
FIR filter has been designed using an equiripple method in
MATLAB and further synthesized on Spartan 3E XC3S500E
target FPGA device. Simulation results show that optimized
FCSD based FIR filter offers a less number of slices, look up
tables (LUTs) and flip-flops as compared to CSD and
conventional FCSD based FIR filter, in addition to enhanced
performance.
I. INTRODUCTION
Digital FIR filter is one of the essential components in
Digital Signal Processing (DSP) and communication
system. With an explosive growth in mobile
computing and multimedia applications, demand for low
power and high speed DSP system has seen a tremendous
growth [1]. Digital filters are used to modify the attributes of
signal by removing noise from the original signal and
shape the spectral characteristics of the resulting signal
[2]. Digital filters are very superior in level of performance as
they are highly stable, accurate and versatile as compared
to analog filter [3]. Moreover, Portable applications
require digital filter which operates at high data rate and low
power consumption as high power consumption reduces
battery lifetime, affecting device reliability and increasing
cool cost [4]. Due to this reason, the requirement of a digital
filter with optimized area, power and
delay is a challenging task. DSP applications require a large order FIR filter. However,
the complexity increases with increase in filter order because of
requirements of larger mathematical computations [5].
Therefore, real time implementation of this filter with precise value is posing as a serious challenge. In order to achieve efficient digital filter, order of FIR filter must be as small as possible. This paper focuses mainly on the FIR filter due to its absolute stability and linear phase response [6]. On the basis of hardware implementation, digital filter can be classified into two categories: multipliers based and memory based [7].
The main components of digital filter consist of registers to
save the samples of signals, adders to carry out sum operations
and multiplier for multiplication of the filter coefficients with
signal samples [8]. Despite the fact that designing of digital
filter seems simple, but the design bottleneck is its multiplier
block for speed, area and power consumption [9]. Complexity
is mainly dominated by coefficient multiplication operation
[10,11]. In order to reduce complexity, the filter
coefficients are represented in FCSD representation which
requires the least number of adders [12]. The filter can
be further optimized by using CSA and a barrel shifter
to achieve the operation of multiplication [13].
The rest of the paper is organized as follows: an overview of
FIR filter is given in section II. Section III consists of modules
for FIR filter. Section IV describes the proposed work for
filter optimization. In section V, simulation results
are discussed. Finally, section VI concludes the paper
by summarizing the main contributes.
Multipliers based design includes multiple constant multiplication (MCM) with add and shift operations.MCM based FIR filter uses transposed structure which increases the speed of the system.The area can be further saved by optimizing
coefficient with quantization technique. Memory based
design are divided into two approaches: distributed
arithmetic (DA) and Look Up table (LUT) method. The
DA based approach computes the inner product by
accumulating bit level partial results in the FIR
filter. The LUT based approach stores odd multiple
of input signal in ROM to realize constant
multiplications in MCM [7].
II. FIR FILTER
FIR filter is also known as non-recursive digital filters as they don’t have feedback [6]. Output of the FIR filter can be described by the following difference equation
FIR filters are digital filter with finite impulse response
which involves convolution operation given by equation [2]:
Digital filter can be designed by calculating the filter
coefficient on the basis of filter order, sampling frequency,
pass band and stop band frequencies etc.[5]. Generally, power
consumption and the amount of computation are directly
proportional to filter order. Filter coefficient can be found with
the MATLAB FDA tool. Further, the filter can be designed by
different method including window functions, frequency
sampling and equiripple method [9]. Table I lists the
parameters of the low pass FIR filter and the corresponding
magnitude response is shown in Fig. 2.
TABLE I. FIR Filter Design Parameter
Filter Parameter Value
Design method Equiripple
Order 8
Density factor 20
Sampling frequency FS = 48000 Hz
Passband frequency Fpass = 9600Hz
Stopband frequency Fstop = 12000Hz
Passband weight Wpass = 1
Stopband weight Wstop = 1
The calculated coefficients of the proposed FIR filter are [9,
16, 17, 32, 33, 32, 17, 16, 9]. Coefficients are symmetric in
nature which further reduces area and power consumption [5].
Order for FIR filter is N while the length of the filter is N+1
which is similar to the number of the filter coefficients [10].
As the filter order increases, complexity of the system
increases by consuming more amount of time for signal
processing.
Where N and Hk represents the length and coefficients of the
FIR filter respectively [10].Basically FIR filter consists of two
structures, i.e., direct form and transposed form. In direct
form, signal samples are multiplied by filter coefficients and
combined together in adder block [7]. A modification over
direct form is transposed structure as shown in fig 1. In
transposed form, the same input signal is multiplied by several
coefficients. In the present work, transposed form is used
which reduces area and delay as compared to direct form [6].
(2)
k
K knxHnYN
)()(0
1
Fig.2. Lowpass FIR filter magnitude response
Three modules are needed for implementation of optimized
FIR filter, i.e., delay, addition and multiplication. Barrel
shifter is used to provide shift operation and CSA is used to
carry out a sum operation. The modules used for
implementation are:
Barrel shifter is an integral component in several
computing devices which is mainly used for shifting and
rotating multiple bits in a single clock. It can be designed with
the help of combinational logic circuits such as logic gates,
multiplexers and decoders. However, the MUX based barrel
shifter provides less delay and power when compared to other
circuits [13]. Therefore, in the present work, BS is designed
using multiplexers architecture. Shifting a data word by a
specific amount of shift is performed in one clock cycle.
Sequences of multiplexers are used to implement the barrel
shifter and the output of one mux is connected to the input of
the next mux that depends on the shift distance [7]. The data
word can be shifted up to 8 bits either in left or right direction. If the input pin is zero, then the observed output remains same, i.e., without applying shifting operation. On the other hand,
the proposed filter has been improved considerably which in
turn increases the operational speed of the system. This
reduction in design complexity, area and delay of proposed
FCSD based filter can be viewed as a possible alternative for
circuit designer.
Fig.4. Bar graph representing CSD, FCSD and proposed work comparison
VI. CONCLUSION
The proposed FIR filter has been designed for 8 tap using
FCSD representation of filter coefficients. An optimized FIR
filter has been designed using barrel shifter and CSA in
VHDL which is further simulated on Xilinx Spartan3E based
XC3S500E target FPGA device. The results show that
optimized FCSD based FIR filter can be operated at a
maximum frequency of 238.322 MHz by consuming 79 slices,
126 flip-flops and 146 LUTs. Simulation results shows that
optimized filter occupies 89.98% less number of slices,
88.682% less number of LUTs and 75.39 % less number of
flipflops as compared to FCSD technique. Delay of the
optimized FIR filter has been reduced by 18.071 ns. It is
concluded that, use of FCSD representation in FIR filters
along with fastest adder and shifter can target significant
reduction in design complexity, area and delay when
compared to other approaches.
REFERENCES
[1] D. L. Maskell, “ Design of Efficient Multiplierless FIR filters,” IET Circuits Device System, vol.1, no. 2, pp. 175-180, May 2007.
[2] M. D. Cilletti, Advance Digital Design with Verilog HDL, PHI learning, first edition, 2003.
[3] A. Nandi, A. K. Saxena and S. Dasgupta, “Design and Analysis of Analog Performance of Dual-k Spacer Based Underlap N/P-FinFET at 12nm Gate Length,” IEEE Trans. on Electron Devices, vol. 60, no. 5, pp. 1529-1535, May 2013.
[4] R. Mahesh and A. P. Vinod,“A New Common Subexpression Elimination Algorithm for Realizing Low Complexity Higher Order Digital Filters,” IEEE Trans. On Computer Aided Design of Integreted Circuits and Sytems, vol. 27, no. 2, pp. 217-229, Feb. 2008.
[5] L. Wu, Y. Cui and J. Huang, “Design and Implemenation of an Optimized FIR Filter for IF GPS Signal Simulator,” IEEE conf. on Microelectronics and Electronics, pp. 25-28, Sept. 2010.
[6] J. Proakis and D. Manolakis, Digital Signal Processing, fourth edition, 2008.
[7] S. F. Hsiao and J. H. Z. Jian, “ Low Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplications,” IEEE
Trans. on Circuits and Systems-II: Expression Briefs, vol. 60, no. 5, pp. 287-291, May 2013.
[8] J. Um and T. Kim, “An Optimal Allocation of Carry Save Adders in
Arithmetic Circuits, ” IIEEE Trans. on computer, vol. 50, no. 3, pp. 215-
230, Mar. 2001.
[9] Mathworks, User Guide Filter Design Toolbox,Version-2, 2007.
[10] L. Litwin, “ FIR and IIR Digital Filters,” IEEE Potentials, vol. 19, no. 4,
pp. 28–31, Oct. i2000.
[11] L. Aksoy, E. Costa, P. Flores and J. Monteiro, “ Exact and Approximate
Algorithms for the Optimization of Area and Delay in Multiple Constant
Multiplications”, IEEE Trans. on Comp. Aided Design of Integreted
Circuits and Sytems, vol. 27, no. 6, pp. 1013-1026, iJune 2008.
[12] K. Priya and R. Mehra, “ FPGA Based Cost Efficient FIR Filter Using
Factored CSD technique ,” International iJournal of Recent Technology
and Engineering,vol. 6, issue 6, pp. 130-134, Jan. 2013.
[13] R. Rajalakshmi and P. ArunaPriya, “ Design and Analysis of A 4-Bit Low Power Universal Barrel-Shifter in 16nm FINFET Technology,” IEEE International Conference on Advanced Communication Control and Computing Technologies, pp. 527-532, May 2014.