Design of fault detection and tolerance system in analog ...research.iaun.ac.ir/pd/saeed-nasri/pdfs/PaperC_2392.pdf · Design of fault detection and tolerance system in analog and

Design of fault detection and tolerance system in analog and digital CMOS circuits

Mohammad Reza Hemmati department of computer,najafabad branch,islamic azad university,najaf abad,iran

Email : [email protected]

Saeed Nasri Assistant Professor Faculty of Electrical Engineering Najafabad branch Islamic Azad University

,Najafabad,iran Email : [email protected]

Abstract Accurate calculation of error in terms of existing parameters in circuit including voltage, gain, and the total energy consumption in analog and digital CMOS circuits require simulation of circuit with precise parameters under real conditions with real inputs. This is fulfilled in analog-like simulation software. In such simulations, Spice simulation time increases and reaches to several days by increasing number of elements in the circuit. In most cases, due to needing to high accuracy, an attempt is made to use analog simulation and estimate energy with faster methods and lower accuracy such as digital simulation. The present research intends to make the calculations and estimate power based on number of transitions. Obtained results indicate calculations and estimation of error at high accuracy. Keywords: fault detection, tolerance system, CMOS circuits Introduction Power consumption in digital CMOS circuits can be divided into three parts which include: 1. Dynamic Power 2. Consumption power during short connection 3. Static power PTotal = PDynamic + PShort Circuit + PStatic Dynamic power implies the consumed power for capacitor charging and discharging in output of a simple CMOS circuit. Such circuit can be considered as a gate that the existing load in its output can be modelled via a capacitor (figure 1).

Figure 1. Existing capacitive load in the output of gate

Considering this point that CMOS circuits are developed from two parts of pull up and pull down, it can know the dynamic power as the result of consumption current in changing output from 0 to 1 for the charge of capacitor by pull up circuit and the consumption current in changing output from 1 to 0 for discharging capacitor by pull down circuit.

Figure 2. Structure of CMOS circuits

The consumption power at each transition can be calculated via the formula P and average consumption power in one period of circuit performance can be obtained via the

formula . Here, f represents frequency of output volatilities of CMOS circuit. Here, f represents frequency of output oscillations of CMOS circuit. Approximately 85% of total consumption power in CMOS circuit can be known due to capacitor charging and discharging in circuit during transitions. Short connection power In transition from 0 to 1 or vice versa in CMOS circuit, both pull up and pull down circuits are on at a moment, as a result a route is connected from Vdd to GND. This route can pass numerous current. The power which is consumed at this moment is called short connection

power (figure 3). 15% short connection power is allocated among the entire consumption power, which this rate has a direct relationship with number of transitions [1][2]. Static power Static power implies the consumed power due to the leakage current when transistors are off. Static power general has little share in total power, under which it can neglect it simply. Yet, we must take this point into consideration that the static power in the entire consumption power keeps increasing by downsizing the transistors and developing technology. Discussion and how to make calculations Estimation of energy through counting transitions As mentioned, over 99% of power or energy is consumed during change of output of a gate[3][4]. Therefore, two major components of power including dynamic power and short connection power must be considered to estimate consumption energy in a circuit. Estimation of consumption energy at short connection time is relatively easier than dynamic power. Known mean of short connection current in all the gates, it can know the consumed energy at short connection time well suited with number of transitions [5][6]. Yet, this method raises error because practically short connection current is greater in the gates which have been designed for fan-out than normal gates, which the reason lies on larger size of transistors and their little resistance in pull up and pull down grids. The consumed energy in a dynamic way can be known well suited with number of transitions.

Figure 3. Short connection current

As mentioned earlier, f can be considered as the frequency of changes in output of gate, but a point which has made estimation of dynamic power much more difficult lies on capacitance of the load connected to output in formula above. In other words, we must know amount of existing load in output to know amount of consumption power. Existing load in output of a gate can be known the gates connected to it. In other words, C is well suited with fan-out of a gate. Estimation of energy by counting transitions is a work conducted in this context. With regard to what mentioned in this article, if there does not exist a large difference in gates in a fan-out circuit, it can estimate energy of circuit with accuracy greater than 90%. In the samples examined in the present research in data-path, there is more than 90% accuracy as fan-outs are the same, but accuracy reaches to less than 70% or even 40% in the control and random logic circuits due to large difference in fan-outs[9][10]. Hence, it requires considering fan-out of gates to increase accuracy of calculations. For this, two methods are considered as follows: -calculating fan-out of gates from net-lists through a computer application and employing it in the calculations and counting transitions -counting number of transitions in input of gates instead of their output The second method is considered in this research. Fan-out is considered in an automatic way by counting transitions in inputs. For instance, if a transition occurs in output of gate A, this is counted for three times in input of gates B, C and D and if a transition occurs in output of gate E, this is counted one time in input of gate F[7][8]. To ensure about accuracy of this method, several experiments have been made which have been represented as follows. To ensure about accuracy of this method, several experiments have been made as follows. In all these experiments, NAND gates with three inputs shown in figure 4 have been used.

Figure 5. Counting transitions in output

Figure 4. fan-out and load problem

Size of transistors is based on table 1.

Hence, W ratio in each of branches of pull-up grid to pull-down grid equals to .

With this ratio, Rise-time and Fall-time times are equal in output of gate. It should be noted that simulation time has been 20 nanoseconds in all these experiments,

thus the consumed energy in circuits is well suited with power. The first experiment: a NAND circuit with three inputs by combining inputs as shown in figure 7 is considered. In this circuit, output changes from 1 to 0 and vice versa by changing input ‘a’ from 0 to 1. Firstly, input is applied to a regarding figure 8. In this way, output

Figure 6. NAND circuit with three inputs

Figure 8. Input wave

Table 1. size of transistors in NAND circuit with three inputs

Figure7

changes regarding figure 9. Firstly this is fulfilled without connecting output of a gate to another gate. Diagram of moment power is based on figure 10 . As observed, power is consumed at the times with change in output state of power. In this state, average consumption power is watt. It can know this amount pertaining to short connection power and necessary dynamic power for charging and discharging the capacitor in output of gate. Now we add one gate to the circuit as shown in figure 11; in this state, there will be Fan-out=1. Take this point into consideration that output B does not change by changing output A, thus we can calculate the changes of power due to charging input capacitor in gate B. by applying

Figure 9. Output wave

Figure 11. the circuit under experiment

Figure 10- moment power

the same input to the circuit in figure 11, average consumption power is obtained equal to watt. By subtracting which associates to power consumption

of gate A, we can calculate the amount added for charging and discharging the capacitor in output of gate B.

Now we repeat this experiment with fan-outs 2 and 4. Result of this experiment can be observed in table 2. As observed, the required power for charging input of the gates in the second class has a direct relationship with their number, that almost watt power is consumed per gate which is connected to output. As mentioned earlier, change in output of gate A does not cause change in output of gate B in the circuits which have not been tested to date. Now, we must observe whether it can acquire the same result if the change in output of gate ‘A’ causes change in output of gate B. The second experiment: we raise changes in the second class of circuit in order that output B changes per change in output A(figure 12).

Figure 12. the circuit pertaining to the second experiment

table 2-results of the first experiment

As observed, two additional inputs of gate B have been connected to input 1. Average power is obtained equal to in case output A is connected to a gate. As known, average power equaled to in previous circuit when there has been Fan-out=1 (figure 11). The reason for this increase of power can be short connection current in output of gate B and required power for charging capacitor in output of gate B during change. If this goes true, due to the same structure of gates A and B, the power due to short connection current must be equal in two gates, thus if we subtract two loads of P0 from this amount, there will be:

If we repeat this experiment on fan-outs 2 and 4, we will acquire the results same as what acquired in the first experiment(table 3). Take the point into consideration as follows: consumed power (P) in the entire circuit, consumed power in the second class of circuit (P-P0), consumed power in each second-class gate and consumed power by input capacitor in each second-class gate . With the same result obtained in this experiment, it can say that the consumption power for charging input capacitor of gates is well suited with their number (fan-out). If we look into interior structure of gates NAND in figure 6, we will observe that each input is connected to two transistors N and P. Indeed, capacitor implies the entire existing capacitors in gates of these two transistors. If one input is connected to more than two transistors or less than two transistors in a specific gate, can we know it similar to two experiments. Definitely, this raises error in calculations. The proposed method to estimate energy With regard to what said above, it can know the consumed energy in circuit well suited with number of transitions. Counting transitions in gate of transistors is used to estimate energy in

table 3. Results of the second experiment

this project. Fan-out is considered using this method. To prove accuracy of this method and examine its accuracy, five different circuits have been considered as the sample. These circuits have been synthesized to the transistor level and the simulations have been made at HSpice and ModelSim. Table 4 indicates features of the circuits under study.

In each case, firstly the consumption power of the circuit has been calculated in analog simulation via software HSpice equal to 0.35. Then, amount of consumed energy has been obtained in terms of J via the equation energy=power*time. These experiments have been repeated under the same conditions with two feeding sources 2.5 and 3.5 volt. At the next stage, the experiments are made with the same inputs via software ModelSim and hardware language Verilog and number of transitions has been counted. By dividing obtained energy via HSpice into number of transitions, it can obtain approximate amount of consumed energy in any transition. As observed in table 5, these amounts are so close to each other and difference of the smallest and largest number in 2.5 volt and 3.3 volt experiments equals to 5% and 7.5%, respectively. Therefore, it can deduce that counting transitions in gate of transistors is a precise method that can be used to estimate energy in larger circuits. Short simulation time and energy estimation at high accuracy without needing to know physical features are advantages of this method than analog simulation. Examine speed of Synchronous circuit Working frequency of Synchronous circuit can be evaluated based on a report proposed by Leonardo’s synthesis instruments. Leonardo has reported maximum delay at critical route equal to . Hence, maximum working frequency of this circuit can be 220 Mhz. this circuit at any hour pulse receives a four bit symbol in its input. Therefore, rate of inclusion of information to this circuit is 880 mg per second, which this figure has no relationship with existence or lack of existence of error in code. Figure 13 represents scheduling inclusion and exclusion of information in the circuit.

Figure 13. Scheduling for input and output in the circuit

Circuit under study Number of transistors

How to estimate speed of Synchronous circuit To calculate speed of Synchronous circuit, it requires simulating this circuit via software HSpice, but this is impossible due to large volume of circuit. Fortunately, due to use of PCHB and PCFB patterns in circuit and similar circuits in these patterns, a suitable solution is required. As mentioned, the aforementioned patterns have the same structure in figure 14. InputAck circuit has the same structure in most of circuits. Hence, it can simulate it in HSpice and compute its delay. Yet this does not come true in the circuits which detect authenticity of input and output, such that structure of circuits changes by increasing number of input and output bits. Hence, it requires making simulation for the input and output with different number of bits. The circuits which detect authenticity of 1, 2 and 8 bit outputs have been represented in figures 15, 16 and 17.

Figure 14-PCHB/PCFB structure

Figure 15. The circuits which detect authenticity of 1 bit output

Figure 16. The circuits which detect authenticity of 2 bit output

FIGURE 17 Conclusion As seen in figures, number of classes in circuit increases by increasing number of bits, as a result delay increases at circuit. Table 6 represents the delay at circuits.

Table 6. Delay at different segments of patterns PCHB/PCFB with technology of 0.35 micron

Circuit Delay in terms of nanosecond

Figure 18. Computational circuit in PCHB

The circuit which calculates output is the only part which differs in different circuits (figure 18). As observed, difference in delay at these circuits compared to delay at rest of segments of circuit is negligent, thus delay ( ) is considered as mean for this part. It seems that simulation of circuit in Verilog and delays at HSpice give acceptable outcome in terms of delay. To justify this, several experiments have been made that their results can be witnessed

Figure 19-computational circuit

in table 8. In this table, delay computed via Verilog has been compared with real delay at circuit, that error at this method is about 7% at the worst state. It should be noted that Input-Input Ack in table above indicates the delay raised since time of authenticity of input till reaching to acknowledge and Input-output indicates delay at circuit since time of authenticity of input till authenticity of output. Concerning FIFO circuit, Input-InputAck indicates delay since authenticity of input of circuit till activation of Acknowledge pertaining to the third buffer after receiving the input. With regard to table 8, it can deduce that such method can be used to estimate speed at larger circuits.

Type of circuit Speed without error

Speed with error

Power without error

Power with error

Maximum power error correction

Technology pipeline

Synchronous 3.3V 880 Mbps 880 Mbps 102.19 mW

131.39 mW

0.13 0.35 µm *

Synchronous 3.3V 1028 Mbps

584 Mbps 90.32 mW 261.77 mW

0.13 0.35 µm *

Synchronous 2.5V 749.4 Mbps

4363 Mbps

35.4 mW 105 mW 0.13 0.35 µm *

Synchronous 1.8V 528 Mbps 306 Mbps 12.2 mW 36.1 mW 0.13 0.35 µm *

Synchronous 1.8V 2166 Mbps

1429 Mbps

25.9 mW 85.25 mW

0.13 0.18 µm *

Table 8. Features of the circuits

Type of circuit

Speed without error

Speed with error

Power without error

Power with error

Maximum power error correction

Technology pipeline

Synchronous 1995 [Kes95]

32 Mbps 7.3 Mbps 0.44 mW 2.6 mW 0.08 0.8 µm -

Synchronous 1999 [Cha99a] [Cha99b]

320 Mbps

320 Mbps

400 mW @ 240 Mbps

400 mW @ 240 Mbps

0.15 0.6 µm *

Synchronous 1998 [Shun98]

133 Mbps

133 Mbps

- - 0.03 0.6 µm *

Synchronous 2001 [Qun01]

180 Mbps

180 Mbps

- - 0.12 0.6 µm *

Synchronous 2000 [Lee00]

600 Mbps

600 Mbps

- - 0.03 0.25 µm *

Synchronous 2001 [Lee01]

5.36 Gbps

5.36 Gbps

- - 0.03 0.16 µm *

Synchronous 2003 [Lee03]

2.4 Gbps 2.4 Gbps - - 0.03 0.13 µm *

Table 9. Features of the circuits

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