Presented By: Under the guidance of Prof. DEBAPRASAD DAS Department of Electronics and Communication Engineering TSSOT, Assam University May 15, 2017 Design Of a CMOS Operational Amplifier Using Cadence Roll No. Name of Students 31330153 Anamika Chakraborty 31320230 Nandi Vashishth 31360060 Pinku Das 31360110 Nirupom Das
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Design of CMOS operational Amplifiers using CADENCE
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Presented By:
Under the guidance of
Prof. DEBAPRASAD DAS
Department of Electronics and Communication Engineering
TSSOT, Assam University
May 15, 2017
Design Of a CMOS Operational Amplifier Using Cadence
Roll No. Name of Students
31330153 Anamika Chakraborty
31320230 Nandi Vashishth
31360060 Pinku Das
31360110 Nirupom Das
Contents
CMOS Amplifier
Current Mirror
CMOS Differential Amplifier
Single Stage Operational Amplifier
Two Stage Operational Amplifier
Conclusion
References
CMOS AMPLIFIER
Requirement of Amplifiers
o Amplifiers are essential building blocks of both analog and digital systems.
o An amplifier is an electronic device that increases the voltage, current, or power of a
signal.
o The amount of amplification provided by an amplifier is measured by its gain: the
ratio of output to input.
o Amplifiers are needed for variety of reasons including:
-To amplify a weak analog signals for further processing.
-To reduce the effect of noise of next stage.
-To provide a proper logical levels(in digital circuits).
CMOS Amplifier SCHEMATIC DESIGN
This is a table of components for building the CMOS Amplifier schematic.
Library name Cell name Properties/Comments
gpdk180 nmos Model name = nmos1(NM0)
W=2u; L=1u
Analoglib Idc DC current= 5uA
Analoglib VDD, Gnd VDD = 1.8V
CMOS Amplifier Schematic (using CADENCE)
This current πΌπ· is a function of gate voltage ππΊπ and drain
voltage ππ·π.. hence, we can write the change in πΌπ· as
dπΌπ·=ππΌπ·
πππΊπdππΊπ +
ππΌπ·
πππ·ππππ·π (1)
Working of CMOS Amplifier
As the drain current is driven by a current source, it is constant and hence dIπ·=0.Then Eqn (1) can be written as
ππΌπ·
πππΊππππΊπ +
ππΌπ·π
πππ·πdππ·π = 0 (2)
With the application of the input AC signal, the change in gate to source voltage is the input voltage (vin = πππΊπ) , and the change
in drain to source voltage is the output voltage (vout = dππ·π ). Hence we can write Eqn (2) as
πππ£ππ + 1
πππ π£ππ’π‘ = 0 (3)
where
Transconductance ππ = ππΌπ·
πππΊπwith ππ·π = constant.
Output resistance πππ = πππ·π
ππΌπ·with ππΊπ = constant.
Hence, from Eqn (3) the voltage gain can be written as
π΄π£ = π£ππ’π‘
π£ππ= -πππππ
Simulation Results
AC Analysis: It is used to sweep the frequency of an AC source. AC analysis is mainly used to obtain the frequency
response of the circuit. In AC- Analysis we determine Phase margin, Gain and GB of the amplifier. Both Gain and Phase margin
are calculated using DC operating point and AC analysis. The values given to implement AC Analysis are:
β’ Start frequency = 100 Hz
β’ Stop frequency = 100 GHz
CMOS Amplifier Gain Bandwidth from AC AnalysisCMOS Amplifier Gain from AC Analysis
AC Analysisβ¦β¦β¦β¦β¦β¦contd.
Parameter Value
Gain 69.37dB
Gain Bandwidth (GB) 33.305 GHz
Phase Margin 134.95 degree
CMOS Amplifier AC Analysis Output
CMOS Amplifier Phase Margin from AC Analysis
Simulation Resultsβ¦..contd.
Transient Analysis
Transient analysis is used to sweep the time. Transient analysis is used to find out the transient response of the circuit. The values
Let us first explain the design parameters that are used to design a CMOS OPAMP circuit.
β’ Gain The open-loop gain of the OPAMP must be very high, so that when it is used in negative feedback, the closed-loopgain must be independent of open-loop gain.
β’ Small signal bandwidth (BW) The open-loop gain decreases as the frequency of the operation increases. Hence, the designmust consider the BW of the OPAMP.
β’ Large signal bandwidth The OPAMP is used in large signal transients. Hence, it must respond to the transient signals thatchange very fast in time.
β’ Slew rate The OPAMP must have a high slew rate.
β’ Linearity The OPAMP characteristics must be linear.
β’ Noise and offset The noise and offset must be insignificant.
β’ Power supply rejection The power supply rejection must be high.
β’ Input Common Mode Range (ICMR) For an op amp, ICMR is the range of common mode signal for which the amplifier'soperation remains linear.
β’ Common Mode Rejection Ratio (CMRR) Common-mode rejection ratio, CMRR, is defined as the ratio of the differentialvoltage amplification to the common-mode voltage amplification. Ideally this ratio would be infinite with common modevoltages being totally rejected.
Single stage Op amp Schematic Design
To design single stage op amp schematic following boundary conditions are required:
1. Process specifications (VT, Kβ, etc.)
2. Supply voltage and range
3. Supply current and range
4. Operating temperature and range
Sl. No. Specifications Value
1. Technology gpdk180
2. Power Supply (VDD) 1.8 V
3. Load Capacitance (CL) 10 pF
4. Gain >= 40 dB
5. Gain Bandwidth >= 5 MHz
6. Slew rate (SR) 5 V/usec
7. ICMR (+) 1.6 V
8. ICMR (-) 0.8 V
9. Power Dissipation <= 2mW
Design Specifications
Model or Device
Parameters
Value
Vtp -0.46 V
Vtn 0.49 V
Kβp 63 uA/V2
Kβn 325 uA/V2
Required Device Parameters for
designing single stage op amp
Single stage opamp design procedure
Figure: Single stage Op amp
1. Pick πΌπ to satisfy the slew rate knowing πΆπΏ and minimum
power dissipation
2. Design W1/L1 (W2/L2) to satisfy
the gain
3. Design W3/L3 (W4/L4) to satisfy
the upper ICMR
4. Design W5/L5 to satisfy the
lower ICMR
β Iterate where necessary
Design Procedureβ¦β¦β¦β¦.contd.
Step1:- To meet the slew rate, and maximum Power Dissipation