Design of an almost continuously controlled three- phase ...

Scientific Research and Essays Vol. 7(2), pp. 219-230, 16 January, 2012 Available online at http://www.academicjournals.org/SRE DOI: 10.5897/SRE11.1580 ISSN 1992-2248 ©2012 Academic Journals

Full Length Research Paper

Design of an almost continuously controlled three-phase static VAR compensator for power factor

correction purposes

Abdulkareem Mokif Obais* and Jagadeesh Pasupuleti

Department of Electrical Power Engineering, Universiti Tenaga Nasional, Malaysia.

Accepted 31 October, 2011

In this paper, a three-phase four-wire automatic power factor correction system is designed and tested. This system employs three-phase Wye-connected thyristor switched-capacitor banks to generate a controllable static VAR. Each capacitor bank is constructed of five binary weighted thyristor switched-capacitors. This arrangement leads to a capacitor bank capable of generating stepping reactive power having thirty one equidistant non-zero levels. The controlling circuit of each capacitor bank is designed such that maximum absolute deviation from linear response is 1/62 of its rating. Each capacitor is controlled by a single thyristor shunted by a reverse diode. The system is capable of correcting lagging power factor up to unity or adjusting it according to user desire. Each capacitor is connected to a series reactor for protecting the solid state combination from inrush current occurring at the first instant of compensator plug in to power system network. The proposed system is characterized by negligible no load operating losses, no generation of harmonics, energy saving, and reduction of transmission losses. The system is designed and implemented on PSpice which is a computer program very close in performance to real hardware and broadly adopted by manufacturing companies. Key words: Capacitor bank, power factor correction, power quality, static VAR.

INTRODUCTION Power factor improvement leads to a big reduction of apparent power drawn from the ac source which in turn saves energy and minimizes the transmission losses (Mehrdad, 2005; Dai et al., 2007; Lupin et al., 2007). It generally employs means that control reactive power in power system network (Gyugy et al., 1978). The process is usually denoted by reactive power compensation which is a productive technology employed for improving power systems performance. This technology serves customers and power system networks. Power quality is an insisting challenge in ac power systems, whereas reactive power compensation techniques offer striking solutions on the *Corresponding author. E-mail [email protected].

route of its achievement. Reactive power control solves or attenuates many power system problems such as poor voltage regulation, line currents unbalance, poor power factor, and reduced efficiency. There are so many techniques approaching reactive power control, but the static VAR compensators are the most reliable ones, since they present high flexibility in design methodology and exhibit reasonable response amongst fast varying environments (Miller, 1982). Static VAR compensators are either series or shunt compensators. Series compensators deal with modification of distribution or transmission parameters of the ac system, while shunt compensators decide the load equivalent impedance (Miller, 1982; Teleke et al., 2008). Both types of compensators can be used to control the reactive power for power factor correction purposes in ac power systems.

220 Sci. Res. Essays Synchronous condensers and manually switched capacitors or inductors can be used for power factor correction purposes, but. static VAR compensators using thyristor switched- capacitors and thyristor controlled reactors are superior to them, since they are characterized by fast response and high design flexibility (Teleke et al., 2008). Fixed capacitor-thyristor controlled reactor (FC-TCR) compensators are widely used for power factor correction purposes. They offer the feasibility of continuous reactive power control, but they exhibit full load operating losses at relaxation time, since the TCR is operating at its full capacity in order to absorb the reactive power generated by the fixed capacitor (Chen et al., 1999). In addition they release large amounts of harmonic current components which increase transmission losses and disturb the power system network voltage profile (Best and La Parra, 1996). The TCR is a source of harmonics, where the third harmonic for instance is about 13% of the TCR rating (Chen et al., 1999). This reveals the need for harmonics filters which add more complexity and more operating and transmission losses (Lee and Wu, 2000). Static VAR compensators using switched-capacitor banks offer stepping responses in reactive power generation mode and their losses are proportional to the reactive power demands (Nandi et al., 1997). FC-TCR and switched capacitor banks static VAR compensators are usually referred to as conventional static VAR compensators which are basically characterized by the employment of naturally commutated solid-state switching devices having high voltage and current ratings.

Employment of converters with an appropriate pulse width modulation control technique, permits the implementation of static VAR compensators capable of generating or absorbing reactive power with fast time response (Walker, 1986; Stahlkopf and Wilhelm, 1997). The recent developments in power electronics devices offer high amount of flexibility in static VAR compensators design for power factor correction and voltage control purposes. The new generations of these devices are characterized by fast responses, wide frequency spectrums, wide safe operating areas, low switching losses, low ON and OFF times, and easy commutation (Rashid, 2001; Bimal, 2006). Basing on the above facts and the recent analytical computations, Flexible AC Transmission Systems (FACTS) appear as a new concept in power transmission systems (Idris et al., 2010).

These new technologies make it easy to present static VAR compensators having fast response and capable of increasing the amount of apparent power through a transmission line in the neighborhood of its thermal capacity, without exceeding its stability limits. These new technologies are limited to low voltage applications, since they are employing fast solid-state switching devices having relatively low voltage and current ratings (Rashid,

2001; Bimal, 2006).

Here in this paper, a reliable switched-capacitors technique is adopted for three-phase automatic power factor correction purposes. The technique is based on designing a switched-capacitor bank exhibiting almost linear response versus reactive power demand. This technique solves the linearity problem of static VAR generation and offers the feasibility of operation at high voltage and current ratings, since it employs solid state switching devices having high ratings. In addition, the proposed technique is harmonic free, thus no harmonic filters are required. THE CAPACITOR BANK CONFIGURATION The proposed capacitor bank is composed of five binary weighted capacitors as shown in Figure 1a. This configuration offers 31 non-zero levels of possible capacitive reactive current as shown in Figure 1b. Each capacitor is controlled by a single thyristor shunted by a reverse diode. The thyristor handles the positive half cycle of the capacitor current and the diode deals with the negative half cycle. Reactors LS1 to LS5 are current limiters. THE PROPOSED SINGLE-PHASE SYSTEM The single-phase power factor correction system block diagram is shown in Figure 2. The capacitor bank triggering circuit is excited by two signals. The first signal is KiL, where K is the attenuation factor of the current transformer (C.T) circuitry and iL is the instantaneous load current. The second signal is K*v, where K* is the attenuation factor of the voltage transformer (V.T) circuitry and v is the instantaneous phase voltage.

The load voltage and current can be given by:

tVv m sin (1)

)sin( tIi mL (2)

Where Vm is the load voltage amplitude in volts, Im is the load current amplitude in amperes, φ is load current power factor angle in radians, and t is time in seconds. The first zero-crossing detector in Figure 2 converts K*v to a rectangular waveform V1 which is then differentiated and half-wave rectified by the first RC differentiator/rectifier, forming V2. The latter is a train of pulses used to trigger the sample and hold circuit at ωt = nπ, where n is a positive odd integer. The analogue differentiator converts K*v to the analogue signal V3

Obais and Pasupuleti 221

C

1

2

2C

1

2

8C

1

2

4C

1

2

16C

1

2

T1 DT1

12

T2 DT2

12

T3 DT3

12

T4 DT4

12

T5 DT5

12

V

LS1

1

2

LS2

1

2

LS3

1

2

LS4

1

2

LS5

1

2

Line

Neutral

(a)

I

2I

6I

4I

10I

8I

14I

12I

18I

16I

22I

20I

26I

24I

30I

28I

32I

10II

2I

4I

8I

6I

14I

12I

18I

16I

22I

20I

26I

24I

30I

28I

Capacitive reactive current demand

Capacitor bank current

32I

Maximum error=I/2

Stepping response

31I

Linear response

I=VwC

31I

(b)

Figure 1. Capacitor bank, (a) configuration, (b) expected reactive current response.

which is then zero-crossing detected, forming the waveform V4. The latter is processed similar to V1, forming V5. These waveforms are shown in Figure 3.

The current signal KiL is sampled by the sample and hold circuit at ωt= nπ, where n is a positive odd integer, yielding an analogue signal proportional directly to the

222 Sci. Res. Essays

VT1

VT3

VT2

VT5

VT4

8-bit ADC

DB5

DB6

DB7

DB2

DB3

DB4

DB0

DB1

CNVRT

INU1A

74A

C08

1 23

U2B

74A

C08

4 56

U3C

74A

C08

9

10

8

U4B

74A

C08

4 56

U4C

74A

C08

9

10

8

Amplifier

C.T

V.T

Driving circuit

Vi

Sample/hold

circuit

Analogue

differentiatorRC differentiator

/rectifier(1)

Zero-crossing

detector(2)

C

1

2

2C

1

2

8C

1

2

4C

1

2

16C

1

2

T1D1

12 T2

D2

12 T3

D3

12 T4

D4

12 T5

D5

12

LS1

1

2

LS2

1

2

LS3

1

2

LS4

1

2

LS5

1

2

R

2

1

L

1

2

N

L

V

Inductive load

RC differentiator

/rectifier(2)

K*v

Capacitor bank triggering circuit

KiL

Capacitor bank

KiL

V1

V2

V3V4

V5

iL

iC

iT

Zero-crossing

detector(1)

Figure 2. The proposed single phase power factor correction system block diagram.

reactive current component of the load current as follows:

sinsin m

nt

mL KItKIKi

(3)

The latter signal is amplified and clamped upward by 0.15625 volts producing the analogue voltage Vi which is proportional to the reactive current demand. Vi is the analogue input of the 8-bit analogue-to-digital converter (8-bit ADC). For unity power factor correction and at full compensator rating, Vi will have a magnitude of 10 volts. The 8-bit ADC starts conversion at ωt = (2n-1)π/2, where n is a positive odd integer. The five most significant digits

(DB7, DB6, DB5, DB4, and DB3) of the 8-bit ADC are employed for controlling the capacitor bank switching devices (T5, T4, T3, T2, and T1) respectively. The instantaneous capacitor bank current iC is determined by the logic status of the 8-bit ADC as follows:

3

5

14

5

25

5

46

5

87

5

16DBDBDBDBDBCVi mC (4)

Where, C is the basic capacitance of the capacitor bank. For DB7, DB6, DB5, DB4, and DB3, logic zero refers to zero volts, while logic one refers to +5 volts. Note that when Vi is zero, all the digital outputs of the 8-bit ADC are


2

2

3

2

5

2

7 2 3 40

Time

0s 20ms 40ms

V(U11:OUT)

-4.0V

0V

4.0V

Time

0s 20ms 40ms

V(VS2)

0V

2.5V

5.0V

Time

0s 20ms 40ms

V(D5:2)

-5.0V

0V

5.0V

3V

5V

4V

2

2

3

2

5

2

7 2 3 40

Time

0s 20ms 40ms

V(VS)

-4.0V

0V

4.0V

Time

0s 20ms 40ms

V(VS1)

0V

2.5V

5.0V

Time

0s 20ms 40ms

V(D6:2)

-5.0V

0V

5.0V

vK *

2V

1V

Time t, Time t,

Figure 3. The single-phase basic voltage waveforms.

logic zero. When Vi is 10 volts, all the digital outputs are logic one.

Table 1 shows the capacitor bank switching status as Vi

varies from zero to 10 volts. The driving circuit includes five sub-circuits; each one of them deals with one of the thyristor (T1 to T5). Choosing appropriate switching instants will protect the switching devices from inrush currents. The appropriate switching of thyristor occurs at ωt = (2n+1)π/2, where n is a positive odd integer. At these instants dv/dt is zero and each of the capacitors (C, 2C, 4C, 8C, and 16C) is charged to -Vm through its corresponding diode and limiting reactor. Note that when this compensator is started, each of the above capacitors charges through its individual diode and limiting reactor to -Vm. No inrush current will associate the charging and switching mechanisms.

THE PROPOSED THREE-PHASE POWER FACTOR CORRECTION SYSTEM

The power circuit of three-phase power factor correction system is shown in Figure 4. It is simply composed of

three identical capacitor banks connected in star form. iCA,

iCB, and iCC are the instantaneous compensator

phase currents, while vA, vB, and vC are the power system instantaneous phase voltages. The three phase instantaneous load currents are iLA,

iLB, and iLC, while the

three phase instantaneous line currents are iA, iB, and iC.

Each capacitor bank will respond according to Figure 1b. The block diagram of the proposed three-phase four-

wire power factor correction system is shown in Figure 5. It comprises three identical voltage transformers and three identical current transformers. Here are three identical triggering circuits; each one of them deals with a single capacitor bank. Phase A triggering circuit is excited by the analogue signals KiLA and K*vA, phase B triggering circuit is excited by the analogue signals KiLB and K*vB, and phase C triggering circuit is excited by the analogue signals KiLC and K*vC. If the compensator is operated by a balanced three-phase supply, then the controlling signals can be given by

tVKvK mA sin** (5)


Table 1. The capacitor bank status as Vi varies from 0 to 10 V.

Vi (Volts) C1 Status C2 Status C3 Status C4 Status C5 Status

0 OFF OFF OFF OFF OFF

0.3125 ON OFF OFF OFF OFF

0.625 OFF ON OFF OFF OFF

0.9375 ON ON OFF OFF OFF

1.25 OFF OFF ON OFF OFF

1.5625 ON OFF ON OFF OFF

1.875 OFF ON ON OFF OFF

2.1875 ON ON ON OFF OFF

2.5 OFF OFF OFF ON OFF

2.8125 ON OFF OFF ON OFF

3.125 OFF ON OFF ON OFF

3.4375 ON ON OFF ON OFF

3.75 OFF OFF ON ON OFF

4.0625 ON OFF ON ON OFF

4.375 OFF ON ON ON OFF

4.6875 ON ON ON ON OFF

5 OFF OFF OFF OFF ON

5.3125 ON OFF OFF OFF ON

5.625 OFF ON OFF OFF ON

5.9375 ON ON OFF OFF ON

6.25 OFF OFF ON OFF ON

6.5625 ON OFF ON OFF ON

6.875 OFF ON ON OFF ON

7.1875 ON ON ON OFF ON

7.5 OFF OFF OFF ON ON

7.8125 ON OFF OFF ON ON

8.125 OFF ON OFF ON ON

8.4375 ON ON OFF ON ON

8.75 OFF OFF ON ON ON

9.0625 ON OFF ON ON ON

9.375 OFF ON ON ON ON

9.6875 ON ON ON ON ON

3/2sin** tVKvK mB (6)

3/4sin** tVKvK mC (7)

AmLALA tKIKi sin (8)

BmLBLB tKIKi 3/2sin (9)

CmLCLC tKIKi 3/4sin (10)

Where ImLA, ImLB, and ImLC are the load phase currents

amplitudes, while φA, φB, and φC are their power factor angles. These three-phase controlling signals are processed in the same manner adopted in the single phase power factor correction system. The capacitor bank of each phase will respond according to the criterion of Table 1.

SYSTEMS CIRCUITS DESIGN The single-phase and three-phase automatic power factor correction systems are designed and implemented using the computer program PSpice. Datasheets of electronic parts and aiding literatures are considered during design process (Rashid, 2001; Bimal, 2006).


N

La

1

2

Ra

Lc

1

2

Rc

Lb

1

2

Rb

C

1

2

2C

1

2

8C

1

2

4C

1

2

16C

1

2

T1D1

12 T2

D2

12 T3

D3

12

T4D4

12 T5 D5

12

LS1

1

2

LS2

1

2

LS3

1

2

LS4

1

2

LS5

1

2

2C

1

2

C1

2

8C

1

2

4C

1

2

16C

1

2

T6

D6

1

2

T7

D7

1

2

T8

D8

1

2

T9

D9

1

2

T10

D10

1

2

LS

6 1

2

LS

7 1

2

LS

8 1

2

LS

9 1

2

LS

10 1

2

C

1

2

8C

1

2

2C

1

2

4C

1

2

16C 1

2

T11

D11

1

2

T12

D12

1

2

T13

D13

1

2

T14

D14

1

2

T15

D15

1

2

LS

11

1

2

LS

12

1

2

LS

13

1

2

LS

14

1

2

LS

15

1

2

N

Ai

Bi

Ci

Av

Bv

Cv

N

CAiLBi

CCi LAi LCiCBi

Three phase loadCompensator power circuit

Figure 4. The power circuit of the three-phase power factor correction system.

Figures 6 and 7 show the circuit diagrams of the single-phase and the three-phase automatic power factor correction systems respectively. The simulation results will be extracted from running these systems on PSpice. RESULTS The basic capacitance C was chosen to be 50 µF for both single-phase and three-phase systems. The power system network has a frequency of 50 Hz and a phase voltage of 240 volts (r.m.s value). Consequently, the single-phase reactive current rating is 165 A (peak value). Figure 8 shows PSpice tests for the single-phase system.

The first test corresponds to the case at which the load

impedance (ZL) was o3725.1 . The power factor for

this load is 0.8 lagging. The reactive component of the load current was 163A (peak value) which was within the compensator rating. Consequently the compensator generated a capacitive reactive current completely cancelled the load current reactive component yielding a real total current (iT) as shown in Figure 8a. The second

test corresponds to an inductive load of o5325.1 .

The reactive component for that load was 217.6A (peak value) which exceeded the system rating by 52.6A (peak value). Therefore the power factor for that load was only improved as shown in Figure 8b. Figure 9 shows tests corresponding to the three-phase system. DISCUSSION Figure 9a concerns a balanced three-phase inductive


RC

differentiator

/rectifier(1)

iCB

iCC

Phase A capacitor bank

Three phase load

iCA

C.T

VGT3

VGT2

VGT1

VGT5

VGT4

RC

differentiator

/rectifier(1)

Phase B capacitor bank

VGT8

VGT9

VGT10

VGT6

VGT7

KiLC

KiLB

KiLA

VT9

VT10

VT7

VT8

VT6

D6

D7

8-bit ADC

D3

D4

D5

D1

D2

CNVRT

IN

D0

U5D

74AC0812

1311

U6B

74AC084

56

U6C

74AC089

108

U7B

74AC084

56

U7C

74AC089

108

Amplifier

Phase B driving circuit

Sample/hold

circuit

Analogue

differentiator

Zero-crossing

detector(2)

RC

differentiator

/rectifier(2)

Phase B triggering circuit

Zero-crossing

detector(1)

K*VA

ViB

ViA

K*VC

K*VB

ViC

VB

VA

V.T

N

VC

V1A

RC

differentiator

/rectifier(1)

Phase C capacitor bank

C.T

VGT15

VGT12

VGT13

VGT14

VGT11

V.T

VT15

VT13

VT14

VT11

VT12

8-bit ADC

D5

D6

D7

D2

D3

D4

D0

D1

CNVRT

IN

U7D

74AC0812

1311

V1B

U8B

74AC084

56

U8C

74AC089

108

U9B

74AC084

56

U9C

74AC089

108

Amplifier

Phase C driving circuit

Sample/hold

circuit

Analogue

differentiator

VT1

Zero-crossing

detector(2)

VT3

VT2

VT4

8-bit ADC

VT5

V1C

Phase C triggering circuit

RC

differentiator

/rectifier(2)

D5

D6

D7

D3

D4

Zero-crossing

detector(1)

D0

D1

D2

CNVRT

IN

U1A

74AC081

23

U2B

74AC084

56

U3C

74AC089

108

U4B

74AC084

56

U5C

74AC089

108

Amplifier

V.T

Phase A driving circuit

Sample/hold

circuit

Analogue

differentiator

Zero-crossing

detector(2)

V2C

V2B

V2A

V3C

V3B

V3AV4A

RC

differentiator

/rectifier(2)

Phase A triggering circuit

Zero-crossing

detector(1)

V4C

V4B

V5B

V5A

V5C

iA

iB

iC

C.T

iLB

iLA

iLC

Figure 5. The proposed three-phase power factor correction system scheme.


R8

1k

21 C3500n1 2

R10150

2

10

0

D3BAW62

R11220

2

1

C212nF

1

2

R1

2k

21

0

0

0

0

R250

2

1

Zero-crossing detector(1)

+5V

-5V

C4

1u

1 2

R72k

21

V4V5

0

U30A

74ACT04

1 2

0

R96.2k

2

1

+10V

R12

10k

2

1

-10V

U8

OP-184/AD

+3

-2

V+

7V

-4

OUT6

KiV1

Analogue differentiator Zero-crossing detector(2)

V2

RC differentiator(1)

RC differentiator(2) Amplifier

0

D1BAW62

U13

AD8042a/AD

+3

-2

V+

7V

-4

OUT6

-5V

+5V

U16

AD8042a/AD

+3

-2

V+

7V

-4

OUT6

-5V

+5V

U18

AD8042a/AD

+3

-2

V+

7V

-4

OUT6

+5V

0

-5V

-10V

V4

10V

0

V2

10V

+10V

V1

5V

+5V

0

0

-5V

V3

5V

U21

AD8042a/AD

+3

-2

V+

7V

-4

OUT6

+5V

-5V

U24

AD8042a/AD

+3

-2

V+

7V

-4

OUT6

-5V

+5V

0

R165k

2

1

0

R215k

2

1

K*v

0

U12C74ACT08

10

98

R52k

21

+10V

R68k

21-10V

U31B74ACT084

56

VT3

VT4

U2

LT1112/LT

+3

-2

V+

8V

-4

OUT1

VT1

VT2

C1100n1 2

0

R4470

2

1

U23A74ACT08

1

23

U31D74ACT08

13

1211

U19ADC8break

DB716

DB615

DB514

DB413

DB312

DB211

DB110

DB09

AG

ND

8

IN1

CNVRT2

STAT3

OVER4

REF5

+5V

0

R31k

21

U1A SD5000

IN4

OUT1

VC3

SU

B2

U7AD8042a/AD

+3

-2

V+

7V

-4

OUT6

+10V

-10V

U4LT1112/LT

+3

-2

V+

8V

-4

OUT1

U32C74ACT0456

V4

0

C6

100n1

2

R20560

21

+5V

0

C9

100n1

2

R30560

210

R285k

2

1

U22AD8042a/AD

+3

-2

V+

7V

-4

OUT6

0

R295k

2

1

V5

0

0

+5V

C5

100n1

2

R15560

21

VT5

U33A74ACT08

1

23

U11AD8042a/AD

+3

-2

V+

7V

-4

OUT6

U14AD8042a/AD

+3

-2

V+

7V

-4

OUT6

+10V

0

VGT5

0

+10V

iT

Binary thyristor switched-capacitor bank

iL

Capacitor bank driving circuit

T1 driving circuit

0

T2 driving circuit

VT2

Power circuit

U26

A4N47A

0 R35

220

2

1R40

5k2 1

R4522k2 1

R504.7k

2 1

Q2

Q2N3904

Q7

Q2N2222A

R551k

2 1

VGT2 +10V

VT1

U25

A4N47A

0 R34

220

2

1R39

5k2 1

R4422k2 1

R494.7k

2 1

Q1

Q2N3904

Q6

Q2N2222A

R541k

2 1

0

T3 driving circuit

VT3

U27

A4N47A

0 R36

220

2

1R41

5k2 1

R4622k2 1

R512k

2 1

Q3

Q2N3904

Q8

Q2N2222A

R561k

2 1

+10VVGT3+10V

0

T4 driving circuit

LS5

20uF

1

2

VT4

C14800uF

1

2

VGT5

U28

A4N47A

0 R37

220

2

1R42

5k2 1

LS1

5uF

1

2

R4722k2 1

R521k

2 1

C1050uF

1

2

T1

CS

19-12

Q4

Q2N3904

LS2

5uF

1

2

VGT1

LS3

10uF

1

2

LS4

20uF

1

2

C11100uF

1

2

C12200uF

1

2

C13400uF

1

2

Q9

Q2N2222A

T2

CS

19-12 VGT4VGT3

T3

50

RIA

120VGT2

R571k

2 1

DT1

HF

A25T

B60

31

VGT4 +10V

DT2

HF

A25T

B60

31

DT3

HF

A25T

B60

31

DT4H

FA

25T

B60

31

DT5

HF

A25T

B60

31

VGT1

K*v

V5

FR

EQ

= 50H

zV

AM

PL = 3

40V

VO

FF

=

0

RVT22k

2

1

0

RVT199k

2

1

T4

2N

18

04

Load impedance

T5

2N

18

04

Voltage transformer

AC supply

Ki

RCT

0.01

2

1 Current transformer

L

2.365mH

1

2

R

1

2

1

iC

0

T5 driving circuit

VT5

U29

A4N47A

0 R38

220

2

1R43

5k2 1

R4822k2 1

R531k

2 1

Q5

Q2N3904

Q10

Q2N2222A

R581k

2 1

+5V

U5B

74ACT04

3 4

R32

1.8k

2 1

R33

200

2 10

0

+5V

0

C7

100n1

2

0

R24560

21

R255k

2

1

U17AD8042a/AD

+3

-2

V+

7V

-4

OUT6

0

0

0

+5V

C8

100n1

2

R26560

21

U20AD8042a/AD

+3

-2

V+

7V

-4

OUT6

0

0

U9

AD8042a/AD

+3

-2

V+

7V

-4

OUT6

-5V

+5V

Sample/Hold circuit

U6

AD8042a/AD

+3

-2

V+

7V

-4

OUT6

+5V

-5V

0

R275k

2

1

DB7

Vi

R172k

2

1

0

U10

AD8042a/AD

+3

-2

V+

7V

-4

OUT6

-5V

+5V

+10V

0

R232k

2 1

R222k

2

1-10V

U15

OP-184/AD

+3

-2

V+

7V

-4

OUT6

0

R141k

2

1

R1382k

2

1

R18128k

2

1

0

R192k

2

1

DB6

DB3

DB4

DB5

Logic circuitPricision comparators Output circuit8-bit ADC

Capacitor bank triggering circuit

D2BAW62

0

U3

AD8042a/AD

+3

-2

V+

7V

-4

OUT6

-5V

+5V

0

R315k

2

1

V3

Figure 6. The circuit diagram of the single-phase power factor correction system.

load operating at a 0.8 lagging power factor and exhibiting balanced reactive current components of 163A (peak value). The compensator corrected the power factor to unity for the three-phase load, since the reactive current demands were within its rating. Figure 9b concerns a balanced three-phase inductive load exhibiting balanced reactive current components exceeding the compensator rating, therefore the system was not capable to completely cancel the three-phase reactive current components, but certainly had improved the power factor. Figure 9c shows the response of the

three-phase system to a three-phase load balanced in magnitude, but unbalanced in phase. Finally, the compensator was completely relaxed while it was dealing with a balanced three-phase real load as shown in Figure 9d. Conclusion The proposed single-phase and three-phase automatic power factor correction systems have certain reactive


U2

0

OP

-18

4/A

D

+3

-2

V+

7

V-

4

OU

T6

0

VG

T3

VG

T4

C1

100n

12

D8

BA

W6

2

R3

2220

21

0

T3

50RIA120

KiC

C4

12nF

1 2V1C

Analogue differentiator


V2C

R1

0470

21

R2

2k

21

T11 driving circuit


ViC


0

0

Amplifier

0

VG

T2

R1

63

1k

21

T12 driving circuit

0

0 R6

50

21

VT

12

VG

T4

DT

1

HFA25TB60

3 1


+5V

U7

9

A4

N4

7A

-5V

+10V

DT

2

HFA25TB60

3 1

C1

1

1u

12

DT

3

HFA25TB60

3 1

0R

11

1

220

21

R2

22k

21

U6

4A

74

AC

T0

8

123

R1

26

5k

21

DT

4

HFA25TB60

3 1

V4B

DT

5

HFA25TB60

3 1

R1

41

22k

21

0

0

V5B

U1

1B

74

AC

T0

4

34

U4

9B

74

AC

T0

8

456

D3

BA

W6

2

R1

56

4.7

k

21

0

R2

46

.2k

21

Q12

Q2

N3

90

4

U4

8

AD

C8

bre

ak

DB

716

DB

615

DB

514

DB

413

DB

312

DB

211

DB

110

DB

09

AGND8

IN1

CN

VR

T2

STA

T3

OV

ER

4

RE

F5

+10V

R3

5

10k

21


0

-10V

+5V

R5

1k

21

Q27Q

2N

22

22

A

U1

9

OP

-18

4/A

D

+3

-2

V+

7

V-

4

OU

T6

U1

AS

D5

00

0

IN4

OU

T1

VC

3

SUB2

R1

71

1k

21

iB

KiB

U1

5A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

iLB

V2B

V1B

+10V

VG

T12



ViB

T6 driving circuit

VT

11

iCB


+10V

U7

8

A4

N4

7A


-10V

U6

LT1

11

2/L

T+

3

-2

V+

8

V-

4

OU

T1

Amplifier

0

T7 driving circuit

0

U2

4A

74

AC

T0

41

2

R1

10

220

21R

12

55k

21

Phase B power circuit

VT

7

VG

T1

V4A

U7

4

A4

N4

7A

R1

40

22k

21

0

R1

55

4.7

k

21

C1

6

100n

1 2

0R

10

6

220

21

R5

6560

21

Q11

Q2

N3

90

4

R1

21

5k

21

0

R1

36

22k

21

+5V

0

Q26Q

2N

22

22

A

C2

5

100n

1 2

D2

BA

W6

2

R8

8560

21

R1

51

4.7

k

21

R1

70

1k

21

0

Q7

Q2

N3

90

4

R7

65k

21

U6

1A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

0

T13 driving circuit

0

R7

75k

21

VT

13

Q22Q

2N

22

22

A

U8

0

A4

N4

7A

V5A

0

0

R1

66

1k

21

0

+5V

C1

3

100n

1 2

R1

12

220

21

VG

T7

R4

2560

21

R1

27

5k

21

R5

32k

21

+10V

0

R1

42

22k

21

VT

6

U2

7

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

R1

57

2k

21

VT

5

U7

3

A4

N4

7A

+5V

U2

9A

74

AC

T0

81 2

3

Q13

Q2

N3

90

4

0

-5V

0R

10

5

220

21

+10V

U2

8A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

R7

22k

21

R6

72k

21

R1

20

5k

21

Q28Q

2N

22

22

A

-10V

U4

3

OP

-18

4/A

D

+3

-2

V+

7

V-

4

OU

T6

U3

6A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

R1

35

22k

21

R1

50

4.7

k

21

R1

72

1k

21

Q6

Q2

N3

90

4

Phase C triggering circuit

0 R4

41k

21

+10V

+10V

VG

T13

R3

982k

21

U3

4

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

K*vA

R5

4128k

21

Q21Q

2N

22

22

A

-5V

+5V

0

0

U4

4

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

R6

22k

21

R1

65

1k

21

-5V

+5V

0

U5

2

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

+5V

T8 driving circuit

-5V

VT

8

U6

0

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

U7

5

A4

N4

7A

+5V

0R

10

7

220

21

-5V

U6

7

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

R1

22

5k

21

-5V

+5V

R1

37

22k

21

S

V5

Implementation = vA

0

R4

85k

21

R1

52

2k

21

Q8

Q2

N3

90

4

0

+10V

R6

35k

21

Q23Q

2N

22

22

A

0

T14 driving circuit

LS

15

20uF

1 2

R1

67

1k

21

VG

T8

+10V

VT

14

U3

3

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

C42

800u

F

12

+5V

VG

T15

-5V

U4

2

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

U8

1

A4

N4

7A

+5V

-5V

U5

1

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

-5V

+5V

U5

9

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

0

T9

2N1804

+5V

-5V

U6

6

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

K*vC

R1

13

220

21

+5V

0

-5V

R4

75k

21

0

R1

28

5k

21

+10V

0

U4

9A

74

AC

T0

8

123

R6

15k

21

R1

72k

21

0

T9 driving circuitL

S10

20uF

1 2

LS

11

5uF

1 2

R1

43

22k

21

R1

58

1k

21

VT

9

C38

50u

F

12

C37

800u

F

12

+10V

VG

T10

U7

6

A4

N4

7A

T11

CS19-12

I

Q14

Q2

N3

90

4

VG

T11

LS

12

5uF

1 2

R1

88k

21 -1

0V

0

LS

13

10uF

1 2

U4

0B

74

AC

T0

84 5

6

K*vB

LS

14

20uF

1 2

R1

08

220

21

C39

100u

F

12

0

R1

23

5k

21

C40

200u

F

12

U4

0D

74

AC

T0

8

13

12

11

VT

14

VT

13

R1

52k

21

C41

400u

F

12

U4

LT1

11

2/L

T

+3

-2

V+

8

V-

4

OU

T1

LS

6

5uF

1 2

VT

12

VT

11

R1

38

22k

21

Q29Q

2N

22

22

A

R1

53

1k

21

T12

CS19-12

C33

50u

F

12

+10V

T6

CS19-12

Q9

Q2

N3

90

4

VG

T6

LS

7

5uF

1 2

R1

68k

21 -1

0V

LS

8

10uF

1 2

U4

0A

74

AC

T0

81 2

3

LS

9

20uF

1 2

C34

100u

F

12

C35

200u

F

12

VT

8

VT

9

S

V6

Implementation = vB

C36

400u

F

12

U3

LT1

11

2/L

T

+3

-2

V+

8

V-

4

OU

T1

VT

6

VT

7

Q24Q

2N

22

22

A

T7

CS19-12

iA

T10

2N1804

Phase C driving circuit

Phase C power circuit

S

V7

Implementation = vC

iLC

iC

iCC

iLA

+5V

U1

1D

74

AC

T0

4

98

RV

T4

2k

21

RV

T1

99k

21

0

R9

4

1.8

k

21

R9

5200

21

0

0

0

+5V

C1

9

100n

1 2

0

R6

9560

21

R7

35k

21

U4

5A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

00

0

+5V

C2

2

100n

1 2

R7

8560

21

U5

5A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

0

0

U2

1

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

-5V

+5V

Sample/Hold circuit

U1

2

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

+5V

-5V

0

R8

15k

21

Load impedance

DB7A

DB4A

DB5A

DB6A

DB3A

Logic circuit

Output circuit

8-bit ADC

Pricision comparators

Voltage transformer

Current transformer

AC supply

KiA

RC

T1

0.0

1

21

LA

1

2.3

65

mH

1 2

RA

1

1

21

Phase A triggering circuit

T14

2N1804

D4

BA

W6

2

0

U5

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

-5V

+5V

Phase B triggering circuit

0

R9

15k

21

0

T5 driving circuit

VT

5

U7

2

A4

N4

7A

T4

2N1804

0R

10

4

220

21R

11

95k

21

R1

34

22k

21

V3A

R1

49

1k

21

Q5

Q2

N3

90

4

R5

22k

210

VG

T13

VG

T14

Q20Q

2N

22

22

A

C5

100n

12

U2

6

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

0

T13

50RIA120

+5V

R1

64

1k

21

0

-5V

+10V

R6

82k

21

R1

2470

21

+10V

VG

T5

R6

62k

21-1

0V

0

R2

0

1k

21

U3

9

OP

-18

4/A

D

+3

-2

V+

7

V-

4

OU

T6

R1

73

1k

21

VG

T12

C7

500n

12

R2

8150

21

0 R4

11k

21

VG

T14

DT

11

HFA25TB60

3 1

R3

882k

21

+10V

0

0

D7

BA

W6

2

DT

12

HFA25TB60

3 1

DT

13

HFA25TB60

3 1

R5

1128k

21

R3

1220

21

0

C2

12nF

1 2

U6

4C

74

AC

T0

8

109

8

R5

72k

21

R1

2k

21

DT

14

HFA25TB60

3 1

DT

15

HFA25TB60

3 1

U4

9D

74

AC

T0

8

13

12

11

0

0

00

U5

4A

DC

8b

rea

k

DB

716

DB

615

DB

514

DB

413

DB

312

DB

211

DB

110

DB

09

AGND8

IN1

CN

VR

T2

STA

T3

OV

ER

4

RE

F5

R4

50

21


+5V

0

-5V

+5V

R9

1k

21

VG

T9

C3

100n

12

VG

T8

C1

0

1u

12

U1

CS

D5

00

0

IN12

OU

T9

VC

11

SUB2

R1

92k

21

0

T8

50RIA120

V4A

U1

7A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

V5A

R1

1470

21

0

U1

1A

74

AC

T0

4

12

-10V

+10V

0

R2

16

.2k

21

VG

T7

U1

0L

T1

11

2/L

T+

3

-2

V+

8

V-

4

OU

T1

R1

68

1k

21

+10V


R3

4

10k

21

U2

4C

74

AC

T0

45

6

-10V

VG

T11

VG

T9

DT

6

HFA25TB60

3 1

0

+10V

V4C

DT

7

HFA25TB60

3 1

U1

8

OP

-18

4/A

D

+3

-2

V+

7

V-

4

OU

T6

DT

8

HFA25TB60

3 1

C1

8

100n

1 2

U6

4B

74

AC

T0

8

456

KiA

R5

9560

21

V1A

DT

9

HFA25TB60

3 1


V2A

0

DT

10

HFA25TB60

3 1

T1 driving circuit


+5V

C2

7

100n

1 2


ViA

R9

0560

21

U4

9C

74

AC

T0

8

109

8

Phase A driving circuit


Amplifier

0

R8

65k

21

T2 driving circuit

0

U5

3 AD

C8

bre

ak

DB

716

DB

615

DB

514

DB

413

DB

312

DB

211

DB

110

DB

09

AGND8

IN1

CN

VR

T2

STA

T3

OV

ER

4

RE

F5

U6

3A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

VT

2

Phase A power circuit

0

R8

75k

21

U6

9

A4

N4

7A

+5V

0

R7

1k

21

0

0

V5C

R1

01

220

21

U1

BS

D5

00

0

IN5

OU

T8

VC

6

SUB2

+5V

0

C1

5

100n

1 2

R1

16

5k

21

U1

6A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

R1

31

22k

21

R4

5560

21

0

D1

BA

W6

2

+10V

R1

46

4.7

k

21

-10V

VT

15

U8

LT1

11

2/L

T+

3

-2

V+

8

V-

4

OU

T1

U2

9C

74

AC

T0

810 9

8

Q2

Q2

N3

90

4

U2

4B

74

AC

T0

43

4

U3

1A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

VG

T6

V4B

U3

8A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

Q17Q

2N

22

22

A

0

C1

7

100n

1 2

R1

61

1k

21

R5

8560

21

+10V

+10V

VG

T2

+5V

0

K*vC

VT

1

C2

6

100n

1 2

0R

89

560

21

T5

2N1804

U6

8

A4

N4

7A

0

R8

45k

21

0R

10

0

220

21

U6

2A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

R1

15

5k

21

0

R1

30

22k

21

R8

55k

21

R1

45

4.7

k

21

+5V

V5B

0

0

Q1

Q2

N3

90

4

U1

1F

74

AC

T0

4

13

12

+5V

C1

4

100n

1 2

RV

T6

2k

21

R4

3560

21

0

RV

T3

99k

21

Q16Q

2N

22

22

A

R9

8

1.8

k

21

VT

10

R9

9200

21

R1

60

1k

21

U2

9B

74

AC

T0

84 5

6

0

U3

0A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

0

T3 driving circuit

0

0

VT

3

U7

0

A4

N4

7A

U3

7A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

0

+5V

C2

1

100n

1 2

R7

1560

21

0R

10

2

220

21

+10V

R1

17

5k

21

R7

55k

21

K*vB

U4

7A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

R1

32

22k

21

0

R1

47

2k

21

0

Q3

Q2

N3

90

4

0

0

+5V

C2

4

100n

1 2

R8

0560

21

Q18Q

2N

22

22

A

+5V

U5

7A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

R1

62

1k

21

U1

1E

74

AC

T0

4

11

10

0

+10V

VG

T3

RV

T5

2k

21

0

U3

2

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

0

RV

T2

99k

21

U2

3

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

-5V

+5V

R9

6

1.8

k

21

-5V

+5V

U4

1

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

R9

7200

21

Sample/Hold circuit

-5V

+5V

U1

4

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

U5

0

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

+5V

-5V

0

+5V

0

0

0

-5V

R8

35k

21

+5V

0

-10VV

4

10V

0

C2

0

100n

1 2

iCA

Load impedance

0 V1

10V

R7

0560

21

DB7C

DB4C

DB5C

DB6C

+10V

V2

5V

R7

45k

21

DB3C

0

+5V

U4

6A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

Logic circuit

-5V

0

Output circuit

V3

5V

8-bit ADC


0

Voltage transformer

0

U5

8

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

Current transformer

AC supply

+5V

0

KiC

RC

T3

0.0

1

21

C2

3

100n

1 2

+5V

R7

9560

21

-5V

LC

1

2.3

65

mH

1 2

U6

5

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

U5

6A

D8

04

2a

/AD

+3

-2

V+

7

V-

4

OU

T6

RC

1

1

21

+5V

0

-5V

R4

65k

21

Phase B driving circuit

0

D6

BA

W6

2

0

+10V

U2

2

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

0

R6

05k

21

0

+5V

U9

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

R4

92k

21

-5V

Sample/Hold circuit

0

T4 driving circuit

0

-5V

+5V

U1

3

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

LS

5

20uF

1 2

U2

5

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

0

+5V

+5V

T15

2N1804

R9

35k

21

0

-5V

-5V

VT

4

+10V

0

0

R8

25k

21

C32

800u

F

12

R6

52k

21

R6

42k

21

T15 driving circuit

VG

T5

U7

1

A4

N4

7A

Load impedance

-10V

VT

15

U8

2

A4

N4

7A

DB6B

DB7B

U3

5

OP

-18

4/A

D

+3

-2

V+

7

V-

4

OU

T6

DB4B

DB5B

DB3B

0 R4

01k

21

0R

11

4

220

21

R3

782k

21

Logic circuit

R1

29

5k

21

Output circuit

R5

0128k

21

8-bit ADC


R1

44

22k

21

Voltage transformer

0

KiB

V3C

Current transformer

AC supply

0

R1

59

1k

21

RC

T2

0.0

1

21

R5

52k

21

Q15

Q2

N3

90

4

LB

1

2.3

65

mH

1 2

K*vA

RB

1

1

21

R1

03

220

21

Q30Q

2N

22

22

A

0

R1

18

5k

21

D5

BA

W6

2

U4

0C

74

AC

T0

8

109

8

R1

74

1k

21

0

U7

AD

80

42

a/A

D

+3

-2

V+

7

V-

4

OU

T6

R1

32k

21

+10V

VG

T15

+5V

LS

1

5uF

1 2

0

-5V

R2

6

1k

21

0

R9

25k

21

R1

33

22k

21

C9

500n

12

R1

48

1k

21

R3

0150

21

C28

50u

F

12

0

0

0

+10V

D9

BA

W6

2

T1

CS19-12

T10 driving circuit

VT

10

Q4

Q2

N3

90

4

R3

3220

21

U7

7

A4

N4

7A

C6

12nF

1 2

VG

T1

LS

2

5uF

1 2

0

R3

2k

21

R1

09

220

21

R1

48k

21

R1

24

5k

21

0

R1

39

22k

21

0

0-1

0V

LS

3

10uF

1 2

Fig. 7 The circuit diagram of the three-phase automatic power factor correction system.

0 R8

50

21

R1

54

1k

21

V3B

U2

9D

74

AC

T0

813

12

11

Q10

Q2

N3

90

4


LS

4

20uF

1 2

-5V

+5V

C1

2

1u

12

Q25Q

2N

22

22

A

C29

100u

F

12

C30

200u

F

12

R2

52k

21

R1

69

1k

21

V4C

VT

3

0

V5C

VT

4

C31

400u

F

12

VG

T10

U1

1C

74

AC

T0

4

56

+10V

U2

LT1

11

2/L

T

+3

-2

V+

8

V-

4

OU

T1

0

0

R2

76

.2k

21

R2

3

1k

21

VT

1

VT

2

+10V

C8

500n

12

Q19Q

2N

22

22

A


R3

6

10k

21

R2

9150

21

T2

CS19-12

-10V

0

Figure 7. The circuit diagram of the three-phase power factor correction system.


(a)

Time

20ms 30ms 40ms 50ms 60ms

V(C1:1) -I(v5) -I(R) -I(RVT5)

-400

0

400

iC

iLiT

v o

LZ 3725.1

v (

Volt t

), i

L,

i C,

i T(A

mp

.)

Time(b)

Time

20ms 30ms 40ms 50ms 60ms

V(C1:1) -I(v5) -I(R) -I(RVT5)

-400

0

400

iC

iL

iT

v

v (

Volt t

), i

L,

i C,

i T(A

mp

.) o

LZ 5325.1

Time

Figure 8. (a) Unity power factor correction, (b) power factor improvement.

Av Bv Cv

LAiLBi LCi

CAiCBi CCi

AiBi

Ci

a Time

Time

20ms 30ms 40ms 50ms

V(V11:PVS) V(LB1:2) V(C41:1)

-400V

0V

400V

Time

20ms 30ms 40ms 50ms

-I(LB1) -I(LA1) -I(LC1)

-400A

0A

400A

Time

20ms 30ms 40ms 50ms

-I(R175) -I(R176) -I(R177)

-200A

0A

200A

Time

20ms 30ms 40ms 50ms

I(R179) I(R178) I(R180)

-400A

0A

400A

voltagesphase ac

currentsline Load

currents

rCompensato

currents linesupply ac

Av Bv Cv

LAiLBi

LCi

CAiCBi CCi

Ai Bi Ci

b Time

Time

20ms 30ms 40ms 50ms

V(R178:2) V(R179:2) V(C41:1)

-400V

0V

400V

Time

20ms 30ms 40ms 50ms

-I(R177) -I(R176) -I(R175)

-200A

0A

200A

Time

20ms 30ms 40ms 50ms

-I(LA1) -I(LB1) -I(LC1)

-400A

0A

400A

Time

20ms 30ms 40ms 50ms

I(R179) I(R178) I(R180)

-200A

0A

200A

voltagesphase ac

currentsline Load

currentsrCompensato


Av BvCv

LAiLBi

LCi

CAiCBi CCi

Ai Bi Ci

c Time

voltagesphase ac

currentsline Load

currents

rCompensato


Time

20ms 30ms 40ms 50ms

V(R178:2) V(R179:2) V(C41:1)

-400V

0V

400V

Time

20ms 30ms 40ms 50ms

-I(LC1) -I(LB1) -I(LA1)

-400A

0A

400A

Time

20ms 30ms 40ms 50ms

-I(R175) -I(R176) -I(R177)

-200A

0A

200A

Time

20ms 30ms 40ms 50ms

I(R178) I(R179) I(R180)

-400A

0A

400A

Av BvCv

LAi LBiLCi

CAiCBi

CCi

AiBi

Ci

d Time

voltagesphase ac

currentsline Load

currentsrCompensato


Time

20ms 30ms 40ms 50ms

V(LA1:2) V(C33:1) V(RVT3:2)

-400V

0V

400V

Time

20ms 30ms 40ms 50ms

-I(LA1) -I(LB1) -I(LC1)

-400A

0A

400A

Time

20ms 30ms 40ms 50ms

-I(R176) -I(R175) -I(R177)

-400A

-200A

0A

200A

400A

Time

20ms 30ms 40ms 50ms

I(R178) I(R180) I(R179)

-400A

0A

400A

Figure 9. Performance of the three-phase compensator during (a) a balanced full load

of 0.8 lagging power factor, (b) a balanced full load of 0.6 lagging power factor, (c) a full load balanced in magnitude and unbalanced in phase, (d) a balanced full resistive load.

230 Sci. Res. Essays current or reactive power ratings. When the detected reactive power absorbed by the load is greater than the compensator rating, the power factor will not be corrected to unity, but certainly will be improved and the apparent power supplied by the ac supply will be reduced. These systems respond almost linearly throughout their pre-assigned areas of operation. They achieve better power quality by reducing the apparent power drawn from the ac supply and minimizing the power transmission losses. In addition, no harmonics disturbing the power system network are released, and hence no filtering is required. The responses of both systems are settled down within the power system network fundamental cycle. There is a feasibility of utilizing this technique for designing systems with high voltage and current ratings. Since this technique is not dealt with accomplishing balanced three-phase currents, the future work will be extended to design an integrated system capable of achieving both power factor correction and load balancing. REFERENCES Best RA, La Parra HZ (1996). Transient response of a static Var shunt

compensator. IEEE t Power Elect., 11(3): 489-494. Bimal KB (2006). Power electronics and motor drives. Elsevier Inc. Chen JH, Lee WJ, Chen MS (1999). Using a static Var compensator to

balance a distribution system. IEEE Ind. Appl., 35(2): 298-304. Dai D, Li S, Ma X, Tse CK (2007). Slow-scale instability of single-stage

power-factor correction power supplies. IEEE T Circuits Syst., 54(8):

1724-1735.

Gyugy L, Otto RA, Putman TH (1978). Principles and applications of

static, thyristor-controlled shunt compensators. IEEE t Power Appl. Syst., PAS-97: 1935-1945.

Idris RM, Khairuddin A, Mustafa MW, Kalam A (2010). Optimal allocation of multi-type FACTS devices using Bees Algorithm for ATC enhancement in deregulated power system, int. rev. Elect. Eng., 5(2):

644-651. Lee S-Y, Wu C-J (2000). Reactive power Compensation and load

balancing for unbalanced three-phase four wire system by a

combined system of an SVC and a series active filter. IEE p-Elect Pow Appl., 147(6): 563-571.

Lupin JM, Chenevard L, Peronnet J (2007). Energy efficiency

improvement through optimization of the power factor correction. In: Proceed. 19

th Int. Conf. Elect. Distr. Held Vienna, pp. 1-4.

Mehrdad M (2005). Saving through power quality. In: Proceeding of the

Twenty-Seventh Industrial Energy Technology Conference held at New Orleans, pp. 1-6.

Miller TJ (1982). Reactive power Control in Electric Systems. John Willey

& Sons. Nandi S, Biswas P, Nandakumar V, Hegde R (1997). Two novel

schemes suitable for static switching of three-phase delta-connected

capacitor banks with minimum surge current. IEEE t Ind. Appl., 33(5): 1348-1354.

Rashid M (2001). Power electronics handbook. Academic Press.

Stahlkopf KE, Wilhelm MR (1997). Tighter controls for busier systems. IEEE Spectrum., 34(4): 48-52.

Teleke S, Abdulahovic T, Thiringer T, Svensson J (2008). Dynamic

performance comparison of synchronous condenser and SVC. IEEE t Power Deliv., 23: 1606-1612.

Walker L (1986). Force-commutated reactive power compensator. IEEE t

Ind. Appl., IA-22: 1091-1104.

Design of an almost continuously controlled three- phase ...

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