Design of a Modular UPQC Configuration Integrating a Components Economical Analysis

IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 24, NO. 4, OCTOBER 2009 1763

Design of a Modular UPQC Configuration Integratinga Components Economical Analysis

Javier A. Muñoz, Student Member, IEEE, Jose R. Espinoza, Member, IEEE, Luis A. Moran, Fellow, IEEE, andCarlos R. Baier, Student Member, IEEE

Abstract—A design procedure to select the components in amodular unified power-quality conditioner configuration basedon single-phase cells is presented. The procedure is based on thefact that the load and distributor operating conditions range areknown and it is required to impose stiff operating conditions inboth the load side (regulation) and the point of common couplingside (power factor). Due to the arbitrary number of cells to be usedin a modular approach, the proposed design procedure allows toselect the power semiconductors and capacitors based on an eco-nomical evaluation, so an optimal number of cells can be chosento minimize the overall power cell cost. This design procedure iswell suited for modular configurations, where several degrees offreedom are not covered if just technical criteria are followed.Thus, an economic approach can be used to select the appropriatecomponents. The rest of the devices, i.e., the transformers turnratio and passive filters, are chosen using classical design methodsbased on technical issues such that the power cells operate withinits permissible ratings. A practical case evaluation is presented fora medium voltage system application.

Index Terms—Power quality (PQ), power device economics, uni-fied power-quality conditioner (UPQC).

I. INTRODUCTION

P OWER-QUALITY problems have been studied by severalauthors [1]–[6] and they agree that a compensation stage

between the electrical energy distributor and consumers thatuse critical loads is necessary. The unified power-quality con-ditioner (UPQC) [7] has achieved prominence in recent yearsas an alternative for solving the power-quality problem, due toits simultaneous compensating capabilities for both the distrib-utor side and the load side. This is mainly because it combinesthe DVR and DSTATCOM features in just one topology, thanksto its dc link back-to-back configuration. Particularly, the topo-logic features of this equipment allow the simultaneous voltageregulation on the load side and the power factor correction at thepoint of common coupling (PCC) [8]–[13].

As a result of technological restrictions on power semicon-ductors ratings, it is necessary the use of novel UPQC multileveltopologies in order to reach higher power levels and, in addition,to comply with the power-quality standards. Up to now, sev-eral topologies have been proposed to overcome the semicon-ductors rating limitation, like including neutral point-clamped

Manuscript received January 21, 2009; revised April 24, 2009. Current ver-sion published September 23, 2009. This work was supported by the ChileanGovernment under Project FONDECYT 108-0247. Paper no. TPWRD-00019-2009.

The authors are with the Department of Electrical Engineering, Universidadde Concepción, Concepción 160-C, Chile (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

Digital Object Identifier 10.1109/TPWRD.2009.2028795

Fig. 1. Proposed UPQC topology based on power cells.

(NPC) converters or structures based on power cells [14]–[18].This last approach allows the symmetrical distribution of theload power among each component of the topology; however,due to the high number of components of these configurations,classic design methods [19]–[21] must be modified and/or re-fined in order to ensure that the power cell components do notexceed its maximum ratings.

A modular UPQC configuration for medium-voltage systemsis proposed in this work. The topology is built-up upon single-phase cells and presents an interesting challenge in the specifi-cation of the various components. This is because there are sev-eral aspects in the design problem—as preventing the selectionsub or over dimensioned of the elements—that can be analyzedconsidering the costs of the power components.

II. PROPOSED TOPOLOGY

The UPQC basic topology can be redefined so as to includea multiple-cell arrange in order to reach higher power levels,while overcoming the limits of the semiconductors rating. Par-ticularly, the electric variable that limits the operation of the se-ries compensator in the UPQC is the total current according tothe transformer turn ratio; and for the shunt compensator is thetotal voltage, because it has to deal with the total load voltage,this is fairly detailed in [18]. The proposed configuration allowsto overcome these limitations interconnecting multiple cells asshown in Fig. 1. This connection is preferred to provide a wayfor the PCC current and load voltage to be shared among all themodules of the configuration. This justifies the parallel connec-tion at the series side of the cells and the series connection at theshunt side of the cells.

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1764 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 24, NO. 4, OCTOBER 2009

Fig. 2. Simplified power cell circuit.

The proposed topology makes the compensation in a sepa-rated way for each phase because the power cells are based onsingle-phase converters in both the series and shunt sides asseen in Fig. 2. Fig. 1 depicts the UPQC proposed configura-tion, where we can see cells per phase and thus 3 cellsfor the total system. The connection between the cells and theelectrical system is done as in standard UPQCs. That is, the se-ries side compensator is connected through a series transformer,so the load voltage is the result of the addition of the PCCvoltage and the injected series voltage ; and the shuntside of the compensator is connected at the same load voltage,so the PCC current is composed of the load current andthe shunt current of the UPQC.

Fig. 2 shows the scheme of a single cell where the superscriptis for the phase, with and is for the cell number,

with . Each cell is composed of a series con-verter, shunt converter, and a dc link. The series compensatormust compensate PCC voltage disturbances like sags, swellsand flickers, while the shunt compensator must sink or injectcurrent harmonics, compensate the reactive power, and keep aconstant dc link voltage. The dc capacitor links both converters,by providing a path for the power flow between compensatorsand it can also be seen as a direct voltage source that providesthe required voltage to generate ac currents and voltages thatcompensates the voltage system disturbances. A passive filter isadded in the ac side of each converter— and for the seriescompensator and for the shunt compensator—to ensure theproper operation of the UPQC.

The number of modules in the topology and the componentsof each cell must be specified in order to satisfy some criteriathat will be detailed in the following. The elements andare used to model the losses of the components; thus, they arenot included in the design procedure.

III. PRELIMINARY CONSIDERATIONS

The design procedure is complex and in this work the knownquantities in the electrical system based on the load and distrib-utor operating ranges are firstly identified.

A. Design Constraints

The known quantities have a close relation with the levelsof the PCC voltage, load voltage, and the expected system be-havior after the compensation stage is connected. The range ofvariation of the PCC voltage must be known, for this reason, asag-swell factor is defined as the per unit PCC voltage range,considering the nominal load voltage as the base value. Hence,

. Similarly, a linear load (for design purposes)featuring a given power level is considered, but a known rangeof variation of its fundamental power factor is considered.

Fig. 3. UPQC simplified schematic.

The desired system behavior after the connection of theUPQC is to assure a constant rms value of load voltage, toensure that load voltage angle (respect to the PCC voltage) islesser than a maximum value [12], and to keep the PCC powerfactor in a specified range.

Summarizing all the constraints detailed previously, theknown quantities are:

• – : PCC voltage range (p.u.);• : nominal load voltage (rms);• : nominal load power• – : load power factor range;• – : PCC power factor range;• : maximum load voltage angle.Once the previous quantities are known, the operating range

of the key electrical variables must be found in order to specifythe rating of the power cell components of the topology. Thecircuit shown in Fig. 3 is a generalized UPQC scheme, wherethe series compensator is viewed as a controlled voltage sourcethat injects the required voltage to compensate the variations ofthe PCC voltage. Similarly, the shunt compensator is consideredas a controlled current source that injects the required current toimprove the overall load power factor.

Fig. 3 is used to find the maximum voltage value of the source, the maximum current value of the source , and the extreme

values for the PCC current . These values become valid re-gardless of the UPQC topology, due the generalized schemeshown in Fig. 3.

B. Maximum Voltage Injection

The maximum voltage injection of the series compensatornaturally depends upon the amount of sag-swell in the PCCvoltage and the desired phase angle between load voltage andPCC voltage. These ranges are combined to determine the max-imum amount of voltage to be injected for the compensator.

Fig. 4 shows that due to the fasorial addition of the voltages,there is a triangle formed by load voltage , the PCC voltage

, and the series injected voltage . Thanks to the cosinetheorem, the relations between those magnitudes and the loadangle are

(1)

The maximum phasor magnitude inspecting Fig. 4 is ob-tained when simultaneously exists a maximum sag in the PCCvoltage and a maximum phase shift between the load voltage

MUÑOZ et al.: DESIGN OF A MODULAR UPQC CONFIGURATION INTEGRATING A COMPONENTS ECONOMICAL ANALYSIS 1765

Fig. 4. Fasorial diagram of Fig. 3.

and the PCC voltage. This leads to the expression of the max-imum injected voltage given by

(2)

C. Maximum PCC Current

Regarding Fig. 3, both sources consume and/or deliver an ac-tive and reactive power that depends on the voltage and currentat each source. However, it has to be considered the fact that theactive power is the same in both controlled sources, because theconverters are linked through out a common dc capacitor and thecomponents are considered lossless (just for design purposes).Hence, making a power balance, one can write

(3)

Considering that , then from (3) one can write

(4)

In order to obtain the operating extreme values of the PCCcurrent, it is just necessary to minimize/maximize (4). Thus, theminimum and maximum per unit values of the PCC current are

(5)

(6)

D. Maximum Shunt Current

Similarly, to find the maximum circulating current expressionthrough the shunt compensator, the cosine theorem will be used

in combination with the fasorial diagram depicted in Fig. 4. Theangle formed in the currents triangle becomes

(7)

In order to calculate the maximum shunt compensator cur-rent, the cases: 1) minimum PCC current and 2) maximum PCCcurrent must be considered, as in these conditions the shunt cur-rent magnitude assumes maximum values.

In the first case, where the PCC current is a maximum, theshunt compensator current will be given by (8), shown at thebottom of the page.

Now, considering the case where the value of the PCC currentis a minimum, the shunt compensator current will be shown in(9), at the bottom of the page.

Hence, the maximum shunt compensator current will be thehighest value obtained out of (8) and (9). Hence

(10)

E. Economic Criteria Justification

The design of power electronics configurations based onpower cells considers several degrees of freedom that cannotbe totally covered by using just technical criteria. For example,in any modular configuration it is possible to choose a highnumber of cells with low rating components or a low numberof cells with higher components ratings. Both alternatives canachieve the technical equipment requirements; however, froman economical point of view, one of those options is optimum.This principle is used in this paper to develop the designprocedure.

In order to choose the best economical option, it is necessaryto know the electrical ratings of the finite set of commerciallyavailable power devices, with their respective prices, particu-larly the power semiconductors and capacitors. Let us consider:

• : -switch element ;• : Maximum allowable voltage of the -switch;• : Maximum allowable current of the -switch;• : price of the -switch;• : -capacitor element ;• : maximum allowable voltage of the -capacitor;• : capacitance value of the -capacitor;• : price of the -capacitor.Once these values are known, it is possible to make the eco-

nomic optimal election of what kind of components (semicon-ductor and capacitor) to use in the topology and then how manycells will be required in the configuration.

(8)

(9)

1766 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 24, NO. 4, OCTOBER 2009

IV. DESIGN PROCEDURE

This section presents the proposed design procedure in orderto obtain the technical features of the different elements of thetopology that complies with the constraints detailed in the pre-vious section.

A. DC Link Capacitor

Two basic principles are considered to design the dc link ca-pacitor for each cell. The first one is to limit the voltage secondharmonic present in the dc link of the single-phase cells. Thesecond capacitor design criterion is based on the ride throughcapability principle. The value of the capacitor is selected forthe most restrictive condition of both criteria exposed above.

The first criterion allows the selection of the dc link capacitorvalue in order to limit the second harmonic (located at )in the dc side voltage that is generated as a result of the single-phase connection. The expression that limits the amplitude ofthis harmonic at times the dc continuous voltage is givenby

(11)

The second design criterion allows the selection of the dc linkcapacitor value in order to make the equipment able to compen-sate the PCC voltage disturbances. During a transient period,the power flows in the UPQC are determined for the kind ofdisturbance in the system. For example, during a sag, the powerdelivered by the ac source varies proportionally to the sag mag-nitude and the rest of the load power must be delivered from thedc link capacitors of each cell.

In order to limit the voltage drop to times the dc contin-uous voltage , during a number of network voltage cycles

, when the PCC presents a voltage sag of magnitude ,the value of the dc link capacitor is given by

(12)

From expressions (11) and (12), the highest capacitor valuemust be chosen in order to assure that both criteria are fulfilled.Derivation of (11) and (12) is shown in the Appendix.

B. Series Transformer

The function of this transformer is to provide the electricalisolation between the power line and the series side of theUPQC. In addition, this transformer modifies the voltage andcurrent levels for the appropriate operation of the equipment.

The total power that has to be handled for this transformeris completely defined for the voltage and current in the primarywindings, so an economic optimization cannot be performed.Hence, the maximum voltage drop in the primary of the se-ries transformer is the same maximum injected voltage ,given by (2). The maximum primary current will be obtainedas the same maximum PCC current , due to the seriesconnection of this transformer with the line.

Thus, the total power of this series transformer, consideringthe three-phase system becomes

(13)

The transformer turn-ratio is associated with the power cellsratings, so the turn ratio selection has to be made taking into con-sideration of maximum voltage and current of the cells. In fact,to allow the series compensator to inject the maximum requiredvoltage , the maximum voltage must not be greater thanthe dc link voltage multiplied by the turn ratio . Taking theextreme case

(14)

The per unit equivalent equation of this last expression andusing the result presented in (2) for the value of , theseries transformer turn ratio becomes

(15)

C. Number of Cells

The number of cells used in the configuration dependsupon the ratings of the power semiconductor used to implementthe module. In fact, the selected semiconductor device imposesthe maximum values of voltage and current permis-sible in the cells. Thus, it is possible to establish a relation be-tween the extreme values in the semiconductor devices (voltageand current) and the number of cells to be used to assemblethe configuration. This relation can be obtained thanks to thefact that the series compensator current is shared between allthe modules and that the LC series filter gain is made unitary atfundamental frequency. The current value in the series side ofthe UPQC (which is divided for each cell due the parallel con-nection of this part of the topology) cannot be greater than themaximum allowable current of the semiconductor. The mathe-matical expression to ensure this current relation is

(16)

Expressing (16) in per unit equivalent values, the number ofcells becomes

(17)

This last result is plotted as a function of the semiconductorvoltage and current in Fig. 5. Each region in the graph representsa different number of cells to be included in the topology. It canbe appreciated that when the voltages and currents are equal toone (in p.u.), just one cell has to be included in the configura-tion, this can be explained because the semiconductor deviceshave high ratings, so it is not necessary to include several cells to

MUÑOZ et al.: DESIGN OF A MODULAR UPQC CONFIGURATION INTEGRATING A COMPONENTS ECONOMICAL ANALYSIS 1767

Fig. 5. Number of cells as function of a generic switch variables.

reach the load power levels. Contrary, when the voltage and cur-rent ratings of the semiconductors became lower, the number ofcells becomes higher, so the stress in the semiconductor devicesis lesser. Each different region in Fig. 5 represents the amountof cells to be included in the configuration as a function of thepower switch voltage and current; except the region 10, that rep-resents a number of cells grater than or equal to 10.

Fig. 5 gives us information about how many cells must be in-cluded in the topology, as a function of the semiconductor rat-ings, however we have not yet decided what kind of device willbe used in the equipment. From a technical point of view, anyoption ensures the right operation of the circuit, so in order tospecify the kind of switch an additional criterion must be de-veloped. In this work, a criterion based on the cost of the maincomponents of each cell (semiconductors and capacitors) andthe total number of these elements that will be used in the mod-ular UPQC is proposed. For example, if low rating componentsare used, they would be cheap; however, the number of cells inthe topology—according to Fig. 5—would be high, so the totalcost of the cell could be not minimal. On the other hand, if highrating components are used, it would require a reduced numberof cells; however, the cost of this kind of devices is more expen-sive than components with lower ratings, so the associated costto the total number of cells could be neither be minimal.

To find the minimum value of the total cost associated tothe cells, the cost of each semiconductor and capacitor mustbe multiplied by total number of cells in the topology obtainedthanks to the plot depicted in Fig. 5. It is well known that thereare a reduced number of semiconductor and capacitor devicesavailable in the market with standardized ratings. Thus, the fullrange of options displayed on the graph is limited to a narrowset of possible implementations of the power circuit. This setis given by the discrete component ratings that are offered bymanufacturers.

Hence, the procedure to find the optimal number of cellsbased upon an economical criterion can be summarized in thefollowing steps.

1. Find a known set of semiconductor (sw) and capacitordevices. In the case of semiconductors, voltage , cur-rent and price must be known. For capacitor,

voltage , capacitance and price are the keyvariables.

2. For each semiconductor of the previous set ( and), use (17) and Fig. 5 to determine the number of

cells to be included for a specific load condition.3. Using (11) and (12), determine the required capacitance

for the calculated number of cells. Based on thecapacitor key variables calculate the size of the capac-itor bank of each cell. Decide which capacitoroption implies the minimal cost. In other words, thecheapest capacitor of the set must be determined for eachsemiconductor.

4. Determine the total number of switches and capacitors tobe included in the topology by using the number of cellscalculated in 2. This has to be done for each switch.

5. Determine the total cost of the semiconductors andcapacitors needed to implement the configurationusing the total number of components already calculatedcombined with the information about semiconductors andcapacitors prices, and , respectively.

6. Finally, choose the option that involves the lower total costin components. This is equivalent to find the semiconductorand capacitor that minimizes the total cells cost

.These steps allow the selection of the semiconductors and

capacitors that will be used for implementing the topology withminimum cell cost.

D. Shunt Transformer

The proposed configuration includes power transformersin the shunt compensator side for each cell. This transformerelectrically isolates all cells between them. Fig. 1 indicatesthat there are as many transformers as number of cells in thetopology, which has a direct influence in the equipment totalcost. However, these various transformers can be implementedin one unique unit, using one magnetic core, one primarywinding (at the load side) and multiple secondary windings(one for each cell in the topology). This approach allows thereduction of the implementation cost of the equipment, notingthat the transformer cost does not depend in such close waywith the number of cells in the configuration, but with theload voltage and shunt reactive power to be compensated asexplained in the following.

The total power that has to be handled for this transformer isalso defined for the voltage and current in the primary windingand it’s independent of the number of cells. The maximumvoltage drop in the primary of the shunt transformer is the sameload voltage . The maximum primary current will be givenby the maximum shunt compensator current , calcu-lated in (10). Hence, the total power in the shunt transformer is

(18)

It is seen in Fig. 1 that the shunt current is the same currentthat will flow through the semiconductors in the shunt side ofthe cells due to the series assembling of the modules in the load

1768 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 24, NO. 4, OCTOBER 2009

side. To ensure that this current will not be greater than the per-missible upper limit of the current in semiconductors devices,then (19) must be satisfied

(19)

On the other hand, for the right operation of the shunt con-verter in any cell, the dc side voltage must be greater than thepeak value of the ac side voltage. This condition is naturally ful-filled in the series converter because the turn ratio of the seriestransformer has been calculated to ensure it. Contrary, in thecase of the shunt converter this constraint must be imposed atthe moment of choosing the turn ratio of the transformer .Thus, according to Fig. 2, it must be accomplished that

(20)

To convert this inequality into an equation, a security factoris introduced and defined as , where we can obtain

(21)

This security factor can be chosen to be any value graterthan 1. It is highly recommendable to choose it between 1.3 and1.5 in order to achieve that the shunt modulating index becomesnear to one. This feature allows the compensator to operatewith low harmonic injection and good converter utilization. Thechosen value of must also ensure that the shunt convertercurrent will not be grater than the semiconductor rating [left partof (21)].

E. Shunt Filter

The shunt filter is a first order inductive filter in the ac side ofthe shunt converter of each cell. Its main function in the UPQCtopology is to make the shunt converter a controlled currentsource for the rest of the power circuit, Fig. 3.

Considering that the shunt compensator must behave like acontrolled current source in order to provide the compensatingcurrent, the shunt current is required to follow a current refer-ence. However, this cannot be achieved in a perfect way becausethe current shape in the inductor depends on the voltage shapeavailable across its terminals. In this case, due to the PWM actype of voltage provided by the compensator (which must bechosen among a finite set of options), the shunt current cannotachieve an arbitrary shape. This approach is fairly explained in[21].

Using the design procedure developed in [21], the inductorvalue can be chosen such that the shunt current follows a refer-ence with a permissible error . This restriction can be obtainedchoosing the inductor value as

(22)

F. Series Filter

The series filter is a second-order LC type of filter located inthe ac side of the series converter of each cell. The main func-

Fig. 6. Design procedure flowchart.

tion of this filter is to attenuate the harmonics generated in thecommutation process. The voltage waveform in the converterac side is a PWM voltage, so the inclusion of this filter is com-pletely necessary in order to make the injected voltage a nearlysinusoidal waveform and thus comply with the harmonic injec-tion requirements in the load voltage.

The design of this filter has been studied for several authorsand they have developed many alternatives in how to choosethe value of the filter components. This paper uses the resultsobtained in [19], [20], where the filter is designed in order toachieve two important goals: 1) limit the harmonic content inthe injected voltage and 2) obtain unitary filter gain at the funda-mental frequency. The design procedure is based upon findinga high ratio between the capacitor impedance of the filter andthe equivalent impedance of the rest of the power circuit. Thishigh ratio ensures that the filter behavior is almost independentof what happens on the rest of the power circuit. The inductorvalue is chosen to limit the THD of the compensator injectedvoltage.

G. Design Procedure Summary

The flow chart on Fig. 6 summarizes the proposed design pro-cedure. Starting from the known quantities, the extreme oper-ating values must be calculated using (1)–(10). The electricalratings of the power cell are determined for all the semiconduc-tors rating. For each semiconductor , the number of cells andthe dc link capacitance must be calculated. Then, the cheapestcapacitor bank must be determined. Thus, using the semi-conductors and capacitors price, the minimal cost option mustbe chosen.

MUÑOZ et al.: DESIGN OF A MODULAR UPQC CONFIGURATION INTEGRATING A COMPONENTS ECONOMICAL ANALYSIS 1769

TABLE IPRELIMINARY DESIGN PARAMETERS

TABLE IINOMINAL LOAD PARAMETERS

TABLE IIIDESIGN CONSTRAINTS

Once the best option is determined, the number of cells andits rating is defined. The rest of parameters are calculated using(16)–(22).

V. PRACTICAL CASE EVALUATION

The proposed design procedure is evaluated for a particularcase in a medium voltage system. First, the operating conditionsare necessary to be known for both the electrical distributor andthe load. The restrictions for the distributor are summarized inTable I.

The nominal operating load conditions must be also knownto step into the design procedure. These parameters are shownin Table II.

A. Design Constraints

Using Tables I and II and (1)–(10), the topology parametersare calculated. Table III summarizes all calculations.

B. Number of Cells

To choose the number of cells to be included in the config-uration is necessary to determine what kind of semiconductordevice will be used. Naturally, this selection is made out a par-ticular set of standard available devices with known electric rat-ings and prices.

TABLE IVNUMBER OF CELLS SELECTION

For the conditions given in Table II, several switches alter-natives are considered. Particularly, this work includes deviceswith 300, 600, and 1200 V voltage ratings, and with current rat-ings from 10 to 100 A. A suitable set of capacitors is also in-cluded, ranging from 1800 to 5600 F. Fig. 5 indicates that eachkind of semiconductor is related with a number of cells inthe topology as a result of the maximum voltage and currentrating of the power cell. On the other hand, each element has itsown price also determined by its electrical characteristics. Thenumber of cells and the price of each element ( and )are listed in Table IV.

Table IV and Fig. 7 show that while the power benefits of theswitches are lower, the number of cells will be higher; however,the elements price are lower. On the other hand, for semicon-ductors with high power ratings, the number of cells is reduced,but the devices are more expensive. Therefore, it is necessary tofind the minimum value of the total cost associated to cell (semi-conductors and capacitors). This cost is calculated asthe product of the number of components in each cell, number ofcells in the topology, and the price of each element. This productis shown in Fig. 7(d).

According to Table IV, the economical best option is the600 V and 70 A voltage-current pair . This ratingrepresents a minimal cell cost to implement the topology. The

1770 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 24, NO. 4, OCTOBER 2009

Fig. 7. Number of cells selection. (a) Number of cells for each switch �� �. (b) Semiconductors cost �� �. (c) Capacitors cost �� �. (d) Total cost �� �.

TABLE VTOPOLOGY PARAMETERS

chosen capacitor bank, regarding this power cell rating, is a bankof four capacitors of 300 V–4700 F.

Fig. 5 indicates that with the chosen device the number ofcells to be included in the configuration is four per phase, sothe equipment will have 12 modules for the entire three-phasesystem.

When choosing the semiconductor, the dc link voltage of eachcell is also determined by the switch and capacitor rating. Inthis case, using a security margin of 20% the dc link voltagerecommended is 500 V.

C. Topology Parameters

Once the number of cells is already determined, the expres-sions developed earlier are used to calculate the parametervalues of the topology. Using (13) to (22) the values shown inTable V are calculated.

D. Sensitivity Analysis

A sensitivity analysis was made in order to determine the in-fluence of the main electrical parameters over the final result.Table VI shows the variation in the nominal total cost of thecells when a deviation of % is introduced in some electricalvariables.

From these last results, it can be said that the load voltage hasthe biggest impact on the total cost of the equipment. On theother hand deviations on the limits power factor (PCC and load)have small impact in the final cost.

Regarding , it can be said that it has a direct impact onthe total cost; this implies that when the voltage compensationcapabilities of the UPQC increases, the equipment cost wouldincrease in a similar proportion.

TABLE VISENSITIVITY ANALYSIS

E. Redundancy

To overcome a failure condition in the proposed UPQCtopology, redundancy can be included by adding onepower cell for each phase to keep it in stand by mode. If thisis the case, the total cells cost will be higher and the best eco-nomical option could change. The way of determine the newoptimal option is adding 1 cell in the column of Table IVand recalculate the total costs , and in Table IVand Fig. 7. In the practical case presented in this work whenredundancy is considered, the best economical optionchanges from to and the cost increasesin US $366.

F. Waveforms

Key waveforms, obtained through simulation with Psim7.0, of the proposed modular UPQC configuration are shownin Fig. 8. The waveforms show the equipment dynamicalbehaviour from an extreme operating point ( and

) changing to another extreme values (and ) at ms.

The equipment is able to maintain constant the rms loadvoltage in its nominal value (1.3 kV) and the desired powerfactor correction , although voltage perturbationsare present in the PCC. The electrical variables (voltage andcurrent) of the cells—Fig. 8(c) and (d)—always remain withinits permissible ranges, even during the transient period. Partic-ularly, the ac current does not exceed the maximum permissible70 A and voltage dc voltage is lesser than 600 V. The controlstrategy used to obtain these dynamical behavior is widelydiscussed in [18].

MUÑOZ et al.: DESIGN OF A MODULAR UPQC CONFIGURATION INTEGRATING A COMPONENTS ECONOMICAL ANALYSIS 1771

Fig. 8. Key waveforms for � � ��� and�� � ���� to � � �� and �� �

� at 30 ms. (a) Load voltage and current. (b) PCC voltage and current. (c) Shuntcurrent of each cell � . (d) Dc voltage of each cell � .

VI. CONCLUSION

It is possible to design the parameters of a multicell UPQCensuring that the semiconductors rating will be appropriated forthe equipment power levels. Thanks to the inclusion of struc-tures based on cells, the voltage and current of the semicon-ductor devices can be considered as design parameters. The useof economic criteria allows the selection of the components tobe used in the configuration based on a minimal cost option,particularly the semiconductors and capacitors. This selectionestablishes the number of cells of the topology. The rest of thetopology’s components can be designed following technical cri-teria that ensure the right operation of the chosen power semi-conductors.

APPENDIX

The highest amplitude of the second harmonic current insingle-phase converters equals the ac current amplitude. So,the worst case in a back-to-back configuration is obtained asthe sum of both ac sides currents amplitude. Thus, the second

harmonic current amplitude in the dc link of a single cell canbe supposed as

(A1)

The amplitude of the second harmonic voltage can be calcu-lated as

(A2)

Thus, to limit the amplitude of the second harmonic dcvoltage to , expression (A3) is used

(A3)

On the other hand, when a sag occurs, the loadpower is delivered from the voltage source (proportional to thesag magnitude) and from the stored energy in the capacitors ofthe UPQC. Thus

(A4)

Assuming a symetric distribution of power among the cells,each module must handle just a fraction of the total UPQCpower given by

(A5)

The energy stored in a capacitor can be calculated as

(A6)

Thus, the power delivered from the capacitor in each cell inpresence of a voltage sag is

(A7)

If the voltage drop is limited to times the dc voltage after, so and . Thus

(A7) can be rewritten as

(A8)

Combining this last result with (A5), finally the dc capacitorvalue can be obtained as

(A9)

ACKNOWLEDGMENT

The authors wish to thank the technical support provided bythe Applied Digital Control Laboratory, Universidad de Con-cepción, Chile.

1772 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 24, NO. 4, OCTOBER 2009

REFERENCES

[1] M. F. McGranaghan, R. C. Dugan, and H. W. Bety, Electrical PowerSystems Quality. New York: McGraw-Hill, 1996.

[2] T. A. Short, Electric Power Distribution Handbook. Boca Raton, FL:CRC, 2004.

[3] P. Heine, “Voltage sag distributions caused by power system faults,”IEEE Trans. Power Syst., vol. 18, no. 4, pp. 1367–1373, Nov. 2003.

[4] D. S. Dorr, M. B. Hughes, T. M. Gruzs, R. E. Jurewicz, and J. L.McClaine, “Interpreting recent power quality surveys to define theelectrical environment,” IEEE Trans. Ind. Appl., vol. 33, no. 6, pp.1480–1487, Nov./Dec. 1997.

[5] T. S. Key and J.-S. Lai, “Comparition of standards and power supplydesign options for limiting harmonic distorsion in power systems,”IEEE Trans. Ind. Appl., vol. 29, no. 4, pp. 688–695, Jul./Aug. 1993.

[6] A. Domijan, Jr., A. Montenegro, A. J. F. Keri, and K. E. Mattern,“Custom power devices: An interaction study,” IEEE Trans. PowerSyst., vol. 20, no. 2, pp. 1111–1118, May 2005.

[7] H. Fujita and H. Akagi, “The unified power quality conditioner: Theintegration of series- and shunt-active filters,” IEEE Trans. Power Elec-tron., vol. 13, no. 1, pp. 315–322, Mar. 1998.

[8] H. Fujita, Y. Watanabe, and H. Akagi, “Control and analysis of aunified power flow controller,” in Proc. IEEE/PELS PESC, 1998, pp.805–811.

[9] M. Rahman, M. Ahmed, R. Gutman, R. J. O’Keefe, R. J. Nelson, and J.Bian, “UPFC application on the AEP system: Planning considerations,”IEEE Trans. Power Syst., vol. 22, no. 4, pp. 1695–1701, Nov. 2007.

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[13] J. R. Reyes, J. R. Espinoza, and C. A. Sepúlveda, “Operating regionof single-phase UPQCs,” presented at the Conf. Rec. PESC, Recife,Brazil, Jun. 12–16, 2005.

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[15] B. Han, S. Baek, H. Kim, and G. Karady, “Dynamic characteristic anal-ysis of SSSC based on multibridge inverter,” IEEE Trans. Power Del.,vol. 17, no. 2, pp. 623–629, Apr. 2002.

[16] B.-M. Han and P. Mattavelli, “Operation analysis of novel UPFC basedon 3-level half-bridge modules,” in Proc. IEEE Bologna Power TechConf., Jun. 2003, vol. 4, pp. 307–312.

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[18] J. Muñoz, J. Reyes, J. Espinoza, I. Rubilar, and L. Morán, “Anovel multi-level three-phase UPQC topology based on full-bridgesingle-phase cells,” in Proc. Conf. Rec. IEEE IECON, Nov. 2007, pp.1787–1792.

[19] S. S. Choi, B. H. Li, and D. M. Vilathgamuwa, “Design and analysisof the inverter-side filter used in the dynamic voltage restorer,” IEEETrans. Power Del., vol. 17, no. 3, pp. 857–864, Jul. 2002.

[20] S. S. Choi, B. H. Li, and D. M. Vilathgamuwa, “On the injection trans-former used in the dynamic voltage restorer,” in Proc. Conf. Rec. IEEEPOWERCON, Dec. 2000, vol. 2, pp. 941–946.

[21] L. A. Morán, L. Fernández, J. W. Dixon, and R. Wallace, “A simple andlow-cost control strategy for active power filters connected in cascade,”IEEE Trans. Ind. Electron., vol. 44, no. 5, pp. 621–629, Oct. 1997.

Javier A. Muñoz (S’08) was born in Concepcion,Chile, in 1983. He received the Eng. degree in elec-tronic engineering (Hons.) and the M.Sc. degree inelectrical engineering from the University of Con-cepcion, Concepcion, in 2007 and 2008, respectively,where he is currently working pursuing the D.Sc. de-gree in electrical engineering in the area of digitalcontrol of multicell power converters.

José R. Espinoza (S’92–M’97) received the Eng. de-gree in electronic engineering and the M.Sc. degree inelectrical engineering from the University of Concep-cion, Concepcion, Chile, in 1989 and 1992, respec-tively, and the Ph.D. degree in electrical engineeringfrom Concordia University, Montreal, QC, Canada,in 1997.

Since 2006, he has been a Professor in the De-partment of Electrical Engineering, University ofConcepcion, where he is engaged in teaching andresearch in the areas of automatic control and power

electronics. He has authored and coauthored more than 100 refereed journaland conference papers and contributed to one chapter in the Power ElectronicsHandbook (New York: Academic, 2008). He is an Associate Editor of the IEEETRANSACTIONS ON INDUSTRIAL ELECTRONICS and IEEE TRANSACTIONS ON

POWER ELECTRONICS.

Luis A. Moran (S’79–M’81–SM’94–F’05) was bornin Concepcion, Chile. He received the electrical en-gineering degree from the University of Concepcion,Concepcion, in 1982 and the Ph.D. degree from Con-cordia University, Montreal, QC, Canada, in 1990.

Since 1990, he has been with the ElectricalEngineering Department, University of Concepcion,where he is a Professor. He has extensive consultingexperience in the mining industry, especially inthe application of medium-voltage ac drives, largepower cycloconverter drives for SAG mills, and

power-quality issues. His main research areas are in ac drives, power-quality,active power filters, flexible ac transmission systems, and power protectionsystems. He has written and published many papers on active power filtersand static VAR compensators in IEEE TRANSACTIONS. Dr. Moran was theAssociate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICSfrom 1997 to 2001.

Dr. Moran received the IEEE Outstanding Paper Award from the IndustrialElectronics Society in 1995 for the Best Paper published in the IEEE TRANS-ACTIONS ON INDUSTRIAL ELECTRONICS. In 1998, he received the Cityof Concepcion Medal of Honour for Achievement in Applied Research. Hewas recently appointed Distinguished Lecturer of the IEEE for the period 2008through 2009.

Carlos R. Baier (S’08) was born in Temuco, Chile,in 1979. He received the B.S. and M.Sc. degrees inelectrical engineering from the University of Concep-cion, Concepcion, Chile, in 2004 and 2006, respec-tively, where he is currently pursuing the Ph.D. de-gree in electrical engineering.

Since 2009, he has been a Professor in the De-partment of Industrial Technologies, Universityof Talca, Talca, Chile, where he is teaching in theareas of automatic control and power electronics.His research interests include improved control

techniques for multicell converters and the implementation of low-cost controlsystems for medium-voltage converters.