DESIGN GUIDE TDADP-SIL-USBC-65W-RD Description The TDADP-SIL-USBC-65W-RD reference design board describes a 65 W universal input offline power supply with programmable output voltage (5 V/3 A, 9 V/3 A, 15 V/3 A, 20 V/3.25 A). The power supply uses SZ1130 (Flyback PWM controller with integrated active clamp circuit) IC, Transphorm TP65H300G4LSG (650 V SuperGaN ® FET) and Weltrend WT6633P USB PD controller. This design shows the high-power density and efficiency that can be achieved due to the high level of integration of the SZ1130 controller. This document contains the power supply specification, schematic, bill-of-materials, transformer documentation, printed circuit layout, and performance data. Key Specs Schematics Input 90-265 Vac Output Voltages 5 V, 9 V, 15 V, 20 V Max Output Current 3.25 A Max Output Power 65 W Output Port USB-C PD Efficiency >94% Full Power Efficiency SZ1130 Features ▪ Integrated High Voltage Active Clamp FET, Active Clamp Driver, and Start-up Regulator ▪ Capable of Over 94% Efficiency ▪ Flat Efficiency Across Universal (90-265 VAC) Input Voltage and Load ▪ Tight Switching Frequency Regulation for Improved Input EMI Filter Utilization ▪ Up to 140 kHz Switching Frequency Operation ▪ OptiMode TM Cycle-by-Cycle Adaptive Digital Control ▪ Multi-Mode Operation (Burst Mode, Quasi- Resonant, Valley Mode Switching) ▪ Advanced Valley Mode Switching for low EMI ▪ Self-Tuning Valley Detection ▪ OTP, UVLO, OVLO, PCL, OPP and OSC Protections ▪ <50mW No Load Power Consumption of the IC ▪ Up to 65 W Output Power Applications ▪ High-Power-Density USB-PD AC/DC Power Supplies May 01, 2021 Silanna Semiconductor and Transphorm Page 1 tdadp-sil-usbc-65w-rd-ov1
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DESIGN GUIDE TDADP-SIL-USBC-65W-RD
Description The TDADP-SIL-USBC-65W-RD reference design board describes a 65 W universal input offline power supply with programmable output voltage (5 V/3 A, 9 V/3 A, 15 V/3 A, 20 V/3.25 A). The power supply uses SZ1130 (Flyback PWM controller with integrated active clamp circuit) IC, Transphorm TP65H300G4LSG (650 V SuperGaN® FET) and Weltrend WT6633P USB PD controller. This design shows the high-power density and efficiency that can be achieved due to the high level of integration of the SZ1130 controller.
This document contains the power supply specification, schematic, bill-of-materials, transformer documentation, printed circuit layout, and performance data.
Key Specs Schematics Input 90-265 VacOutput Voltages 5 V, 9 V, 15 V, 20 V Max Output Current 3.25 A Max Output Power 65 W Output Port USB-C PD Efficiency >94% Full Power Efficiency
SZ1130 Features Integrated High Voltage Active Clamp FET,
Active Clamp Driver, and Start-up Regulator Capable of Over 94% Efficiency Flat Efficiency Across Universal (90-265 VAC)
Input Voltage and Load Tight Switching Frequency Regulation for
Improved Input EMI Filter Utilization Up to 140 kHz Switching Frequency Operation OptiModeTM Cycle-by-Cycle Adaptive Digital
Control Multi-Mode Operation (Burst Mode, Quasi-
Resonant, Valley Mode Switching) Advanced Valley Mode Switching for low EMI Self-Tuning Valley Detection OTP, UVLO, OVLO, PCL, OPP and OSC
Protections <50mW No Load Power Consumption of the IC Up to 65 W Output Power
Applications High-Power-Density USB-PD AC/DC Power
Supplies
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Warning
Disclaimers:
1. Caution – High Voltage Operation: Lethal high voltages are present when this evaluation board ispowered from AC mains. Improper contact with high voltages could lead to electrical shock, burn and/orfire hazards, risking property damage, personal injury, and death.
2. Evaluation Purpose Only: This evaluation board is intended for evaluation purpose only and not forcommercial use. Care must be taken when testing the board, and an isolation transformer should beutilized.
3. Patents: The evaluation board design, along with circuits shown in this test report, may be covered byone or more U.S. and foreign existing/pending patents.
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Power Supply Specifications The evaluation board performance data presented in this report exceeds the power supply specifications listed in the following table.
Description Symbol Min. Typ. Max. Units Comments
Input Voltage Vin 90 115/230 265 VAC
2 Wire Input Frequency fline 47 60/50 63 Hz
Efficiency 5 V/3 A η5V/3.25A 90 %
@ 115 Vac, 25 °C ambient
9 V/3 A η9V/3.25A 93 %
15 V/3 A η15V/3.25A 93 %
20 V/3.25 A η20V/3.25A 93 % 4-Point Ave Efficiency
5 V ηave_5V 82.37 % CoC version 5 tier 2 4- point (25%, 50%, 75%,
100%) average efficiency @ 115Vac
9 V ηave_9V 87.60 %
15 V ηave_15V 88.99 %
20 V ηave_20V 89.16 % No-Load Input Power Pin 75 mW @ 230 Vac, 25 °C
Ambient Temperature TAMB 0 40 °C No airflow, sea level.
NOTE: The circuit board needs to be evaluated for additional tests, such as ESD and Line Surge to use the evaluation board design presented in this test report as a charger/adapter. Furthermore, the layout of the board needs to be adjusted according to the target shape and form factor of the end application.
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Board Pictures
Figure 1: Top Side of the EVB
Figure 2: Bottom Side of the EVB
Tushar Dhayagude
Tushar Dhayagude
Tushar Dhayagude
Tushar Dhayagude
Transphorm 240mOhmGaN Daughter Card
Tushar Dhayagude
Tushar Dhayagude
Silanna Active ClampFlyback IC SZ1130
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Schematic
Figure 3: 65W Schematic
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Circuit Description Input Protection The design incorporates a slow-acting input fuse (F1) as a form of protection in case of destructive failure of any of the downstream components. Furthermore, it has a varistor (RV1) connected between the line and neutral to absorb line surges and minimize the voltage overshoot seen by the downstream converter components. In addition, there is a footprint for an inrush current limiter (RT1) (negative temperature coefficient resistor) for applications which require attenuation of the inrush current.
EMI Filtering To meet the target EN55022 conducted EMI specification with sufficient margin with the least number of components and the highest power processing efficiency, the design utilizes an input filter consisting of an x-capacitor (C1) and a single common- mode choke (L1) as well as transformer (T1) construction for better EMI performance.
Fault Protections The evaluation board features Hiccup Mode Fault Protection using SZ1130-00. Under all applicable fault conditions, the device attempts to auto-restart. Table 1 below lists recovery behaviour under various fault conditions.
Table 1: SZ1130-00 Recovery Behavior
Fault Protection SZ1130
Input Under Voltage Lockout (UVLO)/ Brown-Out Auto-Recovery Input Over Voltage Lockout (OVLO) Auto-Recovery
Internal Over Temp Protection (OTP) Hiccup
External Over Temp Protection (OTP) Hiccup
Peak Current Limit (PCL) Hiccup
Over-Power Protection (OPP) Hiccup
Output Short Circuit (OSC) Hiccup
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PCB Layout PCB Prints
Figure 4: : Component side horizontal board, top
Figure 5: Solder side horizontal, bottom
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Figure 6: Component side vertical board, top
Figure 7: Solder side vertical board, middle 1 (left) and 2 (right)
Figure 8: Solder side vertical board, bottom
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Bill of Materials (BOM) Description Designator Manufacturer Manufacturer part number
USB JACK, C TYPE, POWER ONLY, 6 J1 CUI Devices UJC-HP-3-SMT-TR L2
PTNG 120V N-FET PQFN56 (4mohm) Q1 ON Semiconductor FDMS4D0N12C MOSFET N-CH 25V 124A 8PQFN Q4 ON Semiconductor FDMC2D8N025S DNI RES 1206, DNI RES 1206, , R1, R2
RES SMD 470 OHM 1% 1/10W 0603 R8, Yageo RC0603FR-07470RL
RES 0 OHM JUMPER 1/10W 0603 R9 Stackpole Electronics Inc RMCF0603ZT0R00 RES SMD 0 OHM 1/10W 0603 R10 Yageo RC0603JR-070RL
RES SMD 84.5K OHM 1% 1/10W 0603 R14 Yageo RC0603FR-0784K5L
RES SMD 10K OHM 1% 1/10W 0603 R23 Yageo RC0603FR-0710KL DNI R40
RES SMD 3.9K OHM 1% 1/10W 0603 R41 Yageo RC0603FR-073K9L
RES SMD 1.5K OHM 1% 1/10W 0603 R43 Bourns Inc. CR0603-FX-1501ELF
RES SMD 7.5K OHM 1% 1/10W 0603 R46 Yageo AC0603FR-077K5L
RES SMD 47 OHM 1% 1/10W 0603 R20, R36 Yageo RC0603FR-0747RL RES 0.005 OHM 1% 1W 1206 R25 Bourns Inc. CFN1206-FX-R005ELF
RES SMD 1K OHM 1% 1/10W 0603 R35 Yageo RC0603FR-071KL
RES SMD 1M OHM 1% 1/10W 0603 R37 Yageo RC0603FR-071ML
RES SMD 5.1K OHM 1% 1/10W 0603 R38 Yageo RC0603FR-075K1L
RES SMD 10K OHM 1% 1/10W 0603 R39 Yageo RC0603FR-0710KL
RES SMD 4.7K OHM 1% 1/10W 0603 R42 Yageo RC0603FR-074K7L
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Transformer Specification
Table 2: Transformer Material Lists
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Common-Mode Choke Specification
Table 3: Common-Mode Choke Material Lists
Material Specification Manufacturer Mfr. Part Number Core R12.5 × 7.90 × 6.35 mm dimension
(T38 -10000u) EPCOS/TDK or equivalent B64290L0742X038 or equivalent
AWG26 Magnet wire, dual insulation layer Various Separator PCB or Plastic
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Performance Data Electrical Data Efficiency DoE Level VI and CoC Version 5 Tier-2 4-point (25%, 50%, 75%, 100%) average efficiency, along with CoC Version 5 Tier-2 10% load efficiency requirements. Table 4: Load Efficiency Requirements
5 V/3.25 A 81.88% 81.84% 72.99% 9 V/3.25 A 86.87% 87.30% 77.60%
15 V/3.25 A 87.77% 88.85% 78.99%
20 V/3.25 A 87.54% 89.16. % 79.16%
The following efficiency data are averaged from 18 RD-19 65W boards. The boards are soaked for 5 minutes before measuring the efficiency with output measured after the USB-PD disconnect FET.
115 Vac 4-point average efficiency
VOUT / ILOAD_MAX = 5 V / 3 A %LOAD Efficiency (%) Average Efficiency (%)
100 91.66
89.98 75 91.42
50 90.38
25 86.47
10 83.64
VOUT / ILOAD_MAX = 9 V / 3 A %LOAD Efficiency (%) Average Efficiency (%)
100 93.52
92.24 75 93.24
50 92.49
25 89.70
10 83.52
VOUT / ILOAD_MAX = 15 V / 3 A %LOAD Efficiency (%) Average Efficiency (%)
100 93.84
93.36 75 93.90
50 93.66
25 92.05
10 86.42
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VOUT / ILOAD_MAX = 20 V / 3.25 A %LOAD Efficiency (%) Average Efficiency (%)
100 93.57
93.33 75 93.68
50 93.64
25 92.44
10 87.31
230 Vac 4-point average efficiency
VOUT / ILOAD_MAX = 5 V / 3 A %LOAD Efficiency (%) Average Efficiency (%)
100 89.013
86.34 75 88.00
50 85.20
25 83.15
10 80.82
VOUT / ILOAD_MAX = 9 V / 3 A %LOAD Efficiency (%) Average Efficiency (%)
100 92.45
89.74 75 91.24
50 90.10
25 85.17
10 81.33
VOUT / ILOAD_MAX = 15 V / 3 A %LOAD Efficiency (%) Average Efficiency (%)
100 93.93
92.30 75 93.46
50 92.14
25 89.65
10 83.55
VOUT / ILOAD_MAX = 20 V / 3.25 A %LOAD Efficiency (%) Average Efficiency (%)
100 94.33
93.05 75 94.07
50 93.26
25 90.52
10 84.20
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Full Load Efficiencies at 90Vac / 115Vac / 230Vac / 265Vac; 5V / 9V / 15V / 20V (measured after the USB-PD disconnect FET)
Vout = 5 V Vin Iout Efficiency (%)
90 Vac @ 50 Hz 3 A 91.46
115 Vac @ 60 Hz 3 A 91.66
230 Vac @ 50 Hz 3 A 89.01
265 Vac @ 50 Hz 3 A 88.27
Vout = 9 V Vin Iout Efficiency (%)
90 Vac @ 50 Hz 3 A 92.98
115 Vac @ 60 Hz 3 A 93.52
230 Vac @ 50 Hz 3 A 91.79
265 Vac @ 50 Hz 3 A 91.65
Vout = 15 V Vin Iout Efficiency (%)
90 Vac @ 50 Hz 3 A 93.10
115 Vac @ 60 Hz 3 A 93.84
230 Vac @ 50 Hz 3 A 93.94
265 Vac @ 50 Hz 3 A 93.52
Vout = 20 V Vin Iout Efficiency (%)
90 Vac @ 50 Hz 3.25 A 92.39
115 Vac @ 60 Hz 3.25 A 93.57
230 Vac @ 50 Hz 3.25 A 94.33
265 Vac @ 50 Hz 3.25 A 94.16
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Efficiency Graphs
The following graphs demonstrate 5 V/ 9 V/ 15 V/ 20 V efficiency results with output measured after the USB- PD disconnect FET.
Figure 9: Efficiency graphs for various output voltages and load currents
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Table 5 lists average no-load power consumption of 18 boards across the input voltages.
Table 5: No-load Power Consumption
Input Voltage (Vac) No-Load Power (mW) 115 57.6 230 66.1
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Key Waveforms The key waveforms for the worst case voltage conditions as seen by the primary side GaN Transistor and secondary side MOSFET are shown below. Due to the active clamp operation of SZ1130, there is practically no voltage spike at the switching node as shown in the following figures.
Vin=265 Vac, Vout=20 V, Iout=3.25 A Vds_pri (max) = 553V
Vds_sec (max) = 101.9V
Vin=265 Vac, Vout=20 V, Iout=0 A Vds_pri (max) = 539V
Vds_sec (max) = 115.7V
Figure 10: Voltage stress on the primary and secondary side MOSFET during worst case operating conditions
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Conducted EMI Scans The following conducted EMI measurements demonstrate more than 6 dB margin is maintained under all input (115 Vac/ 230 Vac) and output voltage (5 V/ 9 V/ 15 V/ 20 V) conditions with floating output.
Vin=115 Vac, Vout=5 V, Iout=3 A Vin=115 Vac, Vout=9 V, Iout=3 A
Vin=115 Vac, Vout=15 V, Iout=3 A Vin=115 Vac, Vout=20 V, Iout=3.25 A
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Vin=230 Vac, Vout=5 V, Iout=3 A Vin=230 Vac, Vout=9 V, Iout=3 A
Vin=230 Vac, Vout=15 V, Iout=3 A Vin=230 Vac, Vout=20 V, Iout=3.25 A
Figure 11: Conducted EMI test results under various operating conditions
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Output Voltage Ripple Noise The output voltage ripple was measured using a voltage probe with two capacitors (1 µF/50 V ceramic and 33 µF/50 V
low ESR electrolytic) tied in parallel across it. Measurement done at load side using an E-Mark USB cable.
Table 6: Output Voltage Ripple Summary
Input Voltage (Vac) Vout / Iout Measured Output Ripple (mVpk-pk)
Silanna Semiconductor Proprietary and Confidential Information furnished by Silanna Semiconductor is believed to be accurate and reliable. However, no responsibility is assumed for its use. Silanna Semiconductor makes no representation that the interconnection of its circuits as described herein will not infringe on existing patents rights.
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