Design Frameworkwith Freeware CADTools

A VLSI Design Framework with Freeware CAD Tools

Author

Teh, YK, Mohd-Yasin, F, Reaz, MBI, Kordesch, A

Published

2006

Conference Title

2006 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS,PROCEEDINGS

DOI

https://doi.org/10.1109/SMELEC.2006.380768

Copyright Statement

© 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collectiveworks for resale or redistribution to servers or lists, or to reuse any copyrighted component ofthis work in other works must be obtained from the IEEE.

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Griffith Research Online

https://research-repository.griffith.edu.au

ICSE2006 Proc. 2006, Kuala Lumpur, Malaysia

A VLSI Design Framework with Freeware CAD Tools

Y. K. Teh1, Student Member, IEEE, F. Mohd-Yasin1, Member, IEEE, M. B. I. Reaz2, Member, IEEE,A. Kordesch3, Senior Member, IEEE

'Faculty of Engineering, Multimedia University, 63100 Cyberjaya, Selangor, MALAYSIA2ECE Dept, IIUM, 53100 Kuala Lumpur, MALAYSIA

3Device Modeling Group, Silterra Sdn. Bhd., Kulim, Kedah, MALAYSIAE-mail: yktehgmmu.edu.my

Abstract - This work presents a PC-basedfreeware CAD environment to design andtape out VLSI microelectronic circuits,starting from schematic capture all the way toa foundry compatible GDS II database. Thesefree tools will help more Malaysianuniversities to set up low cost VLSI CADlaboratories and tape out circuits usingSilterra's University Program. This will helpgrow local IC design culture and skills.FreeVLSI uses common freeware CAD tools:5SPICE, LASI, and WinSPICE, and somecustom scripts to interface between these tools.Currently FreeVLSI is able to cater to fullcustom design flow from schematic capture tocircuit layout.

skills. FreeVLSI is currently capable ofaccommodating full custom ASIC design flow.

Three different types of circuits (MOSFET I-V characterizations, digital and analog) havebeen simulated using FreeVLSI and commercialtools. Comparisons have been made with theactual silicon data. Silterra 0.1 8pm CMOSSPICE models were used in all simulations.

II. DESCRIPTION OF FRAMEWORKPROPOSED

Figure 1proposed todesign flow:

shows the freeware componentsaccomplish FreeVLSI Full Custom

I. INTRODUCTION

Electronics manufacturing is one of the mostimportant industries in Malaysia. Recently, cheaplabor from other countries has promptedMalaysia to try to move up the value chain tochip design, following the Taiwan model. It iscrucial to develop manpower with the IC designskills early at universities undergraduate level toachieve the objective.

In Malaysia, Silterra has offered a universityprogram that allows university researchers tofabricate their designs at no cost, similar to [1]and [2]. The chips are designed and simulatedusing costly commercial design tools. Weattempt one step further, by designing free toolsto design chips employing Silterra technology.

The purpose of this work is to present a PC-based freeware CAD environment (calledFreeVLSI) to design and tape out VLSImicroelectronic circuits, starting from schematiccapture finally producing a foundry compatibleGDS II database. These free CAD tools will helpMalaysian universities to set up low cost designlaboratories to grow local IC design culture and

|S;p e C ific atio r'

S che maticCCapture

CE Simu;lII_Not OkE L. i lr 4L1PIC .:

Not Ok

DRC, LVS check(I ..12

c,_

MaIanual ParasiticEstim ation

S PICE simulation withe stimated p arasiticAT T T-__ _ T -_-__-_.M5s {fLfi iA;iJ F 1 H11%ot Ok

L OK

TareCut

Figure 1: Full Custom Design Flow of FreeVLSI

0-7803-9731-2/06/$20.00 ©2006 IEEE 896


* Schematic Capture

Schematic capture software is used toconstruct circuit schematics and generate SPICEsimulation net lists. Two good candidates foundare 5SPICE [3] and LTSPICE [4].

Alternatively LASI which is proposed aslayout editing tool could also be used to performschematic capture and net list extraction.Nevertheless device models in extracted net listshave to be altered in order to match the devicename given in foundry library. This could bedone by manual editing or utilizing computerscripts.

parasitic BJT devices such as bandgap referencecircuits. WINSPICE can perform both electricalsimulation and graphical post processing throughprogramming scripts.

Figure 3: WinSPICE nutmeg and plot snapshot

* Layout Editing

Figure 2: Snapshot of 5SPICE

SPICE Simulation

BSIM3 is popular CMOS MOSFET devicemodel developed by the BSIM Research Group[5] of the University of California, Berkeley. Thethird iteration of BSIM3, BSIM3 Version 3(commonly abbreviated as BSIM3v3) has sincebeen widely used by most semiconductorfoundries and IC design houses world wide fordevice modeling and CMOS IC design.

In this framework, the target is to findfreeware alternatives that are capable ofsimulating commercial BSIM3v3 device modellibraries provided by the foundry. A goodcandidate discovered after testing many freewaresolutions available is WINSPICE [6].WINSPICE is a port of Berkeley's originalSpice3F4 to Microsoft Windows operatingsystem. WINSPICE is capable of taking HSPICEBSIM3V3 compatible MOSFET device modelsand also BJT (Gummel and Poon model) afterapplying software patch upgrades provided bythe author. Users can use WINSPICE to simulatecircuits with a mixture of MOSFET and CMOS

Windows LASI [7] (Windows LAyoutSystem for Individuals) is recommended toperform custom layout editing, Design RuleCheck (DRC), macro extraction, Electrical RuleCheck (ERC), Layout Versus Schematic (LVS),as well as final data codification (conversion toGerber GDS II format for foundry fabrication).LASI was written by Dr. David Boyce. LASIruns on the Microsoft Windows system.

Default set up files for LASI have beenmodified to match GDS layer definitions of thetargeted foundry. It is worth noting that LASI isonly capable of doing simple DRC check andparasitic extraction is still in development assophisticated LASI compatible deck files need tobe rewritten. In the current development ofFreeVLSI, designers have to manually estimateand compute parasitic capacitance based oncircuit layout and foundry electrical design rules.

897


III. DESIGN EXAMPLES

Three different types of circuits have beensimulated using FreeVLSI and commercial toolsfor comparison. Silterra 0.1 8pm CMOStechnology is used in all simulations. Examplecircuits include MOSFET I-V characterization,Bandgap reference circuit (analog circuit) withactual silicon data, and TSPC D flip flop (digitalcircuit).

* MOS I-V characterization

Both NMOS and PMOS types of transistorsavailable in Silterra's 0.18ptm process arecharacterized using HSPICE, Eldo andWinSPICE. Saturation current of PMOS andNMOS of different W/L ratio is extracted. Datafrom three SPICE simulators are plotted inFigures 5 and 6.

ctue8.E-03

6.E-03

4.E-03

2.E-03

O.E+OO -

NVDOS Saturation CQrertvs PdyCGite Size

Three simulators give close results for smallfeature size devices (Poly gate width less than2um). Results are summarized below.

Eldo HSPICE3.34%0 0.88%

l 2.07% 5.91%0Figure 7: Average difference in simulation results

of I-V characterization for Eldo andHSPICE compared to WinSPICE withvariable W, Fixed L = 0.18pim

A. Analog Circuit - Bandgap VoltageReference

Figure 8 shows an analog circuit example,which is a low power current mode bandgapreference circuit derived from H.Banba's paper[8]. DC, AC and transient analyses are simulatedon two simulators: Mentor Graphics Eldo andWINSPICE. The design has been fabricatedusing Silterra's 0.18um process and DC resultsare confirmed with actual silicon IVmeasurement using an HP4 1 56B parameteranalyzer. Simulation results obtained from bothsimulators are compared with actual siliconmeasurement data.

4- VMnSPICE- Bdo- HSPICE

0 2 4 6Feature Size (um)

VreI

8 10

Figure 5: NMOS IDsat vs Poly gate size

Feature Size (um)

Figure 6: PMOS IDsat vs Poly gate size

Figure 8: Bandgap reference circuit investigated

DC sweep simulation result shows less than1% difference between commercial simulator(Eldo) and WinSPICE. Both simulators yieldedgood match against actual silicon results for bothoutput voltage and current consumption as

shown in Figure 9 and Figure 10.

898

PIVD0SSaturaton Cunret vs Pdy Gate SizeCunirt

3. E-03

3. E-03

2.E-03

2.E-03

1.E-03 -WnSPICE

5.E-04 HSPICE

0.E+000 2 4 6 8 10


Barxkap Oupt VoltageTransient response is simulated and plotted in

Figure 12. WinSPICE simulation shows somediscrepancy at initial transient but overall theresponse tracks Eldo's output well after outputvoltage stabilizes.

lBdoVref

mI WnSPICE0.9

-J S\Ibasured 0.8

0.7l

0 1 2 3 4 0.60.5

Figure 9: Vref of Bandgap vs VDD 0.40.30.2

Baringap currert consmnpton 0.1 I

(.n; ,51 ,%10.0 -i-

O.E-H

Bandgap Transient response ElbdoWVMnSRCE

Time

00 1i.E-05 2.E-05 3.E-05 4.E-05 5.E-05

Figure 12: Transient response of Bandgap Vref

B. Digital Circuit- D Flip Flop

-A Bdo Behaviour of digital circuit simulation under-V\nSPICE

FreeVLSI is investigated as well. A TSPC (True

) 1 2 3 4 Single Phase Clock) D flip flop circuit issimulated using both Eldo and WinSPICE.

Figure 10: IDD ofBandgap vs VDD

AC analysis, which is a common analysisperformed by designers is also compared. Againboth simulators give nearly identical results as

shown in Figure 11 (a),(b).

V| fdbBBa d g Ap Vrof A C A na I (ssM Ag1

Wet (db)>..QjjXX . II1.1IIL.L1

lrEDI13i:tAE 01 XUi40Im i0Ewi 1 A 4

Freq=

Deg VfACA (Phse)200

160-

120

80

40

n

.Ij

Elcdo-WrSISRCE

Figure 13: TSPC D Flip Flop circuit

With the same stimulus fed to CLK and Dinput of D flip flop, Q output of D flip flop isforced to switch at 250MHz. Transient response

of Q output from both simulators is plotted on

Figure 14. It can be seen that simulation resultsyielded from Eldo and WinSPICE actually tracksclosely; except the initial transient. Timingdifference demonstrated by both simulatorsshows less than lps difference.

IN"1, Freq1OI

1.0E+00 1.OE02 1.0E+04 1.0E+06 1.0E+08

Figure 11 (a), (b): AC response of Bandgap Vref

899

Vref0.60

0.40

0.20

0.00

IDD4.E I

3.E-06

2.E-06

1 =_:--

-~~~~~~~~~~~~-------

u

us

tz-cJb


D-FF Switching OUtput end PCs. This allows more local universities toventure into the world of VLSI design. It ishoped that with the introduction of thisframework, more local engineers with VLSIdesign experience could flourish.

-EBdo-WnSPICE

[2][2]

I; ; v Time

0 2E-09 4E-09 6E-09 8E-09 1 E-08

Figure 14: Transient response ofD-FF Q output

WinSPICE has better match in digital circuitscompared to analog circuits due to the saturationnature of MOS in digital operation; whereasanalog circuits often operate in the sub-thresholdregime, both simulators do not track analog as

close as digital circuits.

[3][4][5]

[6][7][8]

REFERENCES

http://www.mosis.orghttp://www.europractice.imec.be/europractice/europractice.htmlhttp://www.5spice.comhttp://www.linear.com/company/software.jsphttp:Hwwwdevice.eecs.berkeley.edu/-bsim3/intro.htmlhttp://www.winspice.comhttp://members.aol.com/lasicad/Banba, H. Shiga, T.Miyaba, T.Tanzawa,S.Atsumi, and K.Sakui, "A CMOS BandgapReference Circuit with Sub-1-V Operation",IEEE Journal of Solid State Circuits, Vol 34-5,pp 670-674, May 1999.

IV. DISCUSSION

FreeVLSI has shown comparable performancewith commercial products in SPICE simulationin terms of DC, AC and transient analysis. It issuperior judging from cost factor. However,unlike commercial CAD software, FreeVLSIdoes not have good integrity to interface betweendesign tools. It also lacks a user friendlygraphical interface. For users to maneuver

smoothly within FreeVLSI framework, some

knowledge of computer script is necessary inorder to convert and transfer output betweendifferent tools.

FreeVLSI also suffers from the simple DRCchecking tool. For comprehensive layout, LASIoften overlooks DRC errors and has slow loadingspeed. The next work will look at this issueclosely.

V. CONCLUSION

In conclusion, these results prove thatFreeVLSI can be used as an alternative over

commercial CAD tools for simple mixed signalcustom circuits, with good matching to actualsilicon results. The final design is foundrycompatible and can be fabricated using Silterra'sUniversity Cooperation program.

The advantage of this framework is its zero

cost. In fact FreeVLSI can be installed on low

900

Voltage

2 1

Design Frameworkwith Freeware CADTools

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