Design for Verification in System-level Models and RTL Anmol Mathur Venkat Krishnaswamy Calypto Design Systems, Inc Outline • What is a system-level model? • Verification Methodology from SLM to RTL • Sources of inconsistency between SLM and RTL • Recommendations for keeping SLM and RTL consistent • Conclusions Market Trends: ESL Drivers System Level Design Economics • Development Cost • Time to Revenue • Respin reduction Productivity • Design reuse • Platform design • Optimization Optimization • Performance • Power / battery life • Design updates Complexity • Increasing design size • HW / SW co-design • Verification testbench Leveraging system-level models for RTL verification can reduce the RTL verification bottleneck Levels of Systems IP Software Hardware SOC Block verification Boundary assertion verification Hardware/software Interface verification Uses of System-level Models • Higher level of abstraction resulting in faster simulation turnaround time • Performing architectural tradeoffs and performance validation • Platform for software development Outline • What is a system-level model? • Verification Methodology from SLM to RTL • Sources of inconsistency between SLM and RTL • Recommendations for keeping SLM and RTL consistent • Conclusions Functional Verification Landscape System level RTL level Gate level RTL-gate Equivalence Checking •Simulation/emulation based verification •Assertion based verification Simulation RTL-SL co-simulation
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Design for Verification in System-level Models and RTLb93058/graduate_project/MFASE/Design for... · • HW / SW co-design • Verification testbench Leveraging system-level models
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Design for Verification in System-level Models and RTL
Anmol Mathur
Venkat Krishnaswamy
Calypto Design Systems, Inc
Outline
• What is a system-level model?
• Verification Methodology from SLM to RTL
• Sources of inconsistency between SLM and RTL
• Recommendations for keeping SLM and RTL consistent
• Conclusions
Market Trends:ESL Drivers
System Level Design
Economics• Development Cost
• Time to Revenue
• Respin reduction
Productivity• Design reuse
• Platform design
• Optimization
Optimization• Performance
• Power / battery life
• Design updates
Complexity• Increasing design size
• HW / SW co-design
• Verification testbench
Leveraging system-level models for RTL verification can reduce theRTL verification bottleneck
Levels of Systems
IP
Software
Hardware
SOC
Block verification
Boundary assertion
verification
Hardware/software
Interface verification
Uses of System-level Models
• Higher level of abstraction resulting in faster simulation
turnaround time
• Performing architectural tradeoffs and performance validation
• Platform for software development
Outline
• What is a system-level model?
• Verification Methodology from SLM to RTL
• Sources of inconsistency between SLM and RTL
• Recommendations for keeping SLM and RTL consistent
• Conclusions
Functional Verification Landscape
System level
RTL level
Gate level
RTL-gate Equivalence Checking
•Simulation/emulation based
verification
•Assertion based verification
Simulation
RTL-SL co-simulation
Co-simulation Based SLM to RTL Verification
In_B Out_D4[3] 5[2]
In_A Out_C1 2
foo.c
readData writeData
12
1
10]
2
In_B[11:0] Out_D[9:0]12 10
In_A Out_C[1:0]1 2
foo.v
In_lz Out_lz
Input
Data
Compare Outputs
spec_wrapper
impl_wrapper
• Input transactors to match differences in input protocols
• Output comparison needs to account for timing difference in when corresponding outputs are generated
What is SEC?
• Equivalence check designs with temporal interface differences
• Equivalence check designs with internal state differences
• Effective for eliminating bugs and ensuring consistency without testbenches