Design for Reliability for System-in-Package...Transmitter Receiver Module (TRM): an Avionics Application Lifetime Prediction Solder 90Pb10Sn Model Low Melting Point Solder 63Sn37Pb

Copyright Confidential

Design for Reliability forSystem-in-Package

Stoyan Stoyanov*, Chris Bailey*, Nadia Strusevich* and Jean-Marc Yannou**

*University of Greenwich, London, UK **NXP, Caen, France


Content• Motivation• SiP and Wafer Level Packaging• Technology Challenges• Fan-Out Design Concept• Lifetime Assessment for solder crack in a

MMIC Device (Avionics Applications)• Virtual Prototyping and Design-for-

Reliability• Conclusions


Motivation + Objectives

• Design for Reliability modelling for SiP– Thermal +

Thermo-mechanical – Reliability Prediction aid for

SiP structures– Reduced Order Models

• Optimisation Techniques– Design parameters,

materials, etc– Include data uncertainties





System-in-Package


What is SiP• SiP (ITRS)

“Any combination of semiconductors plus optionally other components such as passives, MEMS, and optical components assembled into a single package”

• Wafer-Level Chip Scale PackagingIntegrated Circuit Package with most process steps shifted at the wafer-level in the wafer foundry (as opposed to IC-level packaging) offering direct IC-to-PCB connections

• WL-SiP (NXP)


Why SiP• Size Reduction• Complexity Reduction• Design Effort Reduction • Power Reduction • Lower System Cost

Moo

re’s

Law

: M

inia

turiz

atio

n

Bas

elin

e C

MO

S: C

PU, M

emor

y, L

ogic

130nm

90nm

65nm

45nm

32nm

22nm

More than Moore: Diversification

Analog/RF Passives HV Power SensorsActuators Biochips

InformationProcessing

Digital contentSystem-on-Chip

(SoC)

Interacting with people and environment

Non-digital content (SiP)Combining SoC and SiP: Higher Value Systems

More than Moore





System-in-Package


WL-SiP Reliability Challenges

• WLP modules are generally larger for SiP than for Single IC’s– Thermal miss-match – Board Level solder joint Reliability main concern– BLR of WLP worsens with larger dies

• WLP modules to be assembled lead-free– Compliance to RoHS– No lead in the wafer-fab


Need for Co-Design in SiP

10Copyright Confidential

Integrated Analysis in Design• Integration taking place

– Electronic Design Automation (EDA)tools now addressing Packaging

– IC, RF, PCB Designs– Integrated Analysis Tools

Functional

Thermo-Mechanical

EMC

Source: Flomerics Limited

http://www.ansys.com/default.asp


Content

• Motivation• SiP and Wafer Level Packaging• Technology Challenges• Fan-Out Design Concept• Lifetime Assessment for solder crack in a MMIC

Device (Avionics Applications)• Virtual Prototyping and Design-for-Reliability• Conclusions

System-in-Package


Fan-out (Embedded) Concept• A new SiP-friendly package platform processed at the

wafer level with built-in substrate routing

mold


Fan-out versus Fan-in WLCSP• Fan-in WLCSP

– Is miniature and low cost (Wafer-Scale Packaging)

– Reliable up to 15mm²

– Package cost impacted by wafer yield

– Pad limitation– Poor acceptance (bare

Si) by some customers

• Fan-out WLCSP– Is miniature and low cost

(Wafer-Scale Packaging)– Expected high reliability even for large

packages– Package cost only spent on

known good dice – No pad limitation– Good customer acceptance (molded lid)– Excellent substrate isolation in between

components– High Q low-cost inductors– Is highly SiP compatible (2D & 3D)

IC Inductor in RDL


Analysis of an Fan-out SIP structure• Thermo-Mechanical

Modelling (Thermal Cycling)• Simulation technology used to

assess the effect of– Mold thickness– Fan-out ratio– Mold material

Redistributionlayer (RDL)

IC1 IC2

PCB

Redistributionlayer (RDL)

IC1 IC2

PCB

IC3

Computer Model: 1/8 section ofan Embedded Die SiP (Fan-Out Package)

Active Die

Passive Die Mold CompoundUnderfill


Fixed Chip Thickness

80μm

Mold Thickness 20μm



Mold

Effect of Mold Compound Thickness (1)

Chip

Mold Compound Properties:CTE: α1=10ppm/ºC, α2=45ppm/ºC

(Tg=130ºC)Young Modulus = 20.E+9PaPoisson’s Ratio = 0.35

Embedded Die SiP without Underfill


Effect of Mold Compound Thickness (2)

0

20

40

60

80

100

0 50 100 150 200 250 300 350

Mold Thickness (um)

Effe

ctiv

e St

ress

(MPa

)

0

20000

40000

60000

80000

100000

120000

0 100 200 300 400

Mold Thickness (um)

Sold

er D

amag

e (P

a)

Solder Damage changes by 40% in the mold thickness range

Lower Mold Compound Thickness improves reliability

Die Stress changes by 70% in the mold thickness range

Solder Joint Reliability Metric:Accumulated creep energy in solder per thermal cycle

Die Reliability Metric:Maximum effective stress during thermal cycling


Mold Chip

Effect of Fan-out Ratio (1)

Total Area is fixed:5700x5700μm2

2000μm

850μm

1400μm1130μm

1450μm 1720μm

Fan-out Ratio =Total Area : Chip Area

Ratio 2 Ratio 4 Ratio 6

Chip

Chip

Chip

Mold Mold Mold

Mold Compound

Chip

Embedded Die SiP without Underfill


0

200000

400000

600000

800000

1000000


Sold

er D

amag

e (P

a) Solder Damage for Fan-Out Ratio 2 is 20 times higher than for the package with Ratio 6

0

20

40

60

80

100

Ratio2 Ratio4 Ratio6

Effe

ctiv

e St

ress

(MPa

)

Stress in the Chip for Fan-Out Ratio 2 is higher by 90% than in the package with Ratio 6

Higher Fan-out Ratio improves reliability

Effect of Fan-out Ratio (2)


Chip

Chip

Chip

Mold Mold Mold


Mold Compounds Material Properties

Material CTE (ppm/oC) Young

Modulus (Pa)

Poisson’s Ratio

Mold Compound 1

1 0

2

58, 45 C

137 gTαα

=⎧=⎨ =⎩

1.91E+9 0.35

Mold Compound 2

1 0

2

10, 130 C

45 gTαα

=⎧=⎨ =⎩

20.0E+9 0.35

Mold Compound 3

1 0

2

7, 165 C

30 gTαα

=⎧=⎨ =⎩

25.0E+9 0.3

Effect of Mold Material (1)

• Three options for mold selection considered

Mold


Effect of Mold Material (2)

0

400000

800000

1200000

1600000

2000000

Mold 1 Mold 2 Mold 3

Sold

er D

amag

e (P

a)

0

10

20

30

40

50

60

Mold 1 Mold 2 Mold 3

Effe

ctiv

e St

ress

(MPa

)

Best mold with respect solder joint reliability is Mold 2

Solder Joint Reliability Metric:Accumulated creep energy in solder per thermal cycle

Die Reliability Metric:Maximum effective stress during thermal cycling


Content

• Motivation• SiP and Wafer Level Packaging• Technology Challenges• Fan-Out Design Concept• Lifetime Assessment for solder crack in a MMIC

Device (Avionics Applications)• Virtual Prototyping and Design-for-Reliability• Conclusions

System-in-Package


• Uses data from FEA: Predicts damage in solder• Lifetime model: Predicts crack growth rate (Ri)• Cycles Prior to Crack Initiation Are Ignored• Total Crack Length =

• Failure Criteria: A joint fails if the crack extends beyond half the diameter of the joint at the interface

Transmitter Receiver Module (TRM): an Avionics Application

Lifetime Prediction ModelSolder 90Pb10Sn

Low Melting Point Solder 63Sn37Pb

Path of Crack Propagation

Crack. ii

i

N R∑( Ni - number of thermal cycles for cycle number i)

ASIC (Application Specific Integrated Circuit) MMIC (Millimetre Microwave

Integrated Circuit)


Thermal Cycles under Investigations

18

17

16

15

14

13

12

11

10

9

8

7

6

-

5

5

4

3

2

1

Temp.Cycle No.

6009040054N/A70N/AYesGround Running 2 x hot18

10509070045N/A35N/A17b

105090700N/A10N/A5YesGround Running 7x normal

17a

30090200N/A-26N/A-31YesGround Running 1x cold16

N/A14401750N/AN/A7133NoNon-Flight Days hot15

N/A14406125N/AN/A255NoNon-Flight Days normal14

N/A1440875N/AN/A-22-33NoNon-Flight Days cold13

N/A60325152515YesMaintenance ATP (LRI)12

N/A30225152515YesMaintenance ATP (SRI)11

1200908001570N/AYesFlight 2 x hot10

21009014001535N/A9b

210090140015N/A5YesFlight 7x normal

9a

6009040015N/A-31YesFlight 1x cold8

No TestStorage7

N/A60325152515YesProduction ATP ( LRI)6

N/A30225152515YesProduction ATP (SRI)5

N/A901530-1960-19YesProduction LRI-PAT4

N/A901054-2670-40YesProduction LRI-ESS 3

N/A151054-2690-40NoProduction SRI-ESS (passive)2

No TestProduction PCA-ESS (passive)1

MaxMinMaxMin

Total No of Hours

Life

Duration of Single

Event (mins)

No of Cycles

Inlet Air Temperature

(°C)

Ambient Air Temperature

(°C)Equipment OperatingDescription

TypeCycle

#

18

17

16

15

14

13

12

11

10

9

8

7

6

-

5

5

4

3

2

1

Temp.Cycle No.

6009040054N/A70N/AYesGround Running 2 x hot18

10509070045N/A35N/A17b

105090700N/A10N/A5YesGround Running 7x normal

17a

30090200N/A-26N/A-31YesGround Running 1x cold16

N/A14401750N/AN/A7133NoNon-Flight Days hot15

N/A14406125N/AN/A255NoNon-Flight Days normal14

N/A1440875N/AN/A-22-33NoNon-Flight Days cold13

N/A60325152515YesMaintenance ATP (LRI)12

N/A30225152515YesMaintenance ATP (SRI)11

1200908001570N/AYesFlight 2 x hot10

21009014001535N/A9b

210090140015N/A5YesFlight 7x normal

9a

6009040015N/A-31YesFlight 1x cold8

No TestStorage7

N/A60325152515YesProduction ATP ( LRI)6

N/A30225152515YesProduction ATP (SRI)5

N/A901530-1960-19YesProduction LRI-PAT4

N/A901054-2670-40YesProduction LRI-ESS 3

N/A151054-2690-40NoProduction SRI-ESS (passive)2

No TestProduction PCA-ESS (passive)1

MaxMinMaxMin

Total No of Hours

Life

Duration of Single

Event (mins)

No of Cycles

Inlet Air Temperature

(°C)

Ambient Air Temperature

(°C)Equipment OperatingDescription

TypeCycle

#


0.0E+00

5.0E-08

1.0E-07

1.5E-07

2.0E-07

2.5E-07

Flight1

xCold

Flight7

xNor

mal(a)

Flight7

xNor

mal(b)

Flight2

xHot

Non-Fligh

t Day

s Norm

alNon-Fl

ight D

ays H

ot

Groun

dRun7_N

ormal(

b)

R, C

rack

Gro

wth

Rat

e (u

m/c

ycle

)Simulation of Crack Growth Rate [μm] for

Various Field Cycles (Life Time Spec)

Path of Crack Propagation

Modelling Predictions for the worst case of the module without underfill


Total Crack Length Calculation

Total Crack Length under the expected field cycles exceeds the critical failure limit, i.e. with no underfill the package will not survive the required life

Cycle Crack Length after required cycles (μm)

Flight 1 x Cold 92

Flight 7 x Normal (a) 25.2

Flight 7 x Normal (b) 16.9

Flight 2 x Hot 128

Non-Flight days Normal 144

Non-Flight days Hot 77.9

Ground Running 7 x Normal 8.5

For Total Covered Cycles 494

Radius = 230 μm

Crack length Propagation


Achieving Required Reliability

No Underfill Underfill A

Damage in solder decreases

• Underfill will enhance reliability • Different underfills simulated• With certain underfills the required reliability can be achieved

Underfill B Underfill C Underfill D





System-in-Package


Integrated Numerical Analysis Framework

Forecast Uncertainty,Process/Product

Capability

Reduced OrderModel Generation

Design of Experiment

High Fidelity Model

Risk Analysis

Optimisation

Sensitivity AnalysisKey process/product

parameters

Process/Product parameters

Decision: alternatives Decision: Optimal Design

Reduced Order Modelling + Sensitivity Analysis

Uncertainty Analysis

Design Data Uncertainty


Fan-in stacked die SiP Structure


Finite Element Model• Finite Element Model of SiP

– One-eight section of the package due to symmetry– Underfill applied

• Material Properties– Inelastic creep behaviour for solder– Temperature dependent ⎟⎟

⎠

⎞⎜⎜⎝

⎛−=

TRQA n

effcrij exp))((sinh σαε&


Design Variables1. PCB thickness (HPCB)2. Board level solder joints

stand-off-height (SOH)3. Passive die thickness

(HDIE)


Damage Parameters• Two SiP responses under accelerated thermal cycling

have been observed1) Maximum warpage of the package Dw2) Mean fatigue life of solder joints Nf

Warpage at 125C Solder Joints Damage

bf aWpN )(=Life-time model


Design Steps Flow1. Identify experimental design

points2. Obtain responses (lifetime,

warpage) at each design point• Undertake finite element analysis at

each design point. 3. Construct Response Surface

Approximation

4. Include formulations to account for

– Parameter uncertainties– Reliability requirements– Robust design requirements

Design of Experiments

FEA at experimental points

Response Surface Modelling (ROM)

Sensitivity Analysis

Design Task as Optimisation Problem / Design Solution

Uncertainties

Reliability Robustness


Step 1: Design of Experiments• Central Composite

Design (CCD)• 15 Design points• FEA Responses for

• Cycles to failure (Nf)• Warpage of SiP (Dw)

Factorial Point

Axial Point

Central Point


Step 2: Response Surface Modelling• Response Surface Models

represent response data: – Warpage of SiP– Lifetime of solder joints

• Fast design evaluations for SiP

• Accuracy using statistical tools– ANOVA– Efficiency measures– E.g. coefficient of multiple

determination for both models is 99.9%


Design Task• A SiP design is defined as reliable if it satisfies

the constraints in the design task• Task formulated as

optimisation problemWarpage

Life-time

SiP thickness


(a) Deterministic Optimal Design• Design task solved using numerical

optimisation techniques• Optimal design

– Warpage reduced by 22 %– Lifetime Satisfied

Deterministic Formulation


(b) Effect of Uncertainties• Design variables have

uncertainties– Will impact system responses– Reliability requirements may be

violated due to uncertainty of the inputs

• Probability of Failure– the n-sigma design approach is

needed

• SiP design variables modelled with Gaussian distribution

• Standard deviations:a) HPCB: σHPCB = 16 um;b) SOH: σSOH = 2 um;c) HDIE: σHDIE = 2.5 um;

Deterministic Optimal design

Probabilistic Optimal design

Critical Response 1

Critical Response 2

Design Variable A

Des

ign

Varia

ble

B


Effect of UncertaintiesDesign for Reliability

• Constraints re-defined in terms of probability of failure

• Monte Carlo simulations– Evaluation of the distribution of

the response values

Probabilistic Formulation

0

200

400

600

800

2640 2660 2680 2700 2720 2740 2760 2780 2800 2820

Fatigue Life (cycles) Uncertanty at Reliable Optimum

Freq

uenc

y

95 % of designs have required life-time


0

200

400

600

800

2340 2360 2380 2400 2420 2440 2460 2480 2500 2520

Fatigue Life (cycles) Uncertanty at Robust Optimum

Freq

uenc

y

Effect of UncertaintiesDesign for Robustness

• Design for Robustness – design that has minimum

uncertainty (variation) of its responses

• Focus is on life-time

Probabilistic Formulation

± 1σ

σ=14 cycles





System-in-Package


Conclusions + Acknowledgments• Lots of interest in SiP and Wafer

Level SiP

• Design-for-Reliability for SiP is a key requirement

– No clear integration between IC and Packaging

– Design of Experiments to understand complex interactions

– Optimisation is deterministic

– No account of data uncertainties

– Reduced Order Models required

– Include data, design and process uncertainties

High Fidelity Modelling

OPTIMISATIONENGINE

Sensitivity Analysis Design Optimisation

Response Surface Analysis

Reduced Order Modelling

Design of Experiments

Uncertainty Analysis

Design for Reliability for System-in-Package...Transmitter Receiver Module (TRM): an Avionics Application Lifetime Prediction Solder 90Pb10Sn Model Low Melting Point Solder 63Sn37Pb

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