Design-for-Debug Architecture for Distributed Embedded Logic Analysis

Department of Computer Science and Engineering

Ho Fai Ko, Member, IEEE, Adam B. Kinsman, Student Member, IEEE, and Nicola Nicolici, Member, IEEE

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Volume: PP Issue:99 2010

Reporter : Chien-Hung Chen

Design-for-Debug Architecture for Distributed Embedded Logic Analysis

Abstract(1/2)

In multi-core designs, distributed embedded logic analyzers with multiple trigger units and trace buffers with real-time offload capability through high-speed trace ports can be placed on-chip. This brings new challenges on how to connect the debug units together in such way that the limited storage space in the trace buffers can be used efficiently. This problem is further aggravated when shadow registers are used to capture data for some signals in the design.

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Abstract(2/2)

In this paper, we propose a new architecture that can dynamically allocate the trace buffers at runtime based on the needs for debug data acquisition coming from multiple data sources and user-programmable priorities. Experimental results show that using the proposed architecture, real-time observability can be improved using only a small amount of on-chip logic hardware, while avoiding excessive storage on-chip.

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What’s the problem?

How to distributed Embedded Logic Analysis in multi-core SoC?

How to connect the debug units together as trigger units and trace buffer…?

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The purpose of this paper

A novel debug methodology for improving the real-time observability of multi-core SoC.

Design-for-debug architecture based on distributed embedded logic analysis.

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Related Work

State-of-the-art design-for-debug architecture for trace buffer-based debug

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[20][21]-[26]

[29][31]

[30][32]

[11]

Assumption 1: Growth in the number of cores

Assumption 2: Adoption of high-speed trace ports

Under two assumptions that the following scenarios are considered 1. When there are multiple trigger events

occurring simultaneously, how to choose trace buffers to sample data from different data sources?

2. When some of the trace buffers are already occupied, is it necessary to reallocate the trace buffers when a new trigger event from a different data source occurs?

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3. How to allocate trace buffers when the number of sample requests is more than the number of available trace buffers?

4. How to allocate trace buffers for data sampling before knowing when trigger events from multiple data sources will happen?

5. How to decide which trace buffers to offload first when multiple trace buffers are idle?

6. How to balance the sampled data among trace buffers such that more trace buffers will have available space for fulfilling upcoming data acquisition requests?

7. In the case when debug experiments are repeatable, can the controller be reprogrammed to acquire different sets of debug data during each rerun of the experiment?

8. When all or some of the state elements are shadowed, how to offload data from these shadow registers without using dedicated scan pins?

To address the scenarios presented debug architecture with 7 new features.

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Proposed design-for-debug architecture based on distributed embedded logic analysis.

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Allocation unit

Trace Buffer => On chip area

Allocation unit to better utilize the storage space in all the trace buffers

Allocation unit

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Trace buffer control unit toupdate the status registersfor controlling the read/write operations of the trace buffers.

They are responsible in providing the appropriatecontrols to the Communication fabric in the proposed architecture

The queue control unit and the individual queue FSMs to monitor what and where segments of prioritized data are stored in the trace buffers in the background.

Top control unit so that only sample requests from low priority data sources should be ignored.

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(a) Overflowing trigger events. (b) Overwriting data in trace buffer.

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Example of using windows to support sampling before trigger. (a) Samplingbefore trigger. (b) After triggering.

Out-of-order offloading.

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(a) Insufficient bandwidth, resulting sample requests being dropped.

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Sufficient bandwidth to satisfy all sample requests.

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Segmented data.

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Nonsegmented data.

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Example of data sampling with different priority settings. (a) Prioritysetting 1. (b) Priority setting 2.

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Area investment analysis when varying the number of cores. Area investment analysis when varying

size/number of trace buffers.

Area investment analysis when varying the number of trace ports.

Effect of programmable priority on data loss.

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Area distribution among hardware components when varying the number of cores.

Area investment analysis when varying the organization of trace buffers.

Area distribution among hardware components when varying the number of trace ports. Impact of various features on acquisition of debug

data.

Conclusion

A distributed embedded logic analysis With shadow scan registers to improve real-

time observability during post-silicon validation.

Using two case studies on a digital video decoder analyzed the cost of managing on-chip

distributed trace buffers.

The Dfd hardware is below 30% of the total area required for debug.

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