GSM BASED VEHICLE THEFT CONTROL SYSTEM 1. INTRODUCTION 1.1 EMBEDDED SYSTEM: An embedded system is a special-purpose system in which the computer is completely encapsulated by or dedicated to the device or system it controls. Unlike a general-purpose computer, such as a personal computer, an embedded system performs one or a few predefined tasks, usually with very specific requirements. Since the system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product. Embedded systems are often mass- produced, benefiting from economies of scale. Personal digital assistants (PDAs) or handheld computers are generally considered embedded devices because of the nature of their hardware design, even though they are more expandable in software terms. This line of definition continues to blur as devices expand. With the introduction of the OQO Model 2 with the Windows XP operating system and ports such as a USB port 1
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Design & Development of a GSM Based Vehicle Theft Control System
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
1. INTRODUCTION
1.1 EMBEDDED SYSTEM:
An embedded system is a special-purpose system in which the computer is
completely encapsulated by or dedicated to the device or system it controls. Unlike a general-
purpose computer, such as a personal computer, an embedded system performs one or a few
predefined tasks, usually with very specific requirements. Since the system is dedicated to
specific tasks, design engineers can optimize it, reducing the size and cost of the product.
Embedded systems are often mass-produced, benefiting from economies of scale.
Personal digital assistants (PDAs) or handheld computers are generally considered
embedded devices because of the nature of their hardware design, even though they are more
expandable in software terms. This line of definition continues to blur as devices expand.
With the introduction of the OQO Model 2 with the Windows XP operating system and ports
such as a USB port
both features usually Belong to "general purpose computers", — the line of nomenclature
blurs even more.
Physically, embedded systems ranges from portable devices such as digital
watches and MP3 players, to large stationary installations like traffic lights, factory
controllers, or the systems controlling nuclear power plants.
In terms of complexity embedded systems can range from very simple with a
single microcontroller chip, to very complex with multiple units, peripherals and networks
mounted inside a large chassis or enclosure.
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
1.2 HISTORY:
In the 1960s, computers possessed an ability to acquire, analyze, process data, and
make decisions at very high speeds. However there were some disadvantages with the
computer controls. They were: high cost, program complexity, and hesitancy of personnel to
learn. However the new concept of electronic devices was evolved. They were called
programmable controllers which later became a part of embedded systems. This concept
developed from a mix of computer technology, solid state devices, and traditional electro
mechanical sequences. The first mass-produced embedded system was the Autonetics D-17
guidance computer for the Minuteman missile released in 1961. It was built from discrete
transistor logic and had a hard disk for main memory.
REQUIREMENTS OF TYPICAL EMBEDDED SYSTEMS: -
EX: CHEMICAL PLANT: Consider a chemical plant. No. of temperatures have to be
measured &based on values certain operations are performed, such as opening a value.
INPUT: - From sensors which measure temperatures.
OUTPUT: signal that controls a value.
Ex: MOBILE PHONES: The processor of a mobile phone needs to carry out a great deal of
communications protocol processing to make "TELEPHONECAL”.
Fig 1.1 Typical embedded sysytem organisation
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
1.3 CHARACTERISTICS:
Embedded systems often use a (relatively) slow processor and small memory size with an
intentionally simplified architecture to minimize costs.
Programs on embedded systems must often run with limited resources
Embedded system designers use compilers to develop an embedded system.
They often have no operating system or a speciali8zed embedded operating system
(often a real-time operating system ).
Programs on an embedded system often must run with resources: often there is no disk
drive, operating system, keyboard or screen. may replace rotating media, and a small
keypad and screen may be used instead of a PC's keyboard and screen.
Embedding a computer is to interact with the environment, often by monitoring and
controlling external machinery. In order to do this, analog inputs and outputs must be
transformed to and from digital signal levels.
1.4 APPLICATIONS OF EMBEDDED SYSTEMS:
Some widely used applications of embedded systems are listed below:
Automatic teller machines
Cellular telephones.
Computer network.
Disc drives.
Thermo stats.
Sprinklers.
Security monitoring systems.
Hand held calculations.
House-hold appliances.
Inertial guided systems.
Flight control hardware / software.
Medical equipment.
1.5 GSM
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
The Global System for Mobile Communications (GSM) is the most popular standard
for mobile phones in the world. GSM phones are used by over a billion people across more than
200 countries. The ubiquity of the GSM standard makes international roaming very common
between mobile phone operators, which enable phone users to access their services in many
other parts of the world as well as their own country. GSM differs significantly from its
predecessors in that both signaling and speech channels are digital, which means that it is seen as
a second generation (2G) mobile phone system. This fact has also meant that data
communication was built into the system from very early on. GSM is an open standard, which is
currently developed by the 3GPP.From the point of view of the consumer, the key advantage of
GSM systems has been higher digital voice quality and low cost alternatives to making calls such
as text messaging. The advantage for network operators has been 8 the ability to deploy
equipment from different vendors because the open standard allows easy inter-operability. Also,
the standards have allowed network operators to offer roaming services, which mean the
subscribers, can use their phone all over the world. GSM retained backward-compatibility with
the original GSM phones as the GSM standard continued to develop, for example packet data
capabilities were added in the Release '97 version of the standard, by means of GPRS. Higher
speed data transmission has also been introduced with EDGE in the Release '99 version of the
standard.
2. BLOCK DIAGRAM AND SCHEMATIC DIAGRAM4
GSM BASED VEHICLE THEFT CONTROL SYSTEM
2.1 BLOCK-DIAGRAM
FIG 2.1 Block diagram of vehicle theft control system
2.2 BLOCK DIAGRAM EXPLANATION:
The project “GSM BASED VEHICLE THEFT CONTROL SYSTEM” deals with
the design & development of a theft control system for automobiles which is being used to
prevent / control the theft of a vehicle. The developed system makes use of an embedded system
based on GSM technology. An interfacing mobile is also connected to the microcontroller, which
is in turn, connected to the engine.
Once, the vehicle is being stolen, the information is being used by the vehicle owner
for further processing. The information is passed onto the central processing insurance system,
where by sitting at a remote place, a particular number is dialed by them to the interfacing
mobile that is with the hardware kit which is installed in the vehicle. By reading the signals
received by the mobile, one can control the ignition of the engine; say to lock it or to stop the
engine immediately. Again it will come to the normal condition only after entering a secured
password. The owner of the vehicle & the centre processing system will know this secured
password. We can modify this concept such that the vehicle owner also can lock the vehicle from
his mobile phone.
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GSM MODEM
KEYPAD
MICRO
CONTROLLER
LCD
LED
MEMS ADC
GSM BASED VEHICLE THEFT CONTROL SYSTEM
The main concept in this design is introducing the mobile communications into the
embedded system. With the help of SIM tracking knows the location of vehicle and informs to
the local police or stops it from further movement.
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
2.3 SCHEMATIC DIAGRAM:
Fig 2.2 schematic diagram
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
2.4 SCHEMATIC DESCRIPTION:
The operation of this circuit mainly depends on the MEM sensor. The actual position
of the MEM sensor should be 90 degrees with respect to ground. If there is any change in the
actual position of the MEM a control signal will be given to the ADC. The ADC will convert
the analog signal to the digital signal and it will send the digital signal to the micro controller.
Micro controller will send a signal to the GSM module. As GSM receives a signal
from micro controller it informs the owner as “vehicle theft detected” through an SMS.
When the owner receives the above message he will send a message to the GSM module to
lock the engine. As the GSM receives a secret code from the owner it sends a signal to the
micro controller and the micro controller will lock the engine. As this is a protocol we have
shown the locking of the engine by glowing led.
After locking the engine, the owner can able to find the location of the Automobile
by using the signals generated by GSM. After reaching the position where vehicle was
locked, the owner enters an secret code to unlock the engine. In this way we can protect the
vehicles. And we can also use this as a accident sensor.
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
3. HARDWARE COMPONENTS
3.1 MICRO CONTROLLER (AT89S52)
3.1.1 INTRODUCTION:
A Micro controller consists of a powerful CPU tightly coupled with memory, various
I/O interfaces such as serial port, parallel port timer or counter, interrupt controller, data
acquisition interfaces-Analog to Digital converter, Digital to Analog converter, integrated on to a
single silicon chip.
If a system is developed with a microprocessor, the designer has to go for external
memory such as RAM, ROM, EPROM and peripherals. But controller is provided all these
facilities on a single chip. Development of a Micro controller reduces PCB size and cost of
design.
One of the major differences between a Microprocessor and a Micro controller is that
a controller often deals with bits not bytes as in the real world application.
Intel has introduced a family of Micro controllers called the MCS-51.
Fig 3.1.1 Micro controller
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
NECESSITY OF MICROCONTROLLERS:
Microprocessors brought the concept of programmable devices and made many
applications of intelligent equipment. Most applications, which do not need large amount of data
and program memory, tended to be:
Costly:
The microprocessor system had to satisfy the data and program requirements so,
sufficient RAM and ROM are used to satisfy most applications .The peripheral control
equipment also had to be satisfied. Therefore, almost all-peripheral chips were used in the
design. Because of these additional peripherals cost will be comparatively high.
An example:
8085 chip needs An Address latch for separating address from multiplex address and data.32-
KB RAM and 32-KB ROM to be able to satisfy most applications. As also Timer / Counter,
Parallel programmable port, Serial port, Interrupt controller are needed for its efficient
applications.
In comparison a typical Micro controller 8052 chip has all that the 8052 board has
except a reduced memory as follows. 4K bytes of ROM as compared to 32-KB, 128 Bytes of
RAM as compared to 32-KB.
Bulky:
On comparing a board full of chips (Microprocessors) with one chip with all
components in it (Micro controller)
Debugging:
Lots of Microprocessor circuitry and program to debug. In Micro controller there is
no Microprocessor circuitry to debug. Slower Development time: As we have observed
Microprocessors need a lot of debugging at board level and at program level, whereas, Micro
controller do not have the excessive circuitry and the built-in peripheral chips are easier to
program for operation.
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
So peripheral devices like Timer/Counter, Parallel programmable port, Serial
Communication Port, Interrupt controller and so on, which were most often used were integrated
with the Microprocessor to present the Micro controller .RAM and ROM also were integrated in
the same chip. The ROM size was anything from 256 bytes to 32Kb or more. RAM was
optimized to minimum of 64 bytes to 256 bytes or more.
Typical Micro controllers have all the following features:
8/16/32 CPU
Instruction set rich in I/O & bit operations.
One or more I/O ports.
One or more timer/counters.
One or more interrupt inputs and an interrupt controller
One or more serial communication ports.
Analog to Digital /Digital to Analog converter
One or more PWM output
Network controlled interface
Why AT 89C52? :
The system requirements and control specifications clearly rule out the use of 16, 32
or 64 bit micro controllers or microprocessors. Systems using these may be earlier to implement
due to large number of internal features. They are also faster and more reliable but, the above
application is satisfactorily served by 8-bit micro controller. Using an inexpensive 8-bit Micro
controller will doom the 32-bit product failure in any competitive market place.
Coming to the question of why to use AT89C52 of all the 8-bit Micro controller
available in the market the main answer would be because it has 8 Kb on chip flash memory
which is just sufficient for our application. The on-chip Flash ROM allows the program memory
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
to be reprogrammed in system or by conventional non-volatile memory Programmer. Moreover
ATMEL is the leader in
Flash technology in today’s market place and hence using AT 89C52 is the optimal
solution.
8052 micro controller architecture:
The 8052 architecture consists of these specific features:
Compatible with MCS®-51 Products
8K Bytes of In-System Programmable (ISP) Flash
4.0V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
256 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Eight Interrupt Sources
Full Duplex UART Serial Channel
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Watchdog Timer
Dual Data Pointer
Power-off Flag
Fast Programming Time
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
Flexible ISP Programming (Byte and Page Mode)
3.1.2 PIN DIAGRAM:
Fig -3.1.2 Pin out diagram of 89C52 ic
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
3.1.3 FUNCTIONAL BLOCK DIAGRAM OF MICROCONTROLLER
Fig 3.1.3 Functional block diagram of micro controller
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
3.1.4 Internal Block diagram:
Fig 3.
Fig 3.1.4 AT89C52 internal block diagram
The 8052 oscillator and clock:
The heart of the 8052 circuitry that generates the clock pulses by which all the
internal all internal operations are synchronized. Pins XTAL1 And XTAL2 is provided for
connecting a resonant network to form an oscillator. Typically a quartz crystal and capacitors are
employed. The crystal frequency is the basic internal clock frequency of the micro controller.
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
The manufacturers make 8052 designs that run at specific minimum and maximum frequencies
typically 1 to 16 MHz.
Types of memory:
The 8052 have three general types of memory. They are on-chip memory, external
Code memory and external Ram. On-Chip memory refers to physically existing memory on the
micro controller itself. External code memory is the code memory that resides off chip. This is
often in the form of an external EPROM. External RAM is the Ram that resides off chip. This
often is in the form of standard static RAM or flash RAM.
a) Code memory
Code memory is the memory that holds the actual 8052 programs that is to be run.
This memory is limited to 64K. Code memory may be found on-chip or off-chip. It is
possible to have 4K of code memory on-chip and 60K off chip memory simultaneously. If
only off-chip memory is available then there can be 64K of off chip ROM. This is controlled
by pin provided as Ea
b) Internal memory
The 8052 have a bank of 256 bytes of internal RAM. The internal RAM is found on-
chip. So it is the fastest Ram available. And also it is most flexible in terms of reading and
writing. Internal Ram is volatile, so when 8052 is reset, this memory is cleared. 256 bytes of
internal memory are subdivided. The first 32 bytes are divided into 4 register banks. Each
bank contains 8 registers. Internal RAM also contains 128 bits, which are addressed from 20h
to 2Fh. These bits are bit addressed i.e. each individual bit of a byte can be addressed by the
user. They are numbered 00h to 7Fh. The user may make use of these variables with
commands such as SETB and CLR.
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
Special Function registered memory:
Special function registers are the areas of memory that control specific functionality
of the 8052 micro controller.
a) Accumulator (0E0h)
As its name suggests, it is used to accumulate the results of large no of instructions. It
can hold 8 bit values
b) B register (0F0h)
The B register is very similar to accumulator. It may hold 8-bit value. The b register
is only used by MUL AB and DIV AB instructions. In MUL AB the higher byte of the product
gets stored in B register. In div AB the quotient gets stored in B with the remainder in A.
c) Stack pointer (81h)
The stack pointer holds 8-bit value. This is used to indicate where the next value to be
removed from the stack should be taken from. When a value is to be pushed onto the stack, the
8052 first store the value of SP and then store the value at the resulting memory location. When a
value is to be popped from the stack, the 8052 returns the value from the memory location
indicated by SP and then decrements the value of SP.
d) Data pointer
The SFRs DPL and DPH work together work together to represent a 16-bit value
called the data pointer. The data pointer is used in operations regarding external RAM and some
instructions code memory. It is a 16-bit SFR and also an addressable SFR.
e) Program counter
The program counter is a 16 bit register, which contains the 2 byte address, which
tells the 8052 where the next instruction to execute to be found in memory. When the 8052 is
initialized PC starts at 0000h. And is incremented each time an instruction is executes. It is not
addressable SFR.
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
f) PCON (power control, 87h)
The power control SFR is used to control the 8052’s power control modes. Certain
operation modes of the 8052 allow the 8052 to go into a type of “sleep mode” which consumes
much less power.
g) TCON (timer control, 88h)
The timer control SFR is used to configure and modify the way in which the 8052’s
two timers operate. This SFR controls whether each of the two timers is running or stopped and
contains a flag to indicate that each timer has overflowed. Additionally, some non-timer related
bits are located in TCON SFR. These bits are used to configure the way in which the external
interrupt flags are activated, which are set when an external interrupt occurs.
h) TMOD (Timer Mode, 89h)
The timer mode SFR is used to configure the mode of operation of each of the two
timers. Using this SFR your program may configure each timer to be a 16-bit timer, or 13 bit
timer, 8-bit auto reload timer, or two separate timers. Additionally you may configure the timers
to only count when an external pin is activated or to count “events ” that are indicated on an
external pin.
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
i) TO (Timer 0 low/high, address 8A/8C h)
These two SFRs taken together represent timer 0. Their exact behavior depends on
how the timer is configured in the TMOD SFR; however, these timers always count up. What is
configurable is how and when they increment in value.
j) T1 (Timer 1 Low/High, address 8B/ 8D h)
These two SFRs, taken together, represent timer 1. Their exact behavior depends on
how the timer is configured in the TMOD SFR; however, these timers always count up.
k)Timer 2:
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event
counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2).
Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud
rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2
consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is
incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the
count rate is 1/12 of the oscillator frequency.
Table 3. Timer 2 Operating Modes
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
In the Counter function, the register is incremented in response to a 1-to-0 transition
at its corresponding external input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples show a high in one cycle and a low
in the next cycle, the count is incremented. The new count value appears in the register
during S3P1 of the cycle following the one in which the transition was detected. Since two
machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the
maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is
sampled at least once before it changes, the level should be held for at least one full machine
cycle.
l) P0 (Port 0, address 90h, bit addressable)
This is port 0 latch. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0 of port
0 is pin P0.0, bit 7 is pin p0.7. Writing a value of 1 to a bit of this SFR will send a high level on
the corresponding I/O pin whereas a value of 0 will bring it to low level.
m) P1 (port 1, address 90h, bit addressable)
This is port latch1. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0 of port
0 is pin P1.0, bit 7 is pin P1.7. Writing a value of 1 to a bit of this SFR will send a high level on
the corresponding I/O pin whereas a value of 0 will bring it to low level
n) P2 (port 2, address 0A0h, bit addressable)
This is a port latch2. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0 of port
0 is pin P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit of this SFR will send a high level on
the corresponding I/O pin whereas a value of 0 will bring it to low level.
o) P3(port 3,address B0h, bit addressable)
This is a port latch3. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0 of port
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
0 is pin P3.0, bit 7 is pin P3.7. Writing a value of 1 to a bit of this SFR will send a high level on
the corresponding I/O pin whereas a value of 0 will bring it to low level
p) IE (interrupt enable, 0A8h):
The Interrupt Enable SFR is used to enable and disable specific interrupts. The low
7 bits of the SFR are used to enable/disable the specific interrupts, where the MSB bit is used to
enable or disable all the interrupts. Thus, if the high bit of IE is 0 all interrupts are disabled
regardless of whether an individual interrupt is enabled by setting a lower bit.
q) IP (Interrupt Priority, 0B8h)
The interrupt priority SFR is used to specify the relative priority of each interrupt. On
8052, an interrupt maybe either low or high priority. An interrupt may interrupt interrupts. For
e.g., if we configure all interrupts as low priority other than serial interrupt. The serial interrupt
always interrupts the system, even if another interrupt is currently executing. However, if a serial
interrupt is executing no other interrupt will be able to interrupt the serial interrupt routine since
the serial interrupt routine has the highest priority.
r) PSW (Program Status Word, 0D0h)
The program Status Word is used to store a number of important bits that are set and
cleared by 8052 instructions. The PSW SFR contains the carry flag, the auxiliary carry flag, the
parity flag and the overflow flag. Additionally, it also contains the register bank select flags,
which are used to select, which of the “R” register banks currently in use.
s) SBUF (Serial Buffer, 99h)
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SBUF is used to hold data in serial communication. It is physically two registers.
One is writing only and is used to hold data to be transmitted out of 8052 via TXD. The other is
read only and holds received data from external sources via RXD. Both mutually exclusive
registers use address 99h.
I/O ports:
One major feature of a microcontroller is the versatility built into the input/output
(I/O) circuits that connect the 8052 to the outside world. The main constraint that limits
numerous functions is the number of pins available in the 8052 circuit. The DIP had 40 pins and
the success of the design depends on the flexibility incorporated into use of these pins. For this
reason, 24 of the pins may each used for one of the two entirely different functions which
depend, first, on what is physically connected to it and, then, on what software programs are used
to “program” the pins.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink
eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance
inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during
accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also
receives the code bytes during Flash programming and outputs the code bytes during program
verification. External pull-ups are required during program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers
can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the
inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being
pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1
can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter
2 trigger input (P1.1/T2EX), respectively, as shown in the follow-ing table. Port 1 also receives
the low-order address bytes during Flash programming and verification.
Port 2
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Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the
inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being
pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order
address byte during fetches from external program memory and dur-ing accesses to external data
memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong
internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit
addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2
also receives the high-order address bits and some control signals during Flash program-ming
and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers
can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the
inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals
for Flash programming and verification. Port 3 also serves the functions of various special
features of the
AT89S52, as shown in the fol-lowing table
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The
DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state
of bit DISRTO, the RESET HIGH out feature is enabled.
ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the address
during accesses to external memory. This pin is also the program pulse input (PROG) during
Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator
frequency and may be used for external timing or clocking purposes. Note, however, that one
ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can
be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a
MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable
bit has no effect if the microcontroller is in external execution mode.
INTERRUPTS:
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
Interrupts are hardware signals that are used to determine conditions that exist in external
and internal circuits. Any interrupt can cause the 8052 to perform a hardware call to an interrupt
–handling subroutine that is located at a predetermined absolute address in the program memory.
Five interrupts are provided in the 8052. Three of these are generated automatically
by the internal operations: Timer flag 0, Timer Flag 1, and the serial port interrupt (RI or TI)
Two interrupts are triggered by external signals provided by the circuitry that is connected to the
pins INTO 0 and INTO1. The interrupts maybe enable or disabled, given priority or otherwise
controlled by altering the bits in the Interrupt Enabled (IE) register, Interrupt Priority (IP)
register, and the Timer Control (TCON) register. . These interrupts are mask able i.e. they can be
disabled. Reset is a non maskable interrupt which has the highest priority. It is generated when a
high is applied to the reset pin. Upon reset, the registers are loaded with the default values.
Each interrupt source causes the program to do store the address in PC onto the stack and
causes a hardware call to one of the dedicated addresses in the program memory. The appropriate
memory locations for each for each interrupt are as follows:
In interrupt A Address
Rr RESET 00 00
IE E0 (External interrupt 0) 00 03
T F0 (Timer 0 interrupt) 00 0B
I E1 (External interrupt 1) 00 13
T F1 (Timer 1 interrupt) 00 1B
S SERIAL 00 23
The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with
4K bytes of Flash programmable and erasable read only memory (PEROM). The device is
manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with
the industry-standard MCS-51 instruction set and pin out. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer.
By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
powerful microcomputer, which provides a highly flexible and cost-effective solution to many
embedded control applications.
Hardware details:
The on chip oscillator of 89C52 can be used to generate system clock. Depending
upon version of the device, crystals from 3.5 to 12 MHz may be used for this purpose. The
system clock is internally divided by 6 and the resultant time period becomes one processor
cycle. The instructions take mostly one or two processor cycles to execute, and very occasionally
three processor cycles. The ALE (address latch enable) pulse rate is 16th of the system clock,
except during access of internal program memory, and thus can be used for timing purposes.
AT89C52 Serial port pins
PIN ALTERNATE USE SFR
P3.O RXD Seria data input SBUF
P3.I TXD Serial data output SBUF
P3.2 INTO External interrupt 0 TCON-1
P3.3 INT1 External interrupt 1 TCON- 2
P3.4 TO External timer 0 input TMOD
P3.5 T1 External timer 1 input TMOD
P3.6 WR External memory write pulse ---------
P3.7 RD External memory read pulse ----
Table – AT89C52 serial port pins
The two internal timers are wired to the system clock and prescaling factor is decided
by the software, apart from the count stored in the two bytes of the timer control registers. One
of the counters, as mentioned earlier, is used for generation of baud rate clock for the UART. It
would be of interest to know that the 8052 have a third timer, which is usually used for
generation of baud rate. The reset input is normally low and taking it high resets the micro controller,
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
In the present hardware, a separate CMOS circuit has been used for generation of reset signal so
that it could be used to drive external devices as well.
Writing the software:
The 89C52 has been specifically developed for control applications. As mentioned
earlier, out of the 128 bytes of internal RAM, 16 bytes have been organized in such a way that all
the 128 bits associated.
With this group may be accessed bit wise to facilitate their use for bit set/reset/test
applications. These are therefore extremely useful for programs involving individual logical
operations. One can easily give example of lift for one such application where each one of the
floors, door condition, etc may be depicted by a single hit. The 89C52 has instructions for bit
manipulation and testing. Apart from these, it has 8-bit multiply and divide instructions, which
may be used with advantage. The 89C52 has short branch instructions for 'within page' and
conditional jumps, short jumps and calls within 2k memory space which are very convenient,
and as such the controller seems to favor programs which are less than 2k byte long. Some
versions of 8751 EPROM devices have a security bit which can be programmed to lock the
device and then the contents of internal program EPROM cannot be read. The device has to be
erased in full for further alteration, and thus it can only be reused but not copied. EEPROM and
FLASH memory versions of the device are also available now.
Memory unit:
Memory is part of the micro controller whose function is to store data. The easiest
way to explain it is to describe it as one big closet with lots of drawers. If we suppose that we
marked the drawers in such a way that they cannot be confused, any of their contents will then be
easily accessible. It is enough to know the designation of the drawer and so its contents will be
known to us for sure.
Memory components are exactly like that. For a certain input we get the contents of a
certain addressed memory location and that’s all. Two new concepts are brought to us:
addressing and memory location. Memory consists of all memory locations, and addressing is
nothing but selecting one of them. This means that we need to select the desired memory
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
location on one hand, and on the other hand we need to wait for the contents of that location.
Besides reading from a memory location, memory must also provide for writing onto it. This is
done by supplying an additional line, called control line. We will designate this line as R/W
(read/write). Control line is used in the following way: if r/w=1, reading is done, and if opposite
is true then writing is done on the memory location. Memory is the first element, and we need a
few operation of our micro controller.
Central Processing Unit:
Let add 3 more memory locations to a specific block that will have a built in
capability to multiply, divide, subtract, and move its contents from one memory location onto
another. The part we just added in is called “central processing unit” (CPU). Its memory
locations are called registers.
Registers are therefore memory locations whose role is to help with performing
various mathematical operations or any other operations with data wherever data can be found.
Look at the current situation. We have two independent entities (memory and CPU), which are
interconnected, and thus any exchange of data is hindered, as well as its functionality. If, for
example, we wish to add the contents of two memory locations and return the result again back
to memory, we would need a connection between memory and CPU. Simply stated, we must
have some “way” through data goes from one block to another.
Bus:
That “way” is called “bus”. Physically, it represents a group of 8, 16, or more wires.
There are two types of buses: address and data bus. The first one consists of as many lines as the
amount of memory we wish to address, and the other one is as wide as data, in our case 8 bits or
the connection line. First one serves to transmit address from CPU memory, and the second to
connect all blocks inside the micro controller.
Input-output unit:
Those locations we’ve just added are called “ports”. There are several types of ports:
input, output or bi-directional ports. When working with ports, first of all it is necessary to
choose which port we need to work with, and then to send data to, or take it from the port.
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
When working with it the port acts like a memory location. Something is simply being
written into or read from it, and it could be noticed on the pins of the micro-controller.
3.2 555 TIMER IC
The 555 Timer IC is an integrated circuit (chip) implementing a variety of timer and
multi vibrator applications. The IC was designed by Hans R. Camenzind in 1970 and brought to
market in 1971 by Signetics (later acquired by Philips). The original name was the SE555 (metal
can)/NE555 (plastic DIP) and the part was described as "The IC Time Machine". It has been
claimed that the 555 gets its name from the three 5 kΩ resistors used in typical early
implementations, but Hans Camenzind has stated that the number was arbitrary. The part is still
in wide use, thanks to its ease of use, low price and good stability. As of 2003, it is estimated that
1 billion units are manufactured every year.
Depending on the manufacturer, the standard 555 package includes over 20
transistors, 2 diodes and 15 resistors on a silicon chip installed in an 8-pin mini dual-in-line
package (DIP-8). Variants available include the 556 (a 14-pin DIP combining two 555s on one
chip), and the 558 (a 16-pin DIP combining four slightly modified 555s with DIS & THR
connected internally, and TR falling edge sensitive instead of level sensitive).
Ultra-low power versions of the 555 are also available, such as the 7555 and TLC555. The 7555
requires slightly different wiring using fewer external components and less power.
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
The 555 has three operating modes:
Monostable mode:
In this mode, the 555 functions as a "one-shot". Applications include timers, missing
pulse detection, bounce free switches, touch switches, frequency divider, capacitance
measurement, pulse-width modulation (PWM) etc
A stable - free running mode:
The 555 can operate as an oscillator. Uses include LED and lamp flashers, pulse
generation, logic clocks, tone generation, security alarms, pulse position modulation, etc.
Bi stable mode or Schmitt trigger:
The 555 can operate as a flip-flop, if the DIS pin is not connected and no capacitor
is used. Uses include bounce free latched switches, etc. The 555 Timer IC is available as an
8-pin metal can, an 8-pin mini DIP (dual-in-package) or a 14-pin DIP.
This IC consists of 23 transistors, 2 diodes and 16 resistors. The explanation of
terminals coming out of the 555 timer IC is as follows. The pin number used in the
following discussion refers to the 8-pin DIP and 8-pin metal can packages.
3.2.1 555 timer ic pin diagram
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
555 timer IC 8 pin configuration
Pin 1: Grounded Terminal. All the voltages are measured with respect to this terminal.
Pin 2: Trigger Terminal. This pin is an inverting input to a comparator that is responsible for
transition of flip-flop from set to reset. The output of the timer depends on the amplitude of the
external trigger pulse applied to this pin.
Pin 3: Output Terminal. Output of the timer is available at this pin. There are two ways in
which a load can be connected to the output terminal either between pin 3 and ground pin (pin 1)
or between pin 3 and supply pin (pin 8). The load connected between pin 3 and ground supply
pin is called the normally on load and that connected between pin 3 and ground pin is called the
normally off load.
Pin 4: Reset Terminal. To disable or reset the timer a negative pulse is applied to this pin
due to which it is referred to as reset terminal. When this pin is not to be used for reset purpose,
it should be connected to + VCC to avoid any possibility of false triggering.
Pin 5: Control Voltage Terminal. The function of this terminal is to control the threshold
and trigger levels. Thus either the external voltage or a pot connected to this pin determines the
pulse width of the output waveform. The external voltage applied to this pin can also be used to
modulate the output waveform. When this pin is not used, it should be connected to ground
through a 0.01 micro Farad to avoid any noise problem.
Pin 6: Threshold Terminal. This is the non-inverting input terminal of comparator 1, which
compares the voltage applied to the terminal with a reference voltage of 2/3 VCC. The amplitude
of voltage applied to this terminal is responsible for the set state of flip-flop.
Pin 7: Discharge Terminal. This pin is connected internally to the collector of transistor and
mostly a capacitor is connected between this terminal and ground. It is called discharge terminal
because when transistor saturates, capacitor discharges through the transistor. When the
transistor is cut-off, the capacitor charges at a rate determined by the external resistor and
capacitor.
Pin 8: Supply Terminal. A supply voltage of + 5 V to + 18 V is applied to this terminal with
respect to ground (pin 1).
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
The 555 timer IC is an amazingly simple yet versatile device. It has been around now
for many years and has been reworked into a number of different technologies. The two primary
versions today are the original bipolar design and the more recent CMOS equivalent. These
differences primarily affect the amount of power they require and their maximum frequency of
operation; they are pin-compatible and functionally interchangeable.
This page contains only a description of the 555 timer IC itself. Functional circuits
and a few of the very wide range of its possible applications will be covered in additional pages
in this category.
The operation of the 555 timer revolves around the three resistors that form a voltage
divider across the power supply, and the two comparators connected to this voltage divider. The
IC is quiescent so long as the trigger input (pin 2) remains at +VCC and the threshold input (pin 6)
is at ground. Assume the reset input (pin 4) is also at +VCC and therefore inactive, and that the
control voltage input (pin 5) is unconnected. Under these conditions, the output (pin 3) is at
ground and the discharge transistor (pin 7) is turned on, thus grounding whatever is connected to
this pin.
The three resistors in the voltage divider all have the same value (5K in the bipolar
version of this IC), so the comparator reference voltages are 1/3 and 2/3 of the supply voltage,
whatever that may be. The control voltage input at pin 5 can directly affect this relationship,
although most of the time this pin is unused.
The internal flip-flop changes state when the trigger input at pin 2 is pulled down
below +VCC/3. When this occurs, the output (pin 3) changes state to +VCC and the discharge
transistor (pin 7) is turned off. The trigger input can now return to +VCC; it will not affect the
state of the IC.
However, if the threshold input (pin 6) is now raised above (2/3)+VCC, the output will
return to ground and the discharge transistor will be turned on again. When the threshold input
returns to ground, the IC will remain in this state, which was the original state when we started
this analysis.
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
The easiest way to allow the threshold voltage (pin 6) to gradually rise to (2/3)+VCC is
to connect it to a capacitor being allowed to charge through a resistor. In this way we can adjust
the R and C values for almost any time interval we might want.
The 555 can operate in either monostable or astable mode, depending on the
connections to and the arrangement of the external components. Thus, it can either produce a
single pulse when triggered, or it can produce a continuous pulse train as long as it remains
powered.
In monostable mode, the timing interval, t, is set by a single resistor and capacitor, as
shown to the right. Both the threshold input and the discharge transistor (pins 6 & 7) are
connected directly to the capacitor, while the trigger input is held at +VCC through a resistor. In
the absence of any input, the output at pin 3 remains low and the discharge transistor prevents
capacitor C from charging.
When an input pulse arrives, it is capacitively coupled to pin 2, the trigger input. The
pulse can be either polarity; its falling edge will trigger the 555. At this point, the output rises to
+VCC and the discharge transistor turns off. Capacitor C charges through R towards +VCC. During
this interval, additional pulses received at pin 2 will have no effect on circuit operation.
The standard equation for a charging capacitor applies here: e = E(1 - (-t/RC)). Here,
"e" is the capacitor voltage at some instant in time, "E" is the supply voltage, VCC, and " " is the
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
base for natural logarithms, approximately 2.718. The value "t" denotes the time that has passed,
in seconds, since the capacitor started charging.
We already know that the capacitor will charge until its voltage reaches (2/3)+VCC,
whatever that voltage may be. This doesn't give us absolute values for "e" or "E," but it does give
us the ratio e/E = 2/3. We can use this to compute the time, t, required to charge capacitor C to
the voltage that will activate the threshhold comparator:
2/3 = 1 - (-t/RC)
-1/3 = - (-t/RC)
1/3 = (-t/RC)
ln(1/3) = -t/RC
-1.0986123 = -t/RC
t = 1.0986123RC
t = 1.1RC
The value of 1.1RC isn't exactly precise, of course, but the round off error amounts to
about 0.126%, which is much closer than component tolerances in practical circuits, and is very
easy to use. The values of R and C must be given in Ohms and Farads, respectively, and the time
will be in seconds. You can scale the values as needed and appropriate for your application,
provided you keep proper track of your powers of 10. For example, if you specify R in megohms
and C in microfarads, t will still be in seconds. But if you specify R in kilo ohms and C in
microfarads, t will be in milliseconds. It's not difficult to keep track of this, but you must be sure
to do it accurately in order to correctly calculate the component values you need for any given
time interval. The timing interval is completed when the capacitor voltage reaches the (2/3)+VCC
upper threshold as monitored at pin 6. When this threshold voltage is reached, the output at pin 3
goes low again, the discharge transistor (pin 7) is turned on, and the capacitor rapidly discharges
back to ground once more. The circuit is now ready to be triggered once again.
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
If we rearrange the circuit slightly so that both the trigger and threshold inputs are
controlled by the capacitor voltage, we can cause the 555 to trigger itself repeatedly. In this case,
we need two resistors in the capacitor charging path so that one of them can also be in the
capacitor discharge path. This gives us the circuit shown to the left.
In this mode, the initial pulse when power is first applied is a bit longer than the
others, having a duration of 1.1(Ra + Rb)C. However, from then on, the capacitor alternately
charges and discharges between the two comparator threshold voltages. When charging, C starts
at (1/3)Vcc and charges towards VCC. However, it is interrupted exactly halfway there, at
(2/3)VCC.Therefore, the charging time, t1, is ln(1/2)(Ra + Rb)C = 0.693(Ra + Rb)C.
When the capacitor voltage reaches (2/3)VCC, the discharge transistor is enabled (pin
7), and this point in the circuit becomes grounded. Capacitor C now discharges through Rb
alone. Starting at (2/3)VCC, it discharges towards ground, but again is interrupted halfway there,
at (1/3)VCC. The discharge time, t2, then, is -ln(1/2)(Rb)C = 0.693(Rb)C.The total period of the
pulse train is t1 + t2, or 0.693(Ra + 2Rb)C. The output frequency of this circuit is the inverse of
the period, or 1.44/(Ra + 2Rb)C.
Note that the duty cycle of the 555 timer circuit in astable mode cannot reach 50%. On time must
always be longer than off time, because Ra must have a resistance value greater than zero to
prevent the discharge transistor from directly shorting VCC to ground. Such an action would
immediately destroy the 555 IC.
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
One interesting and very useful feature of the 555 timer in either mode is that the
timing interval for either charge or discharge is independent of the supply voltage, VCC. This is
because the same VCC is used both as the charging voltage and as the basis of the reference
voltages for the two comparators inside the 555. Thus, the timing equations above depend only
on the values for R and C in either operating mode.
In addition, since all three of the internal resistors used to make up the reference
voltage divider are manufactured next to each other on the same chip at the same time, they are
as nearly identical as can be. Therefore, changes in temperature will also have very little effect
on the timing intervals, provided the external components are temperature stable. A typical
commercial 555 timer will show a drift of 50 parts per million per Centigrade degree of
temperature change (50 ppm/°C) and 0.01%/Volt change in VCC. This is negligible in most
practical applications
3.3 ADC 0808
The ADC0808/ADC0809 data acquisition component is a monolithic CMOS device
with an 8-bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible
control logic. The 8-bit A/D converter uses successive approximation as the conversion
technique. The converter features a high impedance chopper stabilized comparator, a 256R
voltage divider with analog switch tree and a successive approximation register. The 8-channel
multiplexer can directly access any of 8-single-ended analog signals. The device eliminates the
need for external zero and full-scale adjustments. Easy interfacing to microprocessors is
provided by the latched and decoded multiplexer address inputs and latched TTL TRI-STATE
outputs.
The design of the ADC0808, ADC0809 has been optimized by incorporating the most
desirable aspects of several A/D conversion techniques. The ADC0808, ADC0809 offers high
speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and
repeatability, and consumes minimal power. These features make this device ideally suited to
applications from process and machine control to consumer and automotive applications. For 16
channels multiplexer with common output (sample/hold port) see ADC0816 data sheet.
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
FEATURES:
Easy interface to all microprocessors
Operates ratio metrically or with 5 VDC or analog span adjusted voltage reference
No zero or full-scale adjust required
8-channel multiplexer with address logic
0V to VCC input range
Outputs meet TTL voltage level specifications
ADC0808 equivalent to MM74C949
KEY SPECIFICATIONS:
Resolution 8 Bits
Total Unadjusted Error ±½ LSB and ±1 LSB
Single Supply 5 VDC
Low Power 15 mW
Conversion Time 100 μs
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
BLOCK DIAGRAM:
3.3 .1 Block diagram of ADC 0808
PIN DIAGRAM OF ADC 0808
3.3.2 Pin diagram of ADC 0808
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
FUNCTIONAL DESCRIPTION:
MULTIPLEXER:
The device contains an 8-channel single-ended analog signal multiplexer. A particular
input channel is selected by using the address decoder. Table 1 shows the input states for the
address lines to select any channel. The address is latched into the decoder on the low-to-high
transition of the address latch enable signal.
CONVERTER CHARACTERISTICS:
The Converter:
The heart of this single chip data acquisition system is its 8- bit analog-to-digital
converter. The converter is designed to give fast, accurate, and repeatable conversions over a
wide range of temperatures. The converter is partitioned into 3 major sections: the 256R ladder
network, the successive approximation register, and the comparator. The converter's digital
outputs are positive true. The 256R ladder network approach shown in f igure 4.2 was chosen
over the conventional R/2R ladder because of its inherent mono tonicity, which guarantees no
missing digital codes. Mono tonicity is particularly important in closed loop feedback control
systems. A non-monotonic relationship can cause oscillations that will be catastrophic for the
system. Additionally, the 256R network does not cause load variations on the reference voltage.
3.3.3 Ladder network
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GSM BASED VEHICLE THEFT CONTROL SYSTEM
The bottom resistor and the top resistor of the ladder network in figure4.3 are not the
same value as the remainder of the network. The difference in these resistors causes the output
characteristic to be symmetrical with the zero and full-scale points of the transfer curve. The first
output transition occurs when the analog signal has reached +½ LSB and succeeding output
transitions occur every 1 LSB later up to full-scale. The successive approximation register (SAR)
performs 8 iterations to approximate the input voltage. For any SAR type converter, n-iterations
are required for an n-bit converter.
The most important section of the A/D converter is the comparator. It is this section
which is responsible for the ultimate accuracy of the entire converter. It is also the comparator
drift which has the greatest influence on the repeatability of the device. A chopper-stabilized
comparator provides the most effective method of satisfying all the converter requirements. The
chopper-stabilized comparator converts the DC input signal into an AC signal. This signal is then
fed through a high gain AC amplifier and has the DC level restored. This technique limits the
drift component of the amplifier since the drift is a DC component which is not passed by the AC
amplifier. This makes the entire A/D converter extremely insensitive to temperature, long term
drift and input offset errors.
3.4 RS 232:
In telecommunications, RS-232 (Recommended Standard 232) is a standard for serial
binary data signals connecting between a DTE (Data terminal equipment) and a DCE (Data
Circuit-terminating Equipment). It is commonly used in computer serial ports.
Scope of the standard:
The Electronic Industries Alliance (EIA) standard RS-232-C as of 1969 defines:
Electrical signal characteristics such as voltage levels, signaling rate, timing and slew-
rate of signals, voltage withstand level short-circuit behavior, and maximum load
capacitance.
Interface mechanic characteristics, pluggable connectors and pin identification.
Functions of each circuit in the interface connector.