Design Compiler Eng

ASIC Design Flow

Design Compiler

Asic Desgin Flow

Design Compiler

Asic Desgin Flow

● Directory structure● Design compiler step by step

Design Compiler

Asic Desgin Flow

● Directory structure<Project> / ---Project directory

- leda/ --- Check rule

- vcs -- Check timing and verification

- dc --- Design compiler : generate Netlist

● rpt --- report ● work --- ● syn --- synthesis : contain files *.ddc, *.v after synthesis

- fm --- Formality

- pt --- Primetime

- icc --- Layout

Design Compiler

Asic Desgin Flow

Design Compiler

● Design compiler step by stepStep 1Step 1: Invoke Desgin Compiler GUI flow steps :

– Open termial

– go to folder “dc” in project directory

– design_vision OR dc_shell → start_gui

Setp 2Setp 2: Setup Library

– File → Setup

Asic Desgin Flow

● Design compiler step by step

Design CompilerDesign CompilerDesign Compiler

Asic Desgin Flow

● Design compiler step by step

- Search pathSearch path: path for searching file

→ link to directory contain library technology

– Target libraryTarget library : link to file *.db in library technology

– Symbol librarySymbol library: link to file “generic.sdb”

/usr/synopsys/dc/libraries/syn/generic.sdb

– Link libraryLink library : link to both file *.db and *. sldb

– Synthetic librarySynthetic library : dw_foundation.sldb /usr/synopsys/dc/libraries/syn/dw_foundation.sldb

//NOTE: support library technology

Design Compiler

Asic Desgin Flow

● Design compiler step by stepStep 3Step 3: creat file “*.svf” // file *.svf use for Formality

Generate a Formality setup imformation file for efficient compare-point mathching in Formality

Design Compiler

Asic Desgin Flow

● Design compiler step by stepStep 4Step 4: Read file <top_module.v>

File → Read → “top_module.v”

Design Compiler

Asic Desgin Flow

● Design compiler step by stepStep 5Step 5: Analyze

file →analyze → Add→

< top_module.v >→OK

Design Compiler

Asic Desgin Flow

● Design compiler step by step● Step 6Step 6: ElaborateFile → Elaborate → OK

Design Compiler

Asic Desgin FlowAsic Desgin Flow

● Design compiler step by step

Step 7Step 7: Check design: Design→Check design→OK

Design Compiler

Asic Desgin Flow

● Design compiler step by step

Step 8Step 8: Set clock constraints

1- Creat design schematic- click icon on Design Vision GUI

Design Compiler

Asic Desgin Flow

● Design compiler step by step

Design Compiler

Asic Desgin Flow

● Design compiler step by step2- Creat clock:

- Name : clk ; cycle = 4ns

- Use key I & O to zoom in

and zoom out

- Click “clk” in Schematic

Design Compiler

Asic Desgin Flow

● Design compiler step by step

3- Specify clk:Then click on “Attributes” in Design Vision GUI → specify clock

- At “Port name” must be have “clk”

- At “clock name”: clk // clk is specfied

- At “period” : 4 // a cycle = 4 time unit

- Check in “don't touch network” and “fix hold”

● After click OK look at terminal have a comman:

create_clock -name "clk" -period 4 -waveform { 0.000 2.000 } { clk }

→ OK

Design Compiler

Asic Desgin Flow

● Design compiler step by step

Design Compiler

Asic Desgin Flow

● Design compiler step by step

Step 9Step 9: Optimize the design : Design → Compile design...

Design Compiler

Asic Desgin Flow

● Design compiler step by stepStep 10Step 10: Optimized the design : Design → Compile Ultra...

Design Compiler

Asic Desgin Flow

● Design compiler step by step

Step 11Step 11: Report

1- Report - report_timing : Timing → Report Timing Path

- report_constraint : Design → Report Constraint

- report_power : Design →Report Power

- report_resource : Design → Report Design Resources

Design Compiler

Asic Desgin Flow

● Design compiler step by step

2- Save report :

Design Compiler

Asic Desgin Flow

● Design compiler step by step

Step 12Step 12: Creat NETLIST - “top.v” :

● File → Save As

Design Compiler

Asic Desgin Flow

● Design compiler step by step

Step 13Step 13: creat file “top.ddc”

Save the unmapped design

Design Compiler

Asic Desgin Flow

● Design compiler step by stepStep 14Step 14 : creat file “top.sdf”

write a Standard Delay Format back annotation file

Design Compiler

Asic Desgin Flow

● Design compiler step by stepStep 15Step 15: Creat file : “top.sdc”

write out a script in synopsys Design Constraint (sdc)format

Design Compiler

Asic Desgin Flow

● Design compiler step by step

Step 16Step 16 : Set_svf_off

Design Compiler

Asic Desgin Flow

Question?

Design Compiler

Asic Desgin Flow