Design and Verification of a Layer-2 MAC Classification Engine for a Gigabit Ethernet Switch Jorge Tonfat Ricardo Reis Universidade Federal do Rio Grande.

Design and Verification of a Layer-2 MAC Classification Engine for a Gigabit Ethernet SwitchJorge TonfatRicardo Reis

Universidade Federal do Rio Grande do Sul (UFRGS)Instituto de Informática - PPGC/PGMicro

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MotivationMotivationObjectivesObjectivesNetFPGA PlatformNetFPGA PlatformL2 Classification EngineL2 Classification EngineVerification MethodologyVerification MethodologyImplementation ResultsImplementation ResultsConclusionsConclusions

OutlineOutline

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Ethernet is the most popular layer 2 protocol.Widely used in LANs and MANs.Ethernet best characteristics:

It has a low implementation cost compared with other technologies.High performance

MotivationMotivation

LAN = Local Area NetworkMAN = Metropolitan Area Network

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Design of a L2 classification engine for a Gigabit Ethernet switch deployed at an industrial product.

The main function of the Layer-2 classification engine is to forward Ethernet frames to their corresponding output ports.

The classification engine should be able to process VLAN frames. (compliant with IEEE 802.1Q)

ObjectivesObjectives

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NetFPGA PlatformNetFPGA PlatformDeveloped at Stanford University. Enable fast prototyping of networking hardware.Offers basic hardware modular structure.

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NetFPGA PlatformNetFPGA Platform

Frames inside the data pipeline have their own header format.

Contains information such as frame size, source port and destination port.

New modules can add more headers.

NetFPGA module headers

Ethernet FrameEthernet Frame

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The L2 switching task needs:

MAC address

Source Port

VLAN ID

Related solutions:

Binary and Ternary CAMs.

Not feasible for large L2 tables.

Power hungry and high cost per bit.

Software-only switching task.

Low performance results.

L2 Classification EngineL2 Classification Engine

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One popular solution:

Hashing functions

Some disadvantages:

Hash collisions.

Decreased table capacity.

Preferred characteristic:

relatively uniform distribution of output values (mem addr)

This will reduce the hash collisions and improve the table capacity.

L2 Classification EngineL2 Classification Engine

To deal with hash collisions , the lookup table is organized in buckets that contain multiple entries.

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Implements the main function of the Gigabit Ethernet Switch: the frame forwarding and learning.

This module is part of the datapath. The classification engine is part of the output port lookup module.

M A CR xQ

C P UR xQ

M A CR xQ

C P UR xQ

M A CR xQ

C P UR xQ

M A CR xQ

C P UR xQ

M A CTxQ

C P UTxQ

M A CTxQ

C P UTxQ

M A CTxQ

C P UTxQ

M A CTxQ

C P UTxQ

IN P U TA R B ITE R

O U TP U TP O R T

L O O K U P

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F R A M EM A R K E R

L2 Classification EngineL2 Classification Engine

L2 Classification EngineL2 Classification EngineMain Tasks:

Frame forwarding.Source MAC address learning.

Secondary task:MAC address lookup table aging.

Since the SRAM is accessed by three different sources (the forwarding/learning module, the aging module and the external access through the register bus) an arbiter is needed.

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L2 Classification EngineL2 Classification Engine

C yc le 0 C yc le 1 C yc le 2 C yc le 3 C yc le 4 C yc le 5 C yc le 6 C yc le 7 C yc le 8 C yc le 9 C yc le 10 C yc le 11 C yc le 12 C yc le 13 C yc le 14 C yc le 15

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F 1

SRAM arbiter FSM cycles, showing only the memory requests.

To achieve the bandwidth of 42 Gbps, each frame is needed to be processed in 8 cycles for a 500 MHz clock.

Since 11 cycles are needed to process one frame, two frames are processed interleaved. Remembering that for each cycle, only one kind of request (read/write) is possible.

Cycle 7 and Cycle 15 are used to process requests from the aging module and for external access.

C yc le 0 C yc le 1 C yc le 2 C yc le 3 C yc le 4 C yc le 5 C yc le 6 C yc le 7 C yc le 8 C yc le 9 C yc le 10 C yc le 11 C yc le 12 C yc le 13 C yc le 14 C yc le 15

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F 1 F 1 F 1 F 1F 1 R D R E Q

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Design a L2 classification engine...

Verification MethodologyVerification MethodologyA testbench environment was developed using SystemVerilog and Modelsim. It is organized in layers.

DUV: Design Under Verification

The module was synthesized with different MAC Address lookup table sizes: 4K, 32K, 64K and 128K.All of them obtain an operation frequency of 500 MHz and constant bandwidth of 42 Gbps.It was used Cadence tools and a TSMC standard cell library.

Implementation ResultsImplementation Results

Solution Op. Freq. (MHz)

Bandwidth (Gbps)

Technology Process

This work 500 42 TSMC 180nm

[Lau03] 125 22 180nm

[Mishra03] 10 180nm

[Papaefstathiou06] 400 103.5 UMC 130nm

[Papaefstathiou06] has a better bandwidth but is important to note that the bandwidth they show is an average one that depends on the number of collisions and on the size of the table. The results shown are for a 64K table. The ones obtained with a 32K table gives a bandwidth reduced by 25%. The bandwidth in our solution is independent of the table size.

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The architecture presented in this work achieves the necessary throughput for a 42-port Gigabit Ethernet.

It is more time-efficient compared with simpler methods such as direct-test.

The results are good ones comparing to other solutions.

The functional verification stage allows to discover circuit bugs using constrained random stimulus.

ConclusionsConclusions

Design and Verification of a Layer-2 MAC Classification Engine for a Gigabit Ethernet Switch

ICECS 2010 – Athens, Greece

Jorge TonfatRicardo Reis

Universidade Federal do Rio Grande do Sul (UFRGS)Instituto de Informática - PPGC/PGMicro

[email protected], [email protected]

Eventsto not loose

LASCASLASCAS 20112011Second IEEE Latin American Symposium on Circuits and SystemsFebruary 23-25, 2011 Bogotá, Colombia

webpage: lascas.org

IBERCHIP 2011XVII Iberchip WorkshopFebruary 23-25, 2011 Bogotá, Colombia

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CHIP ON THE CLIFFSSBCCI2011SBMicro2011August 30 - September 2, 2011 João Pessoa, Brazil

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CHIP ON THE CLIFFSSBCCI2011SBMicro2011August 30 - September 2, 2011 João Pessoa, Brazil

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CHIP ON THE CLIFFSSBCCI2011SBMicro2011August 30 - September 2, 2011 João Pessoa, Brazil