Design and Simulation Triple-DES

Simulation onSimulation onTriple Data Encryption Triple Data Encryption

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AdviserAdviserAj. Jarern VongshumyenAj. Jarern Vongshumyen

ByByChatsiri RattanaChatsiri Rattana 47221163 47221163 Woranart HasawayukulWoranart Hasawayukul 47221858 47221858

Agenda

• Introduction

• Theory on Triple DES

• Design on Triple DES

• Testing and Result on Triple DES

• Conclusion

Introduction

Background

• Low security of general data transfer.

• Use encryption system to secure the data communicates.

• Then we choose Triple-DES.

• Apply for design digital circuit by using VHDL(VHSIC Hardware Description Language).

Objective• To learn about Triple-DES(Triple-Data

Encryption Standard) algorithm.

• To learn about VHDL(VHSIC Hardware Description Language) coding.

• Can design an implementable digital circuit of Triple-DES.

• Can simulate a circuit that perform result of encryption and decryption.

Tools for Development

Xilinx Inc.Webpack 8.2i.

ModelSim

Theory on Triple DES

What is DES?

• DES - Data Encryption Standard• Symmetric system - uses the same key to encrypt/decrypt data.

CiphertextPlaintext DES

Key

Key

Encrypt

Decrypt

DES Algorithm Structure

• The algorithm consists of:• An initial permutation of

the input data• Sixteen rounds of the

same process –the DES round

• A final inverse initial permutation of the data

Step 1: Create 16 subkeys, each of which is 48-bits long.

Step 2: Encode each 64-bit block of data

The Feistel (F) function

Mode of 3DES

3DES – EDE (2 keys 3DES)

Keys = 112 bits

C = Ek1(Dk2(Ek1(M)))

3DES-EDE

E D E

k1 k2 k1

Plaintext Ciphertext

D E D

k1 k2 k1

Ciphertext Plaintext

Design on Triple DES

Schematic On Top Module

Coding Entity Top module • entity test_tdestop is• Port ( data_intdes : in std_logic_vector(0 to 63);• key1_intdes : in std_logic_vector(0 to 63); • key2_intdes : in std_logic_vector(0 to 63);• key3_intdes : in std_logic_vector(0 to 63);• clock : in std_logic;• function_selecttdes: in std_logic;• set_out: in std_logic;• lddatatdes : in std_logic;• ldkeytdes : in std_logic;• resettdes : in std_logic;• data_outtdes : out std_logic_vector(0 to 63);• out_readytdes : out std_logic • );

Structure on DESCIPHERTOP

DESCIPHERTOP 1,2,3

KEYSCHEDULE

DES

KEYSCHEDULE

DESTOP

BLOCKTOP

E_EXPANSION FUCNTION

ADDKEY

SBOX

PBOX

ADDLEFT

Device Utilization Summary

Logic Utilizatio

n

Used Available

Utilization

Slices 1398 4656 30 %Slice FF 1140 9312 12%

IOB 305 232 131%GCLKs 1 24 4%

MAX CLK 77.548MHz

Testing and Result on Triple DES

Test by Test Bench and Wave Form • Injection Key 1,2,3 and Data to Triple DES

•Key1<=“DataBit”,Key2<=“DataBit”,Key3<=“DataBit”

• Use Text I/O Read and Write Data to Triple DES write write(out_data_out,data_outtdes); writeline(logdata_out,out_data_out); read readline(read_inputtest,read_inputtest_line); read(read_inputtest_line,input_temp);

• Test Bench not permission injection Output

Strategy for test

Encryption Decryption

Text File Text File

Data

Test Triple DES ( Encryption )

Input

Output

Test of Triple DES ( Decryption )

Input

Output

Conclusion

Conclusion • Can design and simulation circuit .

• Use function for simulation circuit.

• Can Applied Algorithm Triple DES .

• Circuit has delay time and cannot control some gate.

• Can synthesis on FPGA board but it need clock generator and RAM.

• Large IOB must has floorplanning to save spaces that use.