Design and Implementation of VLSI Systems (EN1600) Lecture 17: Design Considerations

S. Reda EN160 SP’08

Design and Implementation of VLSI Systems(EN1600)

Lecture 17: Design Considerations

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2008

[sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’08

Measuring the input capacitance (for lab)

Make sure to extract the parasitic capacitance

First, create your standard cell and extract it to SPICE

S. Reda EN160 SP’08

Creating a subcircuit of your cell

Create a subcircuit out of the extracted files

.global vdd gnd

.subckt inv a y Cpar1 vdd 0 14.40942fCpar2 gnd 0 8.9712fCpar3 y 0 12.0537fM1 y a vdd vdd PMOS L=600n W=3uM2 y a gnd gnd NMOS L=600n W=1.5u.ends

S. Reda EN160 SP’08

Basic idea

a y f

• Delay from a to y depend on the load capacitance of I1 → input capacitance of I2

• If CAP has the same capacitance as I2 then delay from a to c will be equal to delay from a to y

• Objective: try to “guess” CAP to equalize the delay

I1 I2

I3

CAP

c

delay of I1

S. Reda EN160 SP’08

SmartSPICE has a builtin optimizer to save your guessing timeXI1 a y invXI2 y f invXI3 a c invCcin c gnd CAP

Vin a gnd PULSE 0 3.3 100ps 0ps 0ps 2000ps 4200ps

.measure TRAN tdr TRIG v(a) VAL='0.5*3.3' FALL=1 TARG v(y) VAL='0.5*3.3' RISE=1.measure TRAN tdf TRIG v(a) VAL='0.5*3.3' RISE=1 TARG v(y) VAL='0.5*3.3' FALL=1.measure TRAN tdavg PARAM='(tdr+tdf)/2'

.measure TRAN tdrc TRIG v(a) VAL='0.5*3.3' FALL=1 TARG v(c) VAL='0.5*3.3' RISE=1.measure TRAN tdfc TRIG v(a) VAL='0.5*3.3' RISE=1 TARG v(c) VAL='0.5*3.3' FALL=1.measure TRAN tdavgc PARAM='(tdrc+tdfc)/2' goal=tdavg

.model opt1 opt method=bisection

.param CAP=optc(0fF, 0fF, 100fF)

.tran 20ps 3000ps sweep optimize=optc results = tdavgc model=opt1

.end

Optimizer report that the input capacitance = 6.25 fF (which you can easily validate!)

S. Reda EN160 SP’08

Design margins

Sources of variations:

Manufacturing (process variations): L, Vth, tox, interconnect dielectric height, .., etc

Temperature

Supply voltage (IR drop)

threshold voltage 0.97V threshold voltage 0.57V

[source: Asenov’99]

1st CPU 2nd CPU

cache thermal profile during runtime

[source: Devgan’05]

S. Reda EN160 SP’08

Variations can be modeled statistically

S. Reda EN160 SP’08

Process corners

• Process corners describe extreme case variations– If a design works in all corners, it will probably work for any

variation.

• Describe corner with four letters (T, F, S)– nMOS speed– pMOS speed– Voltage– Temperature

S. Reda EN160 SP’08

Design corners check

Purpose nMOS pMOS VDD Temp

Cycle time S S S S

Power F F F F

Subthrehold

leakage

F F F S

S. Reda EN160 SP’08

Simulating corner cases in SPICE

.lib '05corners.lib' typ

.temp 27

.option scale=250n

.option postvdd vdd gnd 3.3Vin a gnd PULSE 0 3.3 100ps 0ps 0ps 2000ps 4200psM1 y a gnd gnd NMOS W=4 L=2 AS=20 PS=18 AD=20 PD=18M2 y a vdd vdd PMOS W=8 L=2 AS=40 PS=26 AD=40 PD=26.tran 1ps 500ps.alter .lib '05corners.lib' fastfast.alter .lib '05corners.lib' slowslow.end