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esign and Implementation of VLSI System (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey Pearson]
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Design and Implementation of VLSI Systems (EN0160) lecture03

Jan 14, 2016

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Design and Implementation of VLSI Systems (EN0160) lecture03. Sherief Reda Division of Engineering, Brown University Spring 2008. [sources: Weste/Addison Wesley – Rabaey Pearson]. Recap. nMOS. pMOS. 3-input NANDs. Series-Parallel Combinations. - PowerPoint PPT Presentation
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Page 1: Design and Implementation of VLSI Systems (EN0160) lecture03

Design and Implementation of VLSI Systems(EN0160)lecture03

Sherief RedaDivision of Engineering, Brown University

Spring 2008

[sources: Weste/Addison Wesley – Rabaey Pearson]

Page 2: Design and Implementation of VLSI Systems (EN0160) lecture03

Recap

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+

SiO2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+

nMOS pMOS

Page 3: Design and Implementation of VLSI Systems (EN0160) lecture03

3-input NANDs

Page 4: Design and Implementation of VLSI Systems (EN0160) lecture03

Series-Parallel Combinations

Page 5: Design and Implementation of VLSI Systems (EN0160) lecture03

What are the transistor schematics of the NOR gate?

Page 6: Design and Implementation of VLSI Systems (EN0160) lecture03

And-Or-Inverter (AOI) gate

Page 7: Design and Implementation of VLSI Systems (EN0160) lecture03

Transmission gate

Page 8: Design and Implementation of VLSI Systems (EN0160) lecture03

Tri-state inverter

Page 9: Design and Implementation of VLSI Systems (EN0160) lecture03

Multiplexer (MUX)

Page 10: Design and Implementation of VLSI Systems (EN0160) lecture03

Latch design

Page 11: Design and Implementation of VLSI Systems (EN0160) lecture03

Flip-flop (edge triggered) design

Page 12: Design and Implementation of VLSI Systems (EN0160) lecture03

Summary

• Introduction to VLSI systems and the semiconductor industry

• Basic overview of pn junctions and MOS transistors

• Designing digital logic gates using transistors

• HW1 is out and the due date is Wednesday February 6