DESIGN AND IMPLEMENTATION OF SQUARE & CUBE ALGORITHM USING VEDIC MATHEMATICS BY PRADEEP.S 1 ST SEM (M.TECH) VLSI & EMBEDDED SYSTEM DEPARTMENT OF ELECTRONICS AND COMMUNICATION SJB INSTITUTE OF TECHNOLOGY KENGERI, BANGALORE-560060 2012-2013 A Project Presentation on UNDER THE GUIDANCE OF Dr. REKHA K.R. PROFESSOR, ECE Dept.
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DESIGN AND IMPLEMENTATION OF SQUARE & CUBE ALGORITHMUSING VEDIC MATHEMATICS
BY PRADEEP.S 1ST SEM (M.TECH) VLSI & EMBEDDED SYSTEM
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
SJB INSTITUTE OF TECHNOLOGY
KENGERI, BANGALORE-560060
2012-2013
A Project Presentation on
UNDER THE GUIDANCE OF
Dr. REKHA K.R.PROFESSOR, ECE Dept.
OVERVIEW
Introduction
Literature survey
Basic Concept
Block diagram of square algorithm and cube algorithm
Experimental result
Conclusion and future scope
References
INTRODUCTION
Multiplication is an important fundamental function in
arithmetic operations.
The process of raising a number to a power i.e.,
exponentiation is an important operation. The
exponentiation operation, like square and cube plays a
vital role in communication systems, signal processing
applications…..
Squaring and cubing can be performed using ordinary multipliers, which are scalable but they have a larger delay.
Structure based array implementation are faster but scalability increases design complexity as well as expense. Moreover, multipliers occupy large area, have long latency and consume considerable power.
Therefore, which offer either of the following design targets- scalability, re-configurability, high speed, low power consumption, regularity of layout and less area or even a combination of some of these features are to be designed.
LITERATURE SURVEY
• There are number of techniques that to perform binary multiplication. In general, the choice is based upon factors such as latency, throughput, area, and design complexity.
• Array Multiplier, Booth Multiplier and Wallace Tree Multipliers are some of the standard approaches to have hardware implementation of binary Multiplier.
Array Multiplier gives more power consumption as
well as the optimum number of components required ,but
delay for this Multiplier is larger .It also requires large
number of gates because of which area is increased ;due to
this array Multiplier is less economical .Thus ,it is a fast
Multiplier but hardware complexity is high.
In the Wallace tree Multiplier ,the circuit layout is not
easy although the speed of the operation is high
PROBLEM FORMULATION The problems that are to be handled in this present work is1. To reduce area and delay.2. To minimize power consumption.3. To design a Multiplier with regular in structure. OBJECTIVE The main objective of this work is to implement an Arithmetic unit which makes use of Vedic Mathematics algorithm for multiplication. The Arithmetic unit that has been made performs multiplication, addition, subtraction and Multiply Accumulate operations. The MAC unit, used in the Arithmetic module uses a fast multiplier, built with Vedic Mathematics Algorithm. Also, square and cube algorithms of Vedic Mathematics, to reduce the multiplications required
Reducing the time delay and power consumption are very essential requirements for many applications.
Multiplier based on Vedic Mathematics is one of the fast and low power multiplier.
In the present work we are using the Vedic sutras to compute the square and cube of the input number.
To compute square we have made use of the Duplex property of Urdhava Triyakbyam Sutra.
To find the cube of the number Anurupya Sutra of Vedic mathematics is used.
This approach of obtaining the square and cube of a number is fast and it is easy and simple to implement.
VEDIC SUTRAS
Vedic mathematics is mainly based on the 16 sutras