Design and Development of an ADC/DAC Evaluation Board for ... · the ADC/DAC board is described here. Figure 1: Conceptual board-level overview. Figure 2 shows the completed ADC/DAC

Design and Development of an ADC/DAC Evaluation

Board for NIJ Public Safety Radio

S.M. Shajedul Hasan∗ and S.W. Ellingson

November 20, 2007

Contents

1 Introduction 2

2 ADC/DAC Board Overview 2

3 Description of the ADC Section 4

4 Description of the DAC Section 5

5 Description of the Power Supply Section 5

6 Description of the Settings 6

7 Summary 6

A Pin List 10A.1 ADC Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10A.2 DAC Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

B Bill of Materials 12

C Schematic 15

D Layout 19

∗Bradley Dept. of Electrical & Computer Engineering, 432 Durham Hall, Virginia Polytechnic Institute& State University, Blacksburg, VA 24061 USA. E-mail: [email protected]

1

1 Introduction

An experimental multi-band/multi-mode radio for public safety applications is being devel-oped in Virginia Tech under a project sponsored by the U.S. Department of Justice [1]. Thegoal of this project is to develop and demonstrate a single radio which can operate in allthe public safety frequency bands presented in [2, 3]. To provide context, Figure 1 shows aconceptual “board-level” overview of a prototype of the proposed radio, consisting of multi-plexer boards, RFIC transceiver board, ADC/DAC board and baseband processing board.The description of RFIC board is already presented in [4]. The design and development ofthe ADC/DAC board is described here.

Rx/Tx Boardwith

Motorola RFIC

Board Level Plan of Public Safety Radio

RxMultiplexerBoard

Tx MultiplexerBoard

ADC/DACBoard

SPI

Rx

Tx

I

Q

I

Q

BasebandProcessing

FPGA Board

Figure 1: Conceptual board-level overview.

Figure 2 shows the completed ADC/DAC board.

This report is organized as follows. Section 2 presents the summary of the input/outputports of ADC/DAC board. Section 3 and 4 describe the circuit topology for the ADC andDAC section respectively. Section 5 presents the circuit description of the power supply andSection 6 describes the various jumper settings. Section 7 concludes the report presenting thetotal cost. Finally, four appendices present the pin list of ADC and DAC, bill of materials,complete schematic and layout images.

2 ADC/DAC Board Overview

Figure 3 and Table 1 present all the input/output ports of the ADC/DAC board.

2

NIJ Communications Technologies Principal Investigator MeetingA PROGRAM OF THE NATIONAL INSTITUTE OF JUSTICE

Multiband/Multimode RadioEllingson – Oct 24, 2007

ADC / DAC• ADC: Analog Devices AD9248

2 Ch (i.e., I/Q), 14b, 20 MSPSSample clock sourced by system FPGA; variable over 1-20 MSPS

• DAC: Analog Devices AD97612 Ch (i.e., I/Q), 10b, 40 MSPSSynchronous with ADCMay upgrade to at least 12 bits

130 mA @ 9V, running 4 MSPS< 50 cm2 to implement on a 4-layer PCBADC ~ $21 (1k), DAC ~ $10 (1k)

Figure 2: Image of ADC/DAC board.

ADC/DAC Board

Rx/Tx Board Overview

IB

DAC Output

ADC Input

ADI Interface to

FPGA Board

EXT_CLK_DAC

CLK_ADC

IA

QB

QA

IA

IB

QB

QA

Figure 3: Summary of ADC/DAC board.

3

Function Port Name Conn. Name CharacteristicsDAC Output IB J19 Differential Output

IA J18 of I-ChannelQB J16 Differential OutputQA J17 of Q-Channel

ADC Input IA J2 Differential InputIB J3 of I-ChannelQB J4 Differential InputQA J5 of Q-Channel

CLK ADC Input CLK ADC J6 ADC Reference ClockCLK DAC Input EXT CLK J15 External DAC ClockADI Interface ADI J1, J12 ADI interface to FPGA

Table 1: Input/Output ports of the ADC/DAC board.

3 Description of the ADC Section

AD9248 dual 14-bit A/D converter from Analog Devices has been selected to convert theanalog signal to digital signal in our design to operate the receiver section [5]. The differentialin-phase (I) and quadrature-phase (Q) inputs are supplied to the input ports of the ADCs.Multiplexed data output option enables to get the multiplexed digitized I and Q signalsfrom the Data Port B. One single external clock is used to supply the reference clock forboth of the A/D converters in this IC. The output of the Data Port B is connected to a40-pin connector (J1) through a couple of octal bus buffer ICs (74VHC541) and some 22 ohmresistor pads. The unused output Data Port A is terminated with some 22 ohm resistors andconnected to a 40-pin header connector (J11). Figure 4 shows the circuit diagram examplefor the differential input of the ADC. Detailed circuit diagrams of the ADC section can befound in the “ADC/DAC Board/ADC Circuits” sheet in Appendix C.

Figure 4: ADC input circuit diagram (the unconnected lines in the figure go to the VIN+ Aand VIN- A pins).

4

4 Description of the DAC Section

AD9761 dual 10-bit D/A converter from Analog Devices has been selected to convert thedigital signal to analog signal in our design for the transmission operation [6]. Similar tothe ADC section, the DAC provides the differential in-phase (I) and quadrature-phase (Q)analog output signals from the digital interleaved I and Q input signal. One single externalclock is used to supply the reference clock for the D/A converters in this IC. The input ofthe Data Port is connected to a 40-pin connector (J12) through some 22 ohm resistor pads.Figure 5 shows the circuit diagram example for the differential output of the DAC. Detailedcircuit diagrams of the DAC section can be found in the “ADC/DAC Board/DAC Circuits”sheet in Appendix C.

Figure 5: DAC output circuit diagram (the unconnected lines in the figure go to the IA andIB pins).

5 Description of the Power Supply Section

Three separate 3V supply voltages and one 2.5V supply voltage for ADC, and two separate5V supply voltages for DAC have been created from a single 10V power source. First, themain 10V input voltage is fed into a 3A low dropout regulator IC LT1529 to create a 5Vpositive voltage. This 5V voltage is supplied to the input of the four low dropout regulatorICs ADP3339, which provides the required output voltage of 3V and 2.5V. Two positive volt-age regulator ICs MC78M05 generate the 5V supply voltages for the DAC directly from the10V power supply. Fig. 6 shows the circuit diagram example for the power supply. Detailedcircuit diagrams for all other power supply pins can be found in “ADC/DAC Board/PowerSupply Circuits” sheet in Appendix C.

5

Figure 6: Power supply section circuit diagram (the unconnected lines in the right hand sideof the figure go to the “MC78M05” ICs and “ADP3339” ICs to generate the supply voltagesfor ADC and DAC respectively).

6 Description of the Settings

Table 2 shows the jumper settings of the PCB.

Jumper Description Normal Setting CommentJ21 Power In 3V supply to ADCJ22 Power In 2.5V supply to ADCJ23 Power In 3V supply to ADCJ24 Power In 3V supply to ADCJ25 Power In 5V supply to DACJ26 Power In 5V supply to DACJ8 Mux Select Out Connect MUX SEL pin to ClockJ9 Mux Select Out Connect MUX SEL pin to VDDJ10 Mux Select In Connect MUX SEL pin to GNDJ7 Clock Polarity A Position B select the opposit polarityJ14 DAC Clock Select A ‘A’ selects the ADI clock and ‘B’ selects the

external clock

Table 2: PCB Jumper Settings.

7 Summary

A summary of the cost for one ADC/DAC board is given in Table 3. Since we prepared justtwo boards for the present study using the quickest manufacturing time, the PCB fabricationand assembly cost is not representative of the cost to build the same device in large quantities.

6

Component Quantity Price(US $)ADC & DAC ICs 2 43.20Other ICs 10 26.00Capacitor 68 5.00Inductor 4 1.00Resistor 41 4.00MMCX Connector 10 60.30Other Connectors 16 23.50Other Components 17 3.50

Subtotal 166.50PC Board 1 450.00PC Board Assembly 1 925.00

Total 1541.50

Table 3: Summary of the cost for one ADC/DAC board.

7

References

[1] NIJ project web site, http://www.ece.vt.edu/swe/chamrad/.

[2] S. W. Ellingson, “Phase I Technical Report,” Virginia Tech, VA, Tech. Rep. 15, Oct.2006. [Online]. Available: http://www.ece.vt.edu/swe/chamrad/.

[3] S. W. Ellingson, S.M. Hasan, M. Harun, and C.R. Anderson, “Phase II Tech-nical Report,” Virginia Tech, VA, Tech. Rep. 23, Oct. 2007. [Online]. Available:http://www.ece.vt.edu/swe/chamrad/.

[4] S.M. Hasan and S.W. Ellingson, “Design and Development of an Evaluation Boardwith RFIC Ver. 4,” Virginia Tech, VA, Tech. Rep. 22, Sep. 2007. [Online]. Available:http://www.ece.vt.edu/swe/chamrad/.

[5] Datasheet of AD9248 Dual 14-bit Analog-to-Digital Converter, Rev. A, Mar. 2005. [On-line]. Available: http://www.analog.com/UploadedFiles/Data Sheets/AD9248.pdf.

[6] Datasheet of AD9761 10-bit Dual Transmit D/A Converter, Rev. C, Jun. 2005. [Online].Available: http://www.analog.com/UploadedFiles/Data Sheets/AD9761.pdf.

8

Appendices

9

A Pin List

This section presents the pin description of the ADC and DAC ICs.

A.1 ADC Pin List

Fig. 7 shows the pin function of AD9248 ADC.

AD9248

Rev. A | Page 10 of 48

Table 6. Pin Function Descriptions (64-Lead LQFP and 64-Lead LFCSP) Pin No. Mnemonic Description 1, 4, 13, 16 AGND Analog Ground. 2 VIN+_A Analog Input Pin (+) for Channel A. 3 VIN−_A Analog Input Pin (−) for Channel A. 5, 12, 17, 64 AVDD Analog Power Supply. 6 REFT_A Differential Reference (+) for Channel A. 7 REFB_A Differential Reference (−) for Channel A. 8 VREF Voltage Reference Input/Output. 9 SENSE Reference Mode Selection. 10 REFB_B Differential Reference (−) for Channel B. 11 REFT_B Differential Reference (+) for Channel B. 14 VIN−_B Analog Input Pin (−) for Channel B. 15 VIN+_B Analog Input Pin (+) for Channel B. 18 CLK_B Clock Input Pin for Channel B. 19 DCS Enable Duty Cycle Stabilizer (DCS) Mode. 20 DFS Data Output Format Select Pin (Low for Offset Binary, High for Twos Complement). 21 PDWN_B Power-Down Function Selection for Channel B.

Logic 0 enables Channel B. Logic 1 powers down Channel B (outputs static, not High-Z). 22 OEB_B Output Enable Pin for Channel B.

Logic 0 enables Data Bus B. Logic 1 sets outputs to High-Z. 23 to 27, 30 to 38

D0_B (LSB) to D13_B (MSB)

Channel B Data Output Bits.

28, 40, 53 DRGND Digital Output Ground. 29, 41, 52 DRVDD Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor.

Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF capacitor. 39 OTR_B Out-of-Range Indicator for Channel B. 42 to 51, 54 to 57

D0_A (LSB) to D13_A (MSB)

Channel A Data Output Bits.

58 OTR_A Out-of-Range Indicator for Channel A. 59 OEB_A Output Enable Pin for Channel A.

Logic 0 enables Data Bus A. Logic 1 sets outputs to High-Z. 60 PDWN_A Power-Down Function Selection for Channel A

Logic 0 enables Channel A. Logic 1 powers down Channel A (outputs static, not High-Z). 61 MUX_SELECT Data Multiplexed Mode.

(See Data Format section for how to enable; high setting disables output data multiplexed mode.) 62 SHARED_REF Shared Reference Control Pin (Low for Independent Reference Mode, High for Shared Reference Mode). 63 CLK_A Clock Input Pin for Channel A.

Figure 7: ADC Pin List [5].

A.2 DAC Pin List

Fig. 8 shows the pin function of AD9761 DAC.

10

AD9761

–6–

AD9761

–7–

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 DB9 Most Significant Data Bit (MSB).

2–9 DB8–DB1 Data Bits 1–8.

10 DB0 Least Significant Data Bit (LSB).

11 CLOCK Clock Input. Both DACs’ outputs updated on positive edge of clock and digital filters read respective input registers.

12 WRITE Write Input. DAC input registers latched on positive edge of write.

13 SELECT Select Input. Select high routes input data to I DAC; select low routes data to Q DAC.

14 DVDD Digital Supply Voltage (2.7 V to 5.5 V).

15 DCOM Digital Common.

16 COMP3 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.

17 QOUTA Q DAC Current Output. Full-scale current when all data bits are 1s.

18 QOUTB Q DAC Complementary Current Output. Full-scale current when all data bits are 0s.

19 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.

20 REFIO Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.2 V reference output when internal reference activated. Requires 0.1 µF capacitor to ACOM when internal reference activated.

21 FSADJ Full-Scale Current Output Adjust. Resistance to ACOM sets full-scale output current.

22 COMP2 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.

23 AVDD Analog Supply Voltage (3 V to 5.5 V).

24 ACOM Analog Common.

25 IOUTB I DAC Complementary Current Output. Full-scale current when all data bits are 0s.

26 IOUTA I DAC Current Output. Full-scale current when all data bits are 1s.

27 COMP1 Internal Bias Node for Switch Driver Circuitry. Decouple to AGND with 0.1 µF capacitor.

28 RESET/SLEEP Power-Down Control Input if Asserted for Four Clock Cycles or Longer. Reset control input if asserted for less than four clock cycles. Active high. Connect to DCOM if not used. Refer to RESET/ SLEEP Mode Operation section.

PIN CONFIGURATION

14

13

12

11

17

16

15

20

19

18

10

9

8

1

2

3

4

7

6

5

TOP VIEW(Not to Scale)

28

27

26

25

24

23

22

21

AD9761

(MSB) DB9

IOUTB

IOUTA

COMP1

RESET/SLEEP

DB8

DB7

DB6

COMP2

AVDD

ACOMDB5

DB4

DB3

DB2

DB1

(LSB) DB0 REFLO

REFIO

FSADJ

CLOCK

WRITE

SELECT

DVDD

QOUTB

DCOM

COMP3

QOUTA

REV. C REV. C

Figure 8: DAC Pin List [6].

11

B Bill of Materials

This section presents the bill of materials.

12

Bill of Materials

NIJ ADC_DAC Board, Ver. 1.0

MPRG/Virginia Tech

Prepared By: S.M. Hasan, Date: OCT 01, 2007

Item Qty Reference Part Name Package Manufacturer Manufacturer Part# Distributor Distributor Part# Description

1 2 U2-3 74VHC541 20-SOL TOSHIBA TC74VHC541FW Digikey TC74VHC541FW-ND OCTAL BUS BUFFER

2 1 U4 74VHC04MTC 14-TSSOPFAIRCHILD

SEMICONDUCTOR74VHC04MTC Digikey 74VHC04MTC-ND HEX INVERTER

3 1 U8 AD3339,2.5V SOT-223 Analog Devices ADP3339AKCZ-2.5-R7 Digikey ADP3339AKCZ-2.5-R7CT-ND Low Dropout Regulator

4 3 U7 U9-10 AD3339,3V SOT-223 Analog Devices ADP3339AKCZ-3-RL7 Digikey ADP3339AKCZ-3-RL7CT-ND Low Dropout Regulator

5 1 U1 AD9248 64-LQFP Analog Devices AD9248BSTZ-20 Digikey AD9248BSTZ-20-ND14-Bit Dual A/D

Converter

6 1 U5 AD9761 28-SSOP ANALOG DEVICES AD9761ARSZ Digikey AD9761ARSZ-ND DUAL 10-BIT DAC

7 7C7 C9 C12 C14 C16 C18

C210.001uF CAP_0603 Panasonic-ECG ECJ-1VB1H102K Digikey PCC1772CT-ND

SURFACE MOUNT

CAPACITOR 0603 Size

8 19

C8 C10-11 C13 C17 C19-

20 C25-27 C29-31 C33

C37-38 C41-42 C45

0.1uF CAP_0603 Murata Electronics GRM188R71H104KA93D Digikey 490-1519-1-NDSURFACE MOUNT

CAPACITOR 0603 Size

9 1 C36 1uF CAP_0603 Panasonic-ECG ECJ-1VB1C105K Digikey PCC2224CT-NDSURFACE MOUNT

CAPACITOR 0603 Size

10 6 C23-24 C39-40 C43-44 20pF CAP_0603 Murata Electronics GRM1885C2A200JA01D Digikey 490-1334-1-NDSURFACE MOUNT

CAPACITOR 0603 Size

11 5 C3-6 C35 0.1uF CAP_0805 Kemet C0805C104K5RACTU Digikey 399-1170-1-NDSURFACE MOUNT

CAPACITOR 0805 Size

12 4 C63 C65-66 C68 0.1uF CAP_1206 Kemet C1206C104K5RACTU Digikey 399-1249-1-NDSURFACE MOUNT

CAPACITOR 1206 Size

13 21C1-2 C15 C22 C28 C32

C34 C46-47 C49-6010uF 16V CAP_3216 Rohm TCA1C106M8R Digikey 511-1473-1-ND CAP TANTALUM

14 5 C48 C61-62 C64 C67 22uF 10V CAP_3216 Rohm TCA1A226M8R Digikey 511-1465-1-ND CAP TANTALUM

15 9 J8-10 J21-26CONN_DUAL_HDR

_2PINStraight Header Tyco Electronics 1-87215-0 Digikey A26564-ND 2-Pin Dual Header

16 2 J7 J14CONN_HEADER_3

PINStraight Header Tyco Electronics 87220-3 Digikey A26544-ND

3-pin Single Row 0.100

Header

17 1 J13CONN_SINGLEHEA

DER_4PINStraight Header Tyco Electronics 87220-4 Digikey A26546-ND 4-Pin Single Row Header

18 2 J1 J12 DUAL_HEADER_40 Female Header Sullins Electronics PPPC202LFBN-RC Digikey S7123-ND Header Female

Item Qty Reference Part Name Package Manufacturer Manufacturer Part# Distributor Distributor Part# Description

19 1 R15 Pot 10K SMT PANASONIC EVN-5ESX50B14 Digikey P5E103CT-NDTRIMMER

POTENTIOMETER

20 1 D1 LED, Green SMT LITE-ON LTST-C190GKT Digikey 160-1183-1-ND LIGHT EMITTING DIODE

21 4 L1-4 10uH L-1210 Panasonic-ECG ELJ-FA100JF Digikey PCD1817CT-NDSurface Mount Inductor

1210 Size

22 2 U11-12 MC78M05 TO-252 ON SEMICONDUCTOR MC78M05BDTRKG Digikey MC78M05BDTRKGOSCT-ND500mA POSITIVE

VOLTAGE REGULATORS

23 10 J2-6 J15-19 MMCX_CONN MMCX Amphenol Connex 262104 Digikey ACX1275-ND MMCX CONNECTOR

24 2 R36 R40 100 1/10W RES-0603 Panasonic-ECG ERJ-3GEYJ101V Digikey P100GCT-NDSURFACE MOUNT

RESISTOR 0603 Size

25 1 R37 2K 1/10W RES-0603 Panasonic-ECG ERJ-3GEYJ202V Digikey P2.0KGCT-NDSURFACE MOUNT

RESISTOR 0603 Size

26 1 R41 392 1/10W RES-0603 Panasonic-ECG ERJ-3EKF3920V Digikey P392HCT-NDSURFACE MOUNT

RESISTOR 0603 Size

27 5 R31 R34-35 R38-39 49.9 1/10W RES-0603 Panasonic-ECG ERJ-3EKF49R9V Digikey P49.9HCT-NDSURFACE MOUNT

RESISTOR 0603 Size

28 1 R5 22 1/8W RES-0805 Panasonic-ECG ERJ-6GEYJ220V Digikey P22ACT-NDSURFACE MOUNT

RESISTOR 0805 Size

29 2 R11-12 499 1/8W RES-0805 Panasonic-ECG ERJ-6ENF4990V Digikey P499CCT-NDSURFACE MOUNT

RESISTOR 0805 Size

30 7 R16-22 4.99K 1/8W RES-0805 Panasonic-ECG ERJ-6ENF4991V Digikey P4.99KCCT-NDSURFACE MOUNT

RESISTOR 0805 Size

31 1 R13 0 1/4W RES-1206 Panasonic-ECG ERJ-8GEY0R00V Digikey P0.0ECT-NDSURFACE MOUNT

RESISTOR 1206 Size

32 5 R6-9 R14 33 1/4W RES-1206 Panasonic-ECG ERJ-8GEYJ330V Digikey P33ECT-NDSURFACE MOUNT

RESISTOR 1206 Size

33 1 R10 49.9 1/4W RES-1206 Panasonic-ECG ERJ-8ENF49R9V Digikey P49.9FCT-NDSURFACE MOUNT

RESISTOR 1206 Size

34 6 R25-26 R29-30 R32-33RES_PAK_8_0402,

10KRES-0402 CTS 741X163103JP Digikey 741X163103JPCT-ND RESISTOR PAK 8- 0402

35 8 R1-4 R23-24 R27-28RES_PAK_8_0402,

22 ohmRES-0402 CTS 741X163220JP Digikey 741X163220JPCT-ND RESISTOR PAK 8- 0402

36 1 E1 SM_BEADS_DIFF SMTFAIR-RITE PRODUCTS

CORP2743019447 Mouser 623-2743019447LF SM BEADS DIFFERENTIAL

37 1 J20TERMINAL_BLOCK

_2PINThrough Hole PHOENIX CONTACT 1729018 Digikey 277-1236-ND 2-PIN TERMINAL BLOCK

38 1 U6 VREG_LT1529 DD-PAK Linear Technology LT1529CQ-5#PBF Digikey LT1529CQ-5#PBF-ND Linear Regulator

39 1 J11 DUAL_HEADER_40 Male Header Sullins Electronics PBC20DFAN Digikey S2211E-20-ND Header Male

C Schematic

This section presents the schematic of the RFIC board. This schematic contains the followingthree pages-

• ADC Circuits

• DAC Circuits

• Power Supply Circuits

15

D Layout

This section presents the layout and component placement of the ADC/DAC board. Thepages are added in the following order -

• Top layer (primary component side)

• Bottom layer (secondary component side)

• First inner layer (power layer)

• Second inner layer (ground layer)

• Component placement in top layer, and

• Component placement in bottom layer.

19