DEMODULATOR QPSK (QUADRATURE PHASE SHIFT KEYING) TUGAS AKHIR Diajukan Untuk Memenuhi Salah Satu Syarat Memperoleh Gelar Sarjana Teknik pada Program Studi Teknik Elektro Fakultas Sains dan Teknologi Disusun Oleh: Yohana Febrianti Sumardi NIM : 035114017 PROGRAM STUDI TEKNIK ELEKTRO JURUSAN TEKNIK ELEKTRO FAKULTAS SAINS DAN TEKNOLOGI UNIVERSITAS SANATA DHARMA YOGYAKARTA 2008 i
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DEMODULATOR QPSK
(QUADRATURE PHASE SHIFT KEYING)
TUGAS AKHIR
Diajukan Untuk Memenuhi Salah Satu Syarat
Memperoleh Gelar Sarjana Teknik pada
Program Studi Teknik Elektro
Fakultas Sains dan Teknologi
Disusun Oleh:
Yohana Febrianti Sumardi
NIM : 035114017
PROGRAM STUDI TEKNIK ELEKTRO
JURUSAN TEKNIK ELEKTRO
FAKULTAS SAINS DAN TEKNOLOGI
UNIVERSITAS SANATA DHARMA
YOGYAKARTA
2008
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QPSK DEMODULATOR
FINAL PROJECT
Presented as Partial Fulfillment of the Requirements
To Obtain the Sarjana Teknik Degree
In Electrical Engineering Study Program
By:
Yohana Febrianti Sumardi
Student Number : 035114017
ELECTRICAL ENGINEERING STUDY PROGRAM
SCIENCE AND TECHNOLOGY FACULTY
SANATA DHARMA UNIVERSITY
YOGYAKARTA
2008
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HALAMAN PENGESAHAN
TUGAS AKHIR
DEMODULATOR QPSK
(QUADRATURE PHASED SHIFT KEYING) Disusun Oleh :
YOHANA FEBRIANTI SUMARDI NIM : 035114017
Telah dipertahankan di depan Panitia Penguji
Pada tanggal : 8 Maret 2008
dan dinyatakan memenuhi syarat
Susunan Panitia Penguji
Nama Lengkap Tanda Tangan
Ketua : Martanto, S.T., M.T. ...................................
Anggota : A. Bayu Primawan, S.T., M.Eng. ...................................
Anggota : Pius Yozy Merucahyo, S.T., M.T. ...................................
Yogyakarta, .................................... Fakultas Sains dan Teknologi
Universitas Sanata Dharma Dekan
Ir. Greg. Heliarko, S.J., S.S.,B.S.T., M.A., M. Sc.
iv
LEMBAR PERNYATAAN KEASLIAN KARYA
Saya menyatakan dengan sesungguhnya bahwa yang saya tulis ini tidak memuat
karya atau bagian karya orang lain, kecuali yang telah disebutkan dalam kutipan
dan daftar pustaka, sebagaimana layaknya karya ilmiah.
Yogyakarta, 22 Februari 2008
Penulis
Yohana Febrianti Sumardi
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Percayalah kepada TUHAN dengan segenap hatimu, dan janganlah bersandar kepada pengertianmu sendiri (Amsal 3:5)
Orang yang tidak mau mendengarkan kritik Tidak akan pernah belajar darinya
Ketika seorang sahabat melukai kita, kita harus menulisnya di atas pasir agar angin maaf datang
dan menghapus tulisan itu. Dan bila sesuatu yang luar biasa baik terjadi, kita harus memahatnya di atas batu hati kita, agar takkan pernah
bisa hilang tertiup angin.
vi
Tugas akhir ini kupersembahkan untuk: Tuhan Yesus atas kasih-Nya
Kedua orang tuaku tercinta (Bpk.Sumardi & Ibu Ninik Sri Lestari)
Kakaku tersayang (Danang Indra Sumardi) yang selalu memberikan cinta, doa,
dorongan dan nasehat.
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DEMODULATOR QPSK
INTISARI
QPSK merupakan salah satu teknik modulasi yang dapat digunakan untuk IDR dan VSAT pada komunikasi satelit, modem ISDN, serta telepon seluler. Demodulasi QPSK merupakan proses mengkodekan kembali sinyal analog yang memiliki empat keadaan fasa yang berbeda menjadi dua bit data digital pada masing-masing keadaannya. Keunggulan QPSK adalah efisiensi bandwidth dan lebih tahan terhadap interferensi yang disebabkan oleh perubahan amplitudo. Dengan banyaknya manfaat QPSK, maka perlu dibuat suatu modul sebagai alat bantu belajar.
Demodulator QPSK ini terdiri dari BPF untuk menyaring frekuensi tertentu yang berasal dari modulator QPSK, Carrier Recovery untuk menghasilkan sinyal pembawa, Product Detector untuk mengalikan sinyal termodulasi dan sinyal pembawa, LPF, Komparator, Bit-timing recovery untuk mengasilkan clock, dan register PISO untuk mengubah data paralel menjadi data serial. Demodulator QPSK yang dibuat dapat mengkodekan kembali sinyal informasi dari modulator QPSK jika mengunakan sinyal pembawa dari modulator. Tetapi tidak demikian jika digunakan sinyal pembawa dari Carrier Recovery.
Kata kunci : demodulator QPSK, modulasi fasa.
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QPSK DEMODULATOR
ABSTRACT
QPSK is one of the modulation technique that is used for IDR and VSAT in satellite communication, ISDN modem, and cell phone. QPSK demodulation is an encoding process of analog signal that have four different phase resulting two bit digital data on each phase. The benefit of QPSK is bandwidth efficiency and more robust from interference signal that is caused by amplitude changing. With the benefit of the QPSK modulation, so a practicum module is important to be made.
QPSK demodulator that has been made consist of BPF to filter a certain frequency from QPSK modulator, Carrier Recovery to produce carrier signal, Product Detector to multiply between modulated signal and carrier signal, LPF, Comparator, Bit-timing recovery to produce clock signal for PISO register, and PISO register to change parallel data to serial data. QPSK demodulator that has been made can encode the information signal from QPSK modulator if use carrier signal from modulator. But if use carrier signal from Carrier Recovery, demodulator QPSK cannot encode the information signal. Key word: QPSK demodulator, phase modulation.
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KATA PENGANTAR
Puji dan syukur penulis panjatkan ke Hadirat Tuhan Yang Maha Esa yang
telah melimpahkan rahmat dan karunia-Nya sehingga penulis dapat
menyelesaikan Tugas Akhir yang berjudul. “Demodulatror QPSK ”. Tugas
Akhir ini disusun sebagai salah satu syarat untuk memperoleh gelar Sarjana
Teknik. Dalam penyusunannya, banyak pihak yang telah membantu memberikan
dukungan dan dorongan pada penulis, oleh karena itu, penulis ingin mengucapkan
terima kasih kepada :
1. Bapak Damar Widjaja, ST., MT., yang telah bersedia meluangkan
waktu untuk membimbing penulis.
2. Bapak Martanto, ST.,MT., yang telah bersedia meluangkan waktu dan
kesabaran dalam membimbing. Terima kasih pula untuk seluruh
dosen-dosenku di Fakultas Teknik atas segala ilmu yang berguna
3. Papa, Mama, Yang Ti, Mbah putri di Kartasura, serta kakakku
Danang. Terima kasih atas segalanya. Thanx for you’re love…
4. Untuk Tante Yekti, Om Budi, Titin, terima kasih atas tumpangan
hidupnya selama di Yogya.
5. Untuk Ntong, terima kasih atas kebersamaan kita, susah ,senang, dan
belajar untuk hidup sabar.
6. Sahabat-sahabatku Inggit Suminggit, Amoh alias Gigih , Cik Mer,
Kiwil alias Suryo menggolo, Kokop alias Jakop, Gendut alias Alex,
Angga, Jeffry, Win, Cecep, Adit, terima kasih atas segala kebersamaan
kita yang selalu penuh dengan canda tawa.
7. Teman-teman di Purwokerto Mekar, Pitha, Ethink, Vevi, Veni, Novi,
dan Yaya, terima kasih support-nya I love you all.
xi
8. Untuk mas Sur, mas Mardi, mas Broto, terima kasih atas segala
bantuannya di Laboratorium dan kesabarannya.
9. Semua teman-teman Teknik Elektro angkatan 2003 mari kita berkarya
bersama.
10. Teman-teman di PMK Apostolos, mari kita bertumbuh bersama.
Penulis menyadari bahwa laporan Tugas Akhir ini masih jauh dari sempurna,
oleh karena itu penulis sangat mengharapkan saran dan kritik yang membangun
dari Pembaca agar dalam proses penulisan di kemudian hari dapat semakin
baik. Semoga Tugas Akhir ini dapat bermanfaat secara luas, baik bagi penulis
Lampiran 1. Gambar Rangkaian keseluruhan Demodulator QPSK
Lampiran 2. Tunda Modulator Demodulator QPSK
Lampiran 3 Tunda tiap sistem modulator-demodulator QPSK
Gambar 1
Gambar 2
Gambar 3
Gambar 4
Gambar 5
Gambar 6
Gambar 7
Gambar 8
Gambar 9
Gambar 10
Lampiran 4. Rangkaian Product Detector
Menggunakan MC1496
LF353Wide Bandwidth Dual JFET Input Operational AmplifierGeneral DescriptionThese devices are low cost, high speed, dual JFET inputoperational amplifiers with an internally trimmed input offsetvoltage (BI-FET II™ technology). They require low supplycurrent yet maintain a large gain bandwidth product and fastslew rate. In addition, well matched high voltage JFET inputdevices provide very low input bias and offset currents. TheLF353 is pin compatible with the standard LM1558 allowingdesigners to immediately upgrade the overall performance ofexisting LM1558 and LM358 designs.
These amplifiers may be used in applications such as highspeed integrators, fast D/A converters, sample and holdcircuits and many other circuits requiring low input offsetvoltage, low input bias current, high input impedance, highslew rate and wide bandwidth. The devices also exhibit lownoise and offset voltage drift.
Featuresn Internally trimmed offset voltage: 10 mVn Low input bias current: 50pAn Low input noise voltage: 25 nV/√Hzn Low input noise current: 0.01 pA/√Hzn Wide gain bandwidth: 4 MHzn High slew rate: 13 V/µsn Low supply current: 3.6 mAn High input impedance: 1012Ωn Low total harmonic distortion : ≤0.02%n Low 1/f noise corner: 50 Hzn Fast settling time to 0.01%: 2 µs
Typical Connection
00564914
Simplified Schematic1/2 Dual
00564916
Connection DiagramDual-In-Line Package
00564917
Top ViewOrder Number LF353M, LF353MX or LF353N
See NS Package Number M08A or N08E
BI-FET II™ is a trademark of National Semiconductor Corporation.
If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage ±18V
Power Dissipation (Note 2)
Operating Temperature Range 0˚C to +70˚C
Tj(MAX) 150˚C
Differential Input Voltage ±30V
Input Voltage Range (Note 3) ±15V
Output Short Circuit Duration Continuous
Storage Temperature Range −65˚C to +150˚C
Lead Temp. (Soldering, 10 sec.) 260˚C
Soldering InformationDual-In-Line Package
Soldering (10 sec.) 260˚C
Small Outline Package
Vapor Phase (60 sec.) 215˚C
Infrared (15 sec.) 220˚C
See AN-450 “Surface Mounting Methods and Their Effecton Product Reliability” for other methods of solderingsurface mount devices.
ESD Tolerance (Note 8) 1000V
θJA M Package TBD
Note 1: Absolute Maximum Ratings indicate limits beyond which damage tothe device may occur. Operating ratings indicate conditions for which thedevice is functional, but do not guarantee specific performance limits. Elec-trical Characteristics state DC and AC electrical specifications under particu-lar test conditions which guarantee specific performance limits. This assumesthat the device is within the Operating Ratings. Specifications are not guar-anteed for parameters where no limit is given, however, the typical value is agood indication of device performance.
DC Electrical Characteristics(Note 5)
Symbol Parameter Conditions LF353 Units
MIn Typ Max
VOS Input Offset Voltage RS=10kΩ, TA=25˚C 5 10 mV
Over Temperature 13 mV
∆VOS/∆T Average TC of Input Offset Voltage RS=10 kΩ 10 µV/˚C
IOS Input Offset Current Tj=25˚C, (Notes 5, 6) 25 100 pA
Tj≤70˚C 4 nA
IB Input Bias Current Tj=25˚C, (Notes 5, 6) 50 200 pA
Tj≤70˚C 8 nA
RIN Input Resistance Tj=25˚C 1012 ΩAVOL Large Signal Voltage Gain VS=±15V, TA=25˚C 25 100 V/mV
VO=±10V, RL=2 kΩOver Temperature 15 V/mV
VO Output Voltage Swing VS=±15V, RL=10kΩ ±12 ±13.5 V
VCM Input Common-Mode Voltage VS=±15V ±11 +15 V
Range −12 V
CMRR Common-Mode Rejection Ratio RS≤ 10kΩ 70 100 dB
PSRR Supply Voltage Rejection Ratio (Note 7) 70 100 dB
IS Supply Current 3.6 6.5 mA
AC Electrical Characteristics(Note 5)
Symbol Parameter Conditions LF353 Units
Min Typ Max
Amplifier to Amplifier Coupling TA=25˚C, f=1 Hz−20 kHz −120 dB
(Input Referred)
SR Slew Rate VS=±15V, TA=25˚C 8.0 13 V/µs
GBW Gain Bandwidth Product VS=±15V, TA=25˚C 2.7 4 MHz
en Equivalent Input Noise Voltage TA=25˚C, RS=100Ω, 16
f=1000 Hz
in Equivalent Input Noise Current Tj=25˚C, f=1000 Hz 0.01
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AC Electrical Characteristics (Continued)(Note 5)
Symbol Parameter Conditions LF353 Units
Min Typ Max
THD Total Harmonic Distortion AV=+10, RL=10k,VO=20Vp−p,BW=20 Hz-20 kHz
<0.02 %
Note 2: For operating at elevated temperatures, the device must be derated based on a thermal resistance of 115˚C/W typ junction to ambient for the N package,and 158˚C/W typ junction to ambient for the H package.
Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 4: The power dissipation limit, however, cannot be exceeded.
Note 5: These specifications apply for VS=±15V and 0˚C≤TA≤+70˚C. VOS, IBand IOS are measured at VCM=0.
Note 6: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature, Tj. Due to the limitedproduction test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambienttemperature as a result of internal power dissipation, PD. Tj=TA+θjA PD where θjA is the thermal resistance from junction to ambient. Use of a heat sink isrecommended if input bias current is to be kept to a minimum.
Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS= ±6V to ±15V.
Note 8: Human body model, 1.5 kΩ in series with 100 pF.
Typical Performance CharacteristicsInput Bias Current Input Bias Current
0056491800564919
Supply Current Positive Common-Mode Input Voltage Limit
0056492000564921
LF353
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Typical Performance Characteristics (Continued)
Negative Common-Mode Input Voltage Limit Positive Current Limit
00564922 00564923
Negative Current Limit Voltage Swing
00564924 00564925
Output Voltage Swing Gain Bandwidth
00564926 00564927
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Typical Performance Characteristics (Continued)
Bode Plot Slew Rate
00564928 00564929
Distortion vs. Frequency Undistorted Output Voltage Swing
0056493000564931
Open Loop Frequency Response Common-Mode Rejection Ratio
00564932 00564933
LF353
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Typical Performance Characteristics (Continued)
Power Supply Rejection Ratio Equivalent Input Noise Voltage
0056493400564935
Open Loop Voltage Gain (V/V) Output Impedance
00564936 00564937
Inverter Settling Time
00564938
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Pulse ResponseSmall Signaling Inverting
00564904
Large Signal Inverting
00564906
Small Signal Non-Inverting
00564905
Large Signal Non-Inverting
00564907
Current Limit (RL = 100Ω)
00564908
Application HintsThese devices are op amps with an internally trimmed inputoffset voltage and JFET input devices (BI-FET II). TheseJFETs have large reverse breakdown voltages from gate tosource and drain eliminating the need for clamps across theinputs. Therefore, large differential input voltages can easilybe accommodated without a large increase in input current.The maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltagesshould be allowed to exceed the negative supply as this willcause large currents to flow which can result in a destroyedunit.
Exceeding the negative common-mode limit on either inputwill force the output to a high state, potentially causing areversal of phase to the output. Exceeding the negativecommon-mode limit on both inputs will force the amplifieroutput to a high state. In neither case does a latch occur
LF353
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Application Hints (Continued)
since raising the input back within the common-mode rangeagain puts the input stage and thus the amplifier in a normaloperating mode.
Exceeding the positive common-mode limit on a single inputwill not change the phase of the output; however, if bothinputs exceed the limit, the output of the amplifier will beforced to a high state.
The amplifiers will operate with a common-mode input volt-age equal to the positive supply; however, the gain band-width and slew rate may be decreased in this condition.When the negative common-mode voltage swings to within3V of the negative supply, an increase in input offset voltagemay occur.
Each amplifier is individually biased by a zener referencewhich allows normal circuit operation on ±6V power sup-plies. Supply voltages less than these may result in lowergain bandwidth and slew rate.
The amplifiers will drive a 2 kΩ load resistance to ±10V overthe full temperature range of 0˚C to +70˚C. If the amplifier isforced to drive heavier load currents, however, an increasein input offset voltage may occur on the negative voltageswing and finally reach an active current limit on both posi-tive and negative swings.
Precautions should be taken to ensure that the power supplyfor the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in asocket as an unlimited current surge through the resultingforward diode within the IC could cause fusing of the internalconductors and result in a destroyed unit.
As with most amplifiers, care should be taken with leaddress, component placement and supply decoupling in orderto ensure stability. For example, resistors from the output toan input should be placed with the body close to the input tominimize “pick-up” and maximize the frequency of the feed-back pole by minimizing the capacitance from the input toground.
A feedback pole is created when the feedback around anyamplifier is resistive. The parallel resistance and capacitancefrom the input of the device (usually the inverting input) to ACground set the frequency of the pole. In many instances thefrequency of this pole is much greater than the expected 3dB frequency of the closed loop gain and consequently thereis negligible effect on stability margin. However, if the feed-back pole is less than approximately 6 times the expected 3dB frequency a lead capacitor should be placed from theoutput to the input of the op amp. The value of the addedcapacitor should be such that the RC time constant of thiscapacitor and the resistance it parallels is greater than orequal to the original feedback pole time constant.
Detailed Schematic
00564909
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Typical ApplicationsThree-Band Active Tone Control
Order Number LF353M or LF353MXNS Package Number M08A
Molded Dual-In-Line PackageOrder Number LF353N
NS Package N08E
LF353
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Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implantinto the body, or (b) support or sustain life, andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling, can be reasonably expected to result in asignificant injury to the user.
2. A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system, or to affect itssafety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer ProductsStewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
National SemiconductorAmericas CustomerSupport CenterEmail: [email protected]: 1-800-272-9959
National SemiconductorEurope Customer Support Center
National SemiconductorAsia Pacific CustomerSupport CenterEmail: [email protected]
National SemiconductorJapan Customer Support CenterFax: 81-3-5639-7507Email: [email protected]: 81-3-5639-7560
www.national.com
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
DeviceOperating
Temperature Range Package
SEMICONDUCTORTECHNICAL DATA
BALANCEDMODULATORS/DEMODULATORS
ORDERING INFORMATION
MC1496D
MC1496PTA = 0°C to +70°C
SO–14
Plastic DIP
PIN CONNECTIONS
Order this document by MC1496/D
D SUFFIXPLASTIC PACKAGE
CASE 751A(SO–14)
P SUFFIXPLASTIC PACKAGE
CASE 646
Signal Input 1
2
3
4
5
6
7
10
11
14
13
12
9
N/C
Output
Bias
Signal Input
Gain Adjust
Gain Adjust
Input Carrier8
VEE
N/C
Output
N/C
Carrier Input
N/C
14
1
14
1
MC1496BP Plastic DIPTA = –40°C to +125°C
1MOTOROLA ANALOG IC DEVICE DATA
These devices were designed for use where the output voltage is aproduct of an input voltage (signal) and a switching function (carrier). Typicalapplications include suppressed carrier and amplitude modulation,synchronous detection, FM detection, phase detection, and chopperapplications. See Motorola Application Note AN531 for additional designinformation.
• Excellent Carrier Suppression –65 dB typ @ 0.5 MHzExcellent Carrier Suppression –50 dB typ @ 10 MHz
• Adjustable Gain and Signal Handling
• Balanced Inputs and Outputs
• High Common Mode Rejection –85 dB typical
This device contains 8 active transistors.
Figure 1. SuppressedCarrier Output
Waveform
Figure 2. SuppressedCarrier Spectrum
Figure 3. AmplitudeModulation Output
Waveform
Figure 4. Amplitude–Modulation Spectrum
IC = 500 kHz, IS = 1.0 kHz
IC = 500 kHzIS = 1.0 kHz
60
40
20
0
Log
Scal
e Id
499 kHz 500 kHz 501 kHz
IC = 500 kHzIS = 1.0 kHz
IC = 500 kHzIS = 1.0 kHz
499 kHz 500 kHz 501 kHz
Line
ar S
cale
10
8.0
6.0
4.0
2.0
0
Motorola, Inc. 1996 Rev 4
MC1496, B
2 MOTOROLA ANALOG IC DEVICE DATA
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Power Supply Current I6 +I12Power Supply Current I14
7 6 ICCIEE
––
2.03.0
4.05.0
mAdc
DC Power Dissipation 7 5 PD – 33 – mW
MC1496, B
3MOTOROLA ANALOG IC DEVICE DATA
GENERAL OPERATING INFORMATION
Carrier FeedthroughCarrier feedthrough is defined as the output voltage at
carrier frequency with only the carrier applied (signalvoltage = 0).
Carrier null is achieved by balancing the currents in thedifferential amplifier by means of a bias trim potentiometer(R1 of Figure 5).
Carrier SuppressionCarrier suppression is defined as the ratio of each
sideband output to carrier output for the carrier and signalvoltage levels specified.
Carrier suppression is very dependent on carrier inputlevel, as shown in Figure 22. A low value of the carrier doesnot fully switch the upper switching devices, and results inlower signal gain, hence lower carrier suppression. A higherthan optimum carrier level results in unnecessary device andcircuit carrier feedthrough, which again degenerates thesuppression figure. The MC1496 has been characterizedwith a 60 mVrms sinewave carrier input signal. This levelprovides optimum carrier suppression at carrier frequenciesin the vicinity of 500 kHz, and is generally recommended forbalanced modulator applications.
Carrier feedthrough is independent of signal level, VS.Thus carrier suppression can be maximized by operatingwith large signal levels. However, a linear operating modemust be maintained in the signal–input transistor pair – orharmonics of the modulating signal will be generated andappear in the device output as spurious sidebands of thesuppressed carrier. This requirement places an upper limit oninput–signal amplitude (see Figure 20). Note also that anoptimum carrier level is recommended in Figure 22 for goodcarrier suppression and minimum spurious sidebandgeneration.
At higher frequencies circuit layout is very important inorder to minimize carrier feedthrough. Shielding may benecessary in order to prevent capacitive coupling betweenthe carrier input leads and the output leads.
Signal Gain and Maximum Input LevelSignal gain (single–ended) at low frequencies is defined
as the voltage gain,
AVS VoVS
RLRe2re
where re 26 mVI5(mA)
A constant dc potential is applied to the carrier input terminalsto fully switch two of the upper transistors “on” and twotransistors “off” (VC = 0.5 Vdc). This in effect forms a cascodedifferential amplifier.
Linear operation requires that the signal input be below acritical value determined by RE and the bias current I5.
VS I5 RE (Volts peak)
Note that in the test circuit of Figure 10, VS corresponds to amaximum value of 1.0 V peak.
Common Mode SwingThe common–mode swing is the voltage which may be
applied to both bases of the signal differential amplifier,without saturating the current sources or without saturatingthe differential amplifier itself by swinging it into the upper
switching devices. This swing is variable depending on theparticular circuit and biasing conditions chosen.
Power DissipationPower dissipation, PD, within the integrated circuit package
should be calculated as the summation of the voltage–currentproducts at each port, i.e. assuming V12 = V6, I5 = I6 = I12and ignoring base current, PD = 2 I5 (V6 – V14) + I5)V5 – V14 where subscripts refer to pin numbers.
Design EquationsThe following is a partial list of design equations needed to
operate the circuit with other supply voltages and inputconditions.
A. Operating CurrentThe internal bias currents are set by the conditions at Pin 5.
Assume:I5 = I6 = I12,IB IC for all transistors
then :
R5V
I5500
where: R5 is the resistor betweenwhere: Pin 5 and groundwhere: φ = 0.75 at TA = +25°C
The MC1496 has been characterized for the conditionI5 = 1.0 mA and is the generally recommended value.
B. Common–Mode Quiescent Output Voltage
V6 = V12 = V+ – I5 RLBiasing
The MC1496 requires three dc bias voltage levels whichmust be set externally. Guidelines for setting up these threelevels include maintaining at least 2.0 V collector–base biason all transistors while not exceeding the voltages given inthe absolute maximum rating table;
The foregoing conditions are based on the followingapproximations:
V6 = V12, V8 = V10, V1 = V4
Bias currents flowing into Pins 1, 4, 8 and 10 are transistorbase currents and can normally be neglected if external biasdividers are designed to carry 1.0 mA or more.
Transadmittance BandwidthCarrier transadmittance bandwidth is the 3.0 dB bandwidth
of the device forward transadmittance as defined by:
21C io (each sideband)
vs (signal) Vo 0
Signal transadmittance bandwidth is the 3.0 dB bandwidthof the device forward transadmittance as defined by:
21S io (signal)vs (signal) Vc 0.5 Vdc, Vo 0
MC1496, B
4 MOTOROLA ANALOG IC DEVICE DATA
Coupling and Bypass CapacitorsCapacitors C1 and C2 (Figure 5) should be selected for a
reactance of less than 5.0 Ω at the carrier frequency.
Output SignalThe output signal is taken from Pins 6 and 12 either
balanced or single–ended. Figure 11 shows the output levelsof each of the two output sidebands resulting from variationsin both the carrier and modulating signal inputs with asingle–ended output connection.
Negative SupplyVEE should be dc only. The insertion of an RF choke in
series with VEE can enhance the stability of the internalcurrent sources.
Signal Port StabilityUnder certain values of driving source impedance,
oscillation may occur. In this event, an RC suppressionnetwork should be connected directly to each input usingshort leads. This will reduce the Q of the source–tunedcircuits that cause the oscillation.
Signal Input(Pins 1 and 4)
510
10 pF
An alternate method for low–frequency applications is toinsert a 1.0 kΩ resistor in series with the input (Pins 1, 4). Inthis case input current drift may cause serious degradation ofcarrier suppression.
TEST CIRCUITS
NOTE: Shielding of input and output leads may be neededto properly perform these tests.
Figure 5. Carrier Rejection and Suppression Figure 6. Input–Output Impedance
Figure 7. Bias and Offset Currents Figure 8. Transconductance Bandwidth
0.01µF2.0 k
–8.0 Vdc
I6
I9
1.0 k
I7I8
6.8 k
Zout+ Vo
+
+ VoI9
3
RL3.9 k
VCC12 Vdc
8
C10.1 µF
MC1496
1.0 k2
Re
1.0 k
C20.1 µF
51
10 k
ModulatingSignal Input
CarrierInput
VC
Carrier Null
515110 k
50 k
R1
VS – Vo
RL3.9 k
I6
I4
6
14 512
–
2
Re = 1.0 k
3
Zin
0.5 V 810
I1
41
– Vo101 6
4
14 5
12
6.8 k
V–I10
I5
–8.0 VdcVEE
1.0 k
MC1496
MC1496MC1496 6
14 5
12
I106.8 k
–8.0 VdcVEE
VCC12 Vdc
2
Re = 1.0 k
3
1.0 kModulatingSignal Input
CarrierInput
VCVS
0.1 µF
0.1 µF
1.0 k
51
1.0 k
14 5
6
12
1.0 k2 3
Re
VCC12 Vdc
2.0 k
+ Vo
– Vo
6.8 k
10 k
Carrier Null
5110 k
50 k
V–
–8.0 VdcVEE
50 50810
41
810
41
51
MC1496, B
5MOTOROLA ANALOG IC DEVICE DATA
+ Vo
33.9 k
VCC12 Vdc
8
MC1496
2
Re = 1.0 k1.0 k
0.5 V
1.0 k
50
+
VS– Vo
101 6
4
14 5
12
6.8 k
–8.0 VdcVEE
3.9 k
–
ACM 20 log VoVS
Figure 9. Common Mode Gain Figure 10. Signal Gain and Output Swing
V ,
OU
TPU
T AM
PLIT
UD
E O
F EA
CH
SID
EBAN
D (V
rms)
O
r ,
PAR
ALLE
L IN
PUT
RES
ISTA
NC
E (k
ip
Figure 11. Sideband Output versusCarrier Levels
Figure 12. Signal–Port Parallel–EquivalentInput Resistance versus Frequency
c ,
PAR
ALLE
L IN
PUT
CAP
ACIT
ANC
E (p
F)ip
c
, PAR
ALLE
L O
UTP
UT
CAP
ACIT
ANC
E (p
F)op
Figure 13. Signal–Port Parallel–EquivalentInput Capacitance versus Frequency
Figure 14. Single–Ended Output Impedanceversus Frequency
TYPICAL CHARACTERISTICSTypical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave),
VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25°C, unless otherwise noted.
I5 =1.0 mA
+ Vo
33.9 k
VCC12 Vdc
2
Re = 1.0 k
– Vo6
14 5
12
6.8 k
–8.0 VdcVEE
3.9 k0.5 V
+ –
1.0 k
1.0 k
VS
50
1.0
2.0
0
140
–rip
+rip
14
12
10
8.0
6.0
4.0
010010
120
0
101.0
20
5.0 100
40
50
1.0
1.0f, FREQUENCY (MHz)
80
200
2.0
5.0
10
100
100
500
1.0 M
60
50
100102.0
3.0
2.0
1.0
0
5.0
400 mV
Signal Input = 600 mV
4.0
VC, CARRIER LEVEL (mVrms)
1.6
0
0.8
0
0.4
1.2
10050 150
5.0
100 mV
200 mV
300 mV
5020f, FREQUENCY (MHz)f, FREQUENCY (MHz)
MC1496
81014
rop
Ω)
r ,
PAR
ALLE
L O
UTP
UT
RES
ISTA
NC
E (k
opΩ
)
cop
MC1496, B
6 MOTOROLA ANALOG IC DEVICE DATA
– 30
f, FREQUENCY (MHz)
20
10
0
– 10
– 20
0.1 1.0 10 1000.01
RL = 3.9 kRe = 500 Ω
RL = 3.9 kRe = 2.0 k
|VC| = 0.5 VdcRL = 500 ΩRe = 1.0 k
RL = 3.9 k (StandardRe = 1.0 k Test Circuit)
A
, SIN
GLE
-EN
DED
VO
LTAG
E G
AIN
(dB)
V S
1001.0
Side Band
0.3
0.4
01000
fC, CARRIER FREQUENCY (MHz)
0.6
0.91.0
10
0.8
0.7
0.1
0.2
0.5
0.1
21, T
RAN
SAD
MIT
TAN
CE
(mm
ho)
800
fC ± 3fS
800600400200VS, INPUT SIGNAL AMPLITUDE (mVrms)
fC ± 2fS
0
60
50
40
30
20
10
70
SUPP
RES
SIO
N B
ELO
W E
ACH
FU
ND
AMEN
TAL
CAR
RIE
R S
IDEB
AND
(dB)
fC
2fC
505.00.05 0.1 0.5 1.0 10
3fC
0
60
50
40
30
20
10
70
fC, CARRIER FREQUENCY (MHz)
SUPP
RES
SIO
N B
ELO
W E
ACH
FU
ND
AMEN
TAL
CAR
RIE
R S
IDEB
AND
(dB)
TA, AMBIENT TEMPERATURE(°C)
MC1496(70°C)
–75 –50
60
7550250–25
50
40
30
20
10
100 125 150 17570
CS
V
, C
ARR
IER
SU
PPR
ESIO
N (d
B)
AV RL
Re 2re
TYPICAL CHARACTERISTICS (continued)
Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave),VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25°C, unless otherwise noted.
0.1
5010
10
1.0
0.011.0 5.00.05 0.1 0.5
fC, CARRIER FREQUENCY (MHz)
V
, C
ARR
IER
OU
TPU
T VO
LTAG
E (m
Vrm
s)C
FT
Signal Port0
Figure 15. Sideband and Signal PortTransadmittances versus Frequency
Figure 16. Carrier Suppressionversus Temperature
Figure 17. Signal–Port Frequency ResponseFigure 18. Carrier Suppression
versus Frequency
Figure 19. Carrier Feedthroughversus Frequency
Figure 20. Sideband Harmonic Suppressionversus Input Signal Level
γ
21 IoutVin Vout 0 |VC| 0.5 Vdc
21 Iout (Each Sideband)
Vin (Signal) Vout 0
Sideband Transadmittance
Signal Port Transadmittance
MC1496, B
7MOTOROLA ANALOG IC DEVICE DATA
500100 4003000 200VC, CARRIER INPUT LEVEL (mVrms)
fC = 10 MHz
0
60
50
40
30
20
10
70
CS
V
, C
ARR
IER
SU
PPR
ESSI
ON
(dB)
2fC ± fS
2fC ± 2fS
3fC ± fS
fC, CARRIER FREQUENCY (MHz)50101.0 5.00.05 0.1 0.5
0
60
50
40
30
20
10
70
SUPP
RES
SIO
N B
ELO
W E
ACH
FU
ND
AMEN
TAL
CAR
RIE
R S
IDEB
AND
(dB)
Figure 21. Suppression of Carrier HarmonicSidebands versus Carrier Frequency
The MC1496, a monolithic balanced modulator circuit, isshown in Figure 23.
This circuit consists of an upper quad differential amplifierdriven by a standard differential amplifier with dual currentsources. The output collectors are cross–coupled so thatfull–wave balanced multiplication of the two input voltagesoccurs. That is, the output signal is a constant times theproduct of the two input signals.
Mathematical analysis of linear ac signal multiplicationindicates that the output spectrum will consist of only the sumand difference of the two input frequencies. Thus, the devicemay be used as a balanced modulator, doubly balanced mixer,product detector, frequency doubler, and other applicationsrequiring these particular output signal characteristics.
The lower differential amplifier has its emitters connectedto the package pins so that an external emitter resistancemay be used. Also, external load resistors are employed atthe device output.
Signal LevelsThe upper quad differential amplifier may be operated
either in a linear or a saturated mode. The lower differentialamplifier is operated in a linear mode for most applications.
For low–level operation at both input ports, the outputsignal will contain sum and difference frequency components
and have an amplitude which is a function of the product ofthe input signal amplitudes.
For high–level operation at the carrier input port and linearoperation at the modulating signal port, the output signal willcontain sum and difference frequency components of themodulating signal frequency and the fundamental and oddharmonics of the carrier frequency. The output amplitude willbe a constant times the modulating signal amplitude. Anyamplitude variations in the carrier signal will not appear in theoutput.
The linear signal handling capabilities of a differentialamplifier are well defined. With no emitter degeneration, themaximum input voltage for linear operation is approximately25 mV peak. Since the upper differential amplifier has itsemitters internally connected, this voltage applies to thecarrier input port for all conditions.
Since the lower differential amplifier has provisions for anexternal emitter resistance, its linear signal handling rangemay be adjusted by the user. The maximum input voltage forlinear operation may be approximated from the followingexpression:
V = (I5) (RE) volts peak.This expression may be used to compute the minimum
Carrier Input Signal (V C) Approximate Voltage Gain Output Signal Frequency(s)
Low–level dcRL VC
2(RE 2re) KTq
fM
High–level dcRL
RE 2refM
Low–level acRL VC(rms)
2 2 KTq (RE 2re)
fC ± fM
High–level ac0.637 RLRE 2re
fC ± fM, 3fC ± fM, 5fC ± fM, . . .
NOTES: 1. Low–level Modulating Signal, VM, assumed in all cases. VC is Carrier Input Voltage.2. When the output signal contains multiple frequencies, the gain expression given is for the output amplitude of
each of the two desired outputs, fC + fM and fC – fM.3. All gain expressions are for a single–ended output. For a differential output connection, multiply each
expression by two.4. RL = Load resistance.5. RE = Emitter resistance between Pins 2 and 3.6. re = Transistor dynamic emitter resistance, at 25°C;
re 26 mVI5 (mA)
7. K = Boltzmann′s Constant, T = temperature in degrees Kelvin, q = the charge on an electron.KTq 26 mV at room temperature
The gain from the modulating signal input port to theoutput is the MC1496 gain parameter which is most often ofinterest to the designer. This gain has significance only whenthe lower differential amplifier is operated in a linear mode,but this includes most applications of the device.
As previously mentioned, the upper quad differentialamplifier may be operated either in a linear or a saturatedmode. Approximate gain expressions have been developedfor the MC1496 for a low–level modulating signal input andthe following carrier input conditions:
1) Low–level dc2) High–level dc3) Low–level ac4) High–level ac
These gains are summarized in Figure 25, along with thefrequency components contained in the output signal.
APPLICATIONS INFORMATIONDouble sideband suppressed carrier modulation is the
basic application of the MC1496. The suggested circuit forthis application is shown on the front page of this data sheet.
In some applications, it may be necessary to operate theMC1496 with a single dc supply voltage instead of dualsupplies. Figure 26 shows a balanced modulator designedfor operation with a single 12 Vdc supply. Performance of thiscircuit is similar to that of the dual supply modulator.
AM ModulatorThe circuit shown in Figure 27 may be used as an
amplitude modulator with a minor modification.
All that is required to shift from suppressed carrier to AMoperation is to adjust the carrier null potentiometer for theproper amount of carrier insertion in the output signal.
However, the suppressed carrier null circuitry as shown inFigure 27 does not have sufficient adjustment range.Therefore, the modulator may be modified for AM operationby changing two resistor values in the null circuit as shown inFigure 28.
Product DetectorThe MC1496 makes an excellent SSB product detector
(see Figure 29).This product detector has a sensitivity of 3.0 microvolts
and a dynamic range of 90 dB when operating at anintermediate frequency of 9.0 MHz.
The detector is broadband for the entire high frequencyrange. For operation at very low intermediate frequenciesdown to 50 kHz the 0.1 µF capacitors on Pins 8 and 10should be increased to 1.0 µF. Also, the output filter at Pin 12can be tailored to a specific intermediate frequency and audioamplifier input impedance.
As in all applications of the MC1496, the emitter resistancebetween Pins 2 and 3 may be increased or decreased toadjust circuit gain, sensitivity, and dynamic range.
This circuit may also be used as an AM detector byintroducing carrier signal at the carrier input and an AM signalat the SSB input.
The carrier signal may be derived from the intermediatefrequency signal or generated locally. The carrier signal maybe introduced with or without modulation, provided its level issufficiently high to saturate the upper quad differential
MC1496, B
9MOTOROLA ANALOG IC DEVICE DATA
amplifier. If the carrier signal is modulated, a 300 mVrmsinput level is recommended.
Doubly Balanced MixerThe MC1496 may be used as a doubly balanced mixer
with either broadband or tuned narrow band input and outputnetworks.
The local oscillator signal is introduced at the carrier inputport with a recommended amplitude of 100 mVrms.
Figure 30 shows a mixer with a broadband input and atuned output.
Frequency DoublerThe MC1496 will operate as a frequency doubler by
introducing the same frequency at both input ports.
Figures 31 and 32 show a broadband frequency doublerand a tuned output very high frequency (VHF) doubler,respectively.
Phase Detection and FM DetectionThe MC1496 will function as a phase detector. High–level
input signals are introduced at both inputs. When both inputsare at the same frequency the MC1496 will deliver an outputwhich is a function of the phase difference between the twoinput signals.
An FM detector may be constructed by using the phasedetector principle. A tuned circuit is added at one of the inputsto cause the two input signals to vary in phase as a functionof frequency. The MC1496 will then provide an output whichis a function of the input signal frequency.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, andspecifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motoroladata sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights ofothers. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or otherapplications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injuryor death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorolaand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney feesarising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges thatMotorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an EqualOpportunity/Affirmative Action Employer.
How to reach us:USA/EUROPE/Locations Not Listed : Motorola Literature Distribution; JAPAN : Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: [email protected] – TOUCHTONE 602–244–6609 ASIA/PACIFIC : Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC1496/D
◊
LM565/LM565CPhase Locked LoopGeneral DescriptionThe LM565 and LM565C are general purpose phase lockedloops containing a stable, highly linear voltage controlled os-cillator for low distortion FM demodulation, and a double bal-anced phase detector with good carrier suppression. TheVCO frequency is set with an external resistor and capacitor,and a tuning range of 10:1 can be obtained with the samecapacitor. The characteristics of the closed loopsystem — bandwidth, response speed, capture and pull inrange — may be adjusted over a wide range with an externalresistor and capacitor. The loop may be broken between theVCO and the phase detector for insertion of a digital fre-quency divider to obtain frequency multiplication.
The LM565H is specified for operation over the −55˚C to+125˚C military temperature range. The LM565CN is speci-fied for operation over the 0˚C to +70˚C temperature range.
Featuresn 200 ppm/˚C frequency stability of the VCOn Power supply range of ±5 to ±12 volts with 100 ppm/%
typical
n 0.2% linearity of demodulated outputn Linear triangle wave with in phase zero crossings
availablen TTL and DTL compatible phase detector input and
square wave outputn Adjustable hold in range from ±1% to > ±60%
Applicationsn Data and tape synchronizationn Modemsn FSK demodulationn FM demodulationn Frequency synthesizern Tone decodingn Frequency multiplication and divisionn SCA demodulatorsn Telemetry receiversn Signal regenerationn Coherent demodulators
If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage ±12VPower Dissipation (Note 2) 1400 mWDifferential Input Voltage ±1V
Operating Temperature RangeLM565H −55˚C to +125˚CLM565CN 0˚C to +70˚C
Storage Temperature Range −65˚C to +150˚CLead Temperature
(Soldering, 10 sec.) 260˚C
Electrical CharacteristicsAC Test Circuit, TA = 25˚C, VCC = ±6V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-tional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guar-antee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit isgiven, however, the typical value is a good indication of device performance.
Note 2: The maximum junction temperature of the LM565 and LM565C is +150˚C. For operation at elevated temperatures, devices in the TO-5 package must bederated based on a thermal resistance of +150˚C/W junction to ambient or +45˚C/W junction to case. Thermal resistance of the dual-in-line package is +85˚C/W.
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Typical Performance Characteristics
Power Supply Current as aFunction of Supply Voltage
DS007853-14
Lock Range as a Functionof Input Voltage
DS007853-15
VCO Frequency
DS007853-16
Oscillator OutputWaveforms
DS007853-17
Phase Shift vs Frequency
DS007853-18
VCO Frequency as aFunction of Temperature
DS007853-19
Loop Gain vs LoadResistance
DS007853-20
Hold in Range as aFunction of R 6–7
DS007853-21
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Schematic Diagram
DS
0078
53-1
www.national.com 4
AC Test Circuit
Typical Applications
DS007853-5
Note: S1 open for output offset voltage (V7 − V6) measurement.
2400 Hz Synchronous AM Demodulator
DS007853-6
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Typical Applications (Continued)
FSK Demodulator (2025–2225 cps)
DS007853-7
FSK Demodulator with DC Restoration
DS007853-8
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Typical Applications (Continued)
Frequency Multiplier (x10)
DS007853-9
IRIG Channel 13 Demodulator
DS007853-10
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Applications InformationIn designing with phase locked loops such as the LM565, theimportant parameters of interest are:
FREE RUNNING FREQUENCY
LOOP GAIN: relates the amount of phase change betweenthe input signal and the VCO signal for a shift in input signalfrequency (assuming the loop remains in lock). In servotheory, this is called the “velocity error coefficient.”
The loop gain of the LM565 is dependent on supply voltage,and may be found from:
fo = VCO frequency in Hz
Vc = total supply voltage to circuit
Loop gain may be reduced by connecting a resistor betweenpins 6 and 7; this reduces the load impedance on the outputamplifier and hence the loop gain.
HOLD IN RANGE: the range of frequencies that the loop willremain in lock after initially being locked.
fo= free running frequency of VCO
Vc= total supply voltage to the circuit
THE LOOP FILTER
In almost all applications, it will be desirable to filter the sig-nal at the output of the phase detector (pin 7); this filter maytake one of two forms:
A simple lag filter may be used for wide closed loop band-width applications such as modulation following where thefrequency deviation of the carrier is fairly high (greater than10%), or where wideband modulating signals must be fol-lowed.
The natural bandwidth of the closed loop response may befound from:
Associated with this is a damping factor:
For narrow band applications where a narrow noise band-width is desired, such as applications involving tracking aslowly varying carrier, a lead lag filter should be used. In gen-eral, if 1/R1C1 < Ko KD, the damping factor for the loop be-comes quite small resulting in large overshoot and possibleinstability in the transient response of the loop. In this case,the natural frequency of the loop may be found from
R2 is selected to produce a desired damping factor δ, usuallybetween 0.5 and 1.0. The damping factor is found from theapproximation:
δ ) π τ2fnThese two equations are plotted for convenience.
Simple Lead Filter
DS007853-11
Lag-Lead Filter
DS007853-12
Filter Time Constant vs Natural Frequency
DS007853-13
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Applications Information (Continued) Capacitor C2 should be much smaller than C1 since its func-tion is to provide filtering of carrier. In general C2 ≤ 0.1 C1.
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implantinto the body, or (b) support or sustain life, andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling, can be reasonably expected to result in asignificant injury to the user.
2. A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system, or to affect itssafety or effectiveness.
National SemiconductorCorporationAmericasTel: 1-800-272-9959Fax: 1-800-737-7018Email: [email protected]
National SemiconductorAsia Pacific CustomerResponse GroupTel: 65-2544466Fax: 65-2504466Email: [email protected]
National SemiconductorJapan Ltd.Tel: 81-3-5639-7560Fax: 81-3-5639-7507
www.national.com
LM565/LM
565CP
haseLocked
Loop
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Note 1: The “Absolute Maximum Ratings” are those values beyond whichthe safety of the device cannot be guaranteed. The device should not beoperated at these limits. The parametric values defined in the ElectricalCharacteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditionsfor actual device operation.
Recommended Operating Conditions
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4: ICCH is measured with all outputs OPEN, one input at each gate at 4.5V, and the other inputs grounded.
Note 5: ICCL is measured with all outputs OPEN and all inputs grounded.
Switching Characteristics at VCC = 5V and TA = 25°C
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −0.4 mA
IOL LOW Level Output Current 8 mA
TA Free Air Operating Temperature 0 70 °C
Symbol Parameter Conditions MinTyp
Max Units(Note 2)
VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max,2.7 3.4 V
Output Voltage VIL = Max, VIH = Min
VOL LOW Level VCC = Min, IOL = Max,0.35 0.5
Output Voltage VIL = Max, VIH = Min V
IOL = 4 mA, VCC = Min 0.25 0.4
II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.2 mA
IIH HIGH Level Input Current VCC = Max, VI = 2.7V 40 µA
IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.6 mA
IOS Short Circuit Output Current VCC = Max (Note 3) −20 −100 mA
ICCH Supply Current with Outputs HIGH VCC = Max (Note 4) 6.1 10 mA
ICCL Supply Current with Outputs LOW VCC = Max (Note 5) 9 15 mA
RL = 2 kΩ
Symbol Parameter Conditions CL = 15 pF CL = 50 pF Units
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.
2. A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.
Note 1: The “Absolute Maximum Ratings” are those values beyond whichthe safety of the device cannot be guaranteed. The device should not beoperated at these limits. The parametric values defined in the ElectricalCharacteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditionsfor actual device operation.
Recommended Operating Conditions
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics at VCC = 5V and TA = 25°C
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −0.4 mA
IOL LOW Level Output Current 8 mA
TA Free Air Operating Temperature 0 70 °C
Symbol Parameter Conditions MinTyp
Max Units(Note 2)
VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max,2.7 3.4 V
Output Voltage VIL = Max
VOL LOW Level VCC = Min, IOL = Max,0.35 0.5
Output Voltage VIH = Min V
IOL = 4 mA, VCC = Min 0.25 0.4
II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA
IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA
IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.36 mA
IOS Short Circuit Output Current VCC = Max (Note 3) −20 −100 mA
ICCH Supply Current with Outputs HIGH VCC = Max 0.8 1.6 mA
ICCL Supply Current with Outputs LOW VCC = Max 2.4 4.4 mA
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.
2. A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.
*Dimension including the plating thicknessBase material dimension
*0.2
2 ±
0.05
*0.42 ± 0.08
0.12
0.15
M
2.20
Max
5.5
10.06
0.80 Max
16 9
1 8
10.5 Max
+ 0.20– 0.307.80
0.70 ± 0.20
0° – 8°
0.10
± 0
.10
1.15
1.27
0.40 ± 0.06
0.20
± 0
.04
Hitachi CodeJEDECEIAJWeight (reference value)
FP-16DNConformsConforms0.15 g
Unit: mm
*Dimension including the plating thicknessBase material dimension
1.27
16 9
1 8
0.15
0.25 M
1.75
Max
3.95
*0.2
2 ±
0.03
9.9
0° – 8°
10.3 Max
+ 0.10– 0.306.10
+ 0.67– 0.200.60
+ 0
.11
– 0.
040.
14
*0.42 ± 0.08
0.635 Max
0.40 ± 0.06
0.20
± 0
.03
1.08
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,copyright, trademark, or other intellectual property rights for information contained in this document.Hitachi bears no responsibility for problems that may arise with third party’s rights, includingintellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you havereceived the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,contact Hitachi’s sales office before using the product in an application that demands especially highquality and reliability or where its failure or malfunction may directly threaten human life or cause riskof bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularlyfor maximum rating, operating supply voltage range, heat radiation characteristics, installationconditions and other characteristics. Hitachi bears no responsibility for failure or damage when usedbeyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeablefailure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or otherconsequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document withoutwritten approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductorproducts.
Hitachi, Ltd.Semiconductor & Integrated Circuits.Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, JapanTel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
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54LS74/DM54LS74A/DM74LS74ADual Positive-Edge-Triggered D Flip-Flopswith Preset, Clear and Complementary Outputs
General DescriptionThis device contains two independent positive-edge-trig-
gered D flip-flops with complementary outputs. The informa-
tion on the D input is accepted by the flip-flops on the posi-
tive going edge of the clock pulse. The triggering occurs at a
voltage level and is not directly related to the transition time
of the rising edge of the clock. The data on the D input may
be changed while the clock is low or high without affecting
the outputs as long as the data setup and hold times are not
violated. A low logic level on the preset or clear inputs will
set or reset the outputs regardless of the logic levels of the
other inputs.
FeaturesY Alternate military/aerospace device (54LS74) is avail-
able. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6373–1
Order Number 54LS74DMQB, 54LS74FMQB, 54LS74LMQB,
DM54LS74AJ, DM54LS74AW, DM74LS74AM or DM74LS74AN
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
Inputs Outputs
PR CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H* H*H H u H H L
H H u L L H
H H L X Q0 Q0
H e High Logic Level
X e Either Low or High Logic Level
L e Low Logic Level
u e Positive-going Transition
* e This configuration is nonstable; that is, it will not persist when either the preset
and/or clear inputs return to their inactive (high) level.
Q0 e The output logic level of Q before the indicated input conditions were established.
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range
DM54LS and 54LS b55§C to a125§CDM74LS 0§C to a70§C
Storage Temperature Range b65§C to a150§C
Note: The ‘‘Absolute Maximum Ratings’’ are those valuesbeyond which the safety of the device cannot be guaran-teed. The device should not be operated at these limits. Theparametric values defined in the ‘‘Electrical Characteristics’’table are not guaranteed at the absolute maximum ratings.The ‘‘Recommended Operating Conditions’’ table will definethe conditions for actual device operation.
Recommended Operating Conditions
Symbol ParameterDM54LS74A DM74LS74A
UnitsMin Nom Max Min Nom Max
VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
VIL Low Level Input Voltage 0.7 0.8 V
IOH High Level Output Current b0.4 b0.4 mA
IOL Low Level Output Current 4 8 mA
fCLK Clock Frequency (Note 2) 0 25 0 25 MHz
fCLK Clock Frequency (Note 3) 0 20 0 20 MHz
tW Pulse Width Clock High 18 18
(Note 2)Preset Low 15 15 ns
Clear Low 15 15
tW Pulse Width Clock High 25 25
(Note 3)Preset Low 20 20 ns
Clear Low 20 20
tSU Setup Time (Notes 1 and 2) 20u 20u ns
tSU Setup Time (Notes 1 and 3) 25u 25u ns
tH Hold Time (Note 1 and 4) 0u 0u ns
TA Free Air Operating Temperature b55 125 0 70 §CNote 1: The symbol (u) indicates the rising edge of the clock pulse is used for reference.
Note 2: CL e 15 pF, RL e 2 kX, TA e 25§C, and VCC e 5V.
Note 3: CL e 50 pF, RL e 2 kX, TA e 25§C, and VCC e 5V.
Note 4: TA e 25§C and VCC e 5V.
2
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions MinTyp
Max Units(Note 1)
VI Input Clamp Voltage VCC e Min, II e b18 mA b1.5 V
VOH High Level Output VCC e Min, IOH e Max DM54 2.5 3.4V
Voltage VIL e Max, VIH e MinDM74 2.7 3.4
VOL Low Level Output VCC e Min, IOL e Max DM54 0.25 0.4
Voltage VIL e Max, VIH e MinDM74 0.35 0.5 V
IOL e 4 mA, VCC e Min DM74 0.25 0.4
II Input Current @Max VCC e Max Data 0.1
Input Voltage VI e 7VClock 0.1
mAPreset 0.2
Clear 0.2
IIH High Level Input VCC e Max Data 20
Current VI e 2.7VClock 20
mAClear 40
Preset 40
IIL Low Level Input VCC e Max Data b0.4
Current VI e 0.4VClock b0.4
mAPreset b0.8
Clear b0.8
IOS Short Circuit VCC e Max DM54 b20 b100mA
Output Current (Note 2)DM74 b20 b100
ICC Supply Current VCC e Max (Note 3) 4 8 mA
Note 1: All typicals are at VCC e 5V, TA e 25§C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where
shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO e 2.25V and 2.125V for DM54 and
DM74 series, respectively, with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test
equipment.
Note 3: With all outputs open, ICC is measured with CLOCK grounded after setting the Q and Q outputs high in turn.
Switching Characteristics at VCC e 5V and TA e 25§C (See Section 1 for Test Waveforms and Output Load)
From (Input)RL e 2 kX
Symbol Parameter To (Output) CL e 15 pF CL e 50 pF Units
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National SemiconductorCorporation Europe Hong Kong Ltd. Japan Ltd.1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, KowloonFax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.