Delay Locked Loop Delay Locked Loop with Linear Delay with Linear Delay Element Element Goran Jovanović, Mile Stojčev and Dragiša Krstić Faculty of Electronic Engineering, Niš, Serbia TELSIKS 2005, Niš
Jan 03, 2016
Delay Locked Loop with Delay Locked Loop with Linear Delay ElementLinear Delay Element
Goran Jovanović, Mile Stojčev and Dragiša KrstićFaculty of Electronic Engineering, Niš, Serbia and Montenegro
TELSIKS 2005, Niš
DLL circuit is designed for fine, precise, and accurate pulse delay control in a high-speed digital and mixed integrated circuits.
Definition of DLLDefinition of DLL
• achieve correct synchronization between different digital blocks (CPU and SDRAM interface, ...),
• eliminate clock skew and jitter within VLSI ICs,• low-jitter clock synthesis, • implementation of Time-to-Digital-Converter with Vernier
delay pattern,• PN code tracking in spread spectrum systems…
Applications of DLLApplications of DLL
CP
PD
UP DOWN
Vctrl
C
CLKin CLKout
LPF
VCDL
FSM
PD
CLKinDCDL
PS
CP
PD
UP DOWN
Vctrl
C
CLKout
LPF
VCDLAnalog DLL
FSM
PD
CLKin
CLKout
DL
PS
Digital DLL
Hybrid DLL
Types of the DLL architectureTypes of the DLL architecture
VCDL – voltage controlled delay line, PD – phase detector, CP – charge pump, PS – phase selector, FSM – finite state machine
The DLL structure is based on a delay element.
According to the principle of delay generation DLL architectures classified as:
•analog, analog,
•digital, and digital, and
•hybrid (dual loop)hybrid (dual loop)
Classification of delay line elements Classification of delay line elements
Variable delay line elements are classified as:Variable delay line elements are classified as:• Digital- Controlled Delay Elements (DCDEs)Digital- Controlled Delay Elements (DCDEs)
realized as series of delay elements of variable length (the number of elements in a chain determines the amount of the delay).
• Voltage-Controlled Delay Elements (VCDEs)Voltage-Controlled Delay Elements (VCDEs)are inverter-based circuits, efficient in applications where small, accurate, and precise amount of delay is necessary to achieve.
Common to VCDLsCommon to VCDLs
Advantages:Advantages:• Simple structuresSimple structures• Fine delay resolutionFine delay resolutionDisadvantages:Disadvantages:• Voltage controlled DLs have non-linear transfer Voltage controlled DLs have non-linear transfer
function, delay variation in term of control function, delay variation in term of control voltage voltage
Problem of VCDL realization was considered by:Problem of VCDL realization was considered by:• Y. MoonY. Moon, , et al., “An All-Analog Multiphase Delay-Locked Loop Using a Replica et al., “An All-Analog Multiphase Delay-Locked Loop Using a Replica
Delay Line for Wide-Range Operation and Low-Jitter Performance”, Delay Line for Wide-Range Operation and Low-Jitter Performance”, IEEE JSSCIEEE JSSC, , vol.35, No. 3, pp. 377-384, March 2000.vol.35, No. 3, pp. 377-384, March 2000.
• M. Maymandi-Nejad, M. Sachdev, “A digitally Programmable Delay Element: Design M. Maymandi-Nejad, M. Sachdev, “A digitally Programmable Delay Element: Design and Analysis”, and Analysis”, IEEE Trans. on VLSI SystemsIEEE Trans. on VLSI Systems, vol. 11, No. 5, October 2003., vol. 11, No. 5, October 2003.
• G. Jovanović, M. Stojčev, “Voltage Controlled Delay Line for Digital Signal”, G. Jovanović, M. Stojčev, “Voltage Controlled Delay Line for Digital Signal”, Facta Facta Universitatis, Series: Electronics and EnergeticUniversitatis, Series: Electronics and Energetic, vol. 16. No. 2, pp. 215-232, August , vol. 16. No. 2, pp. 215-232, August 2003...2003...
What we proposeWhat we propose• Linearization of VCDL’s transfer functionLinearization of VCDL’s transfer function• We use Current Starved DE. We use Current Starved DE. • Why: Why:
– Simple structureSimple structure– Relatively wide range of delay regulationRelatively wide range of delay regulation
• How we achieve linear VCDL?How we achieve linear VCDL?– We modify the bias circuit. We modify the bias circuit. – We use a non-linear bias circuit which is based on We use a non-linear bias circuit which is based on
the square-law characteristics of a MOS transistor the square-law characteristics of a MOS transistor in saturation. in saturation.
– By a cascade connection of two non-linear By a cascade connection of two non-linear elements, the bias circuit and the current starved elements, the bias circuit and the current starved delay element, we obtain a linear transfer function delay element, we obtain a linear transfer function (delay in terms of control voltage).(delay in terms of control voltage).
Delay Line Element – standard solutionDelay Line Element – standard solutionCascade composition of a bias circuit and VCDLCascade composition of a bias circuit and VCDL
swcp
delay VI
Ct
where:
tdelay - delay time,
C - parasitic output capacitance,
Vsw clock buffer (inverter) swing voltage,
Icp - charging/discharging current of C.
Vctrl
VBP
M1
Vdd
VBNM6
M5
Vdd1.5/21
2/212/7
1.5/7
M2
M3
M4
2/7
2/21
Vdd
IN OUT
voltage control delay element
Icp
Icp
Cload
linearbias
circuit
VBN
VBP
Bias circuit with Bias circuit with reciprocal current regulationreciprocal current regulation
proposalproposal
VBP
inin out
VBN
VBP
VBN
Vdd
Vdd Vdd
Vctrl+
Vctrl -
WA / LA
R
B1 B2I1 I2
IBss
I0'
Vctrl
I0''R
Vdiff
B1
MD1 MD2
MA1 MA2
MS1
MS2
MS3
WA / LA
Bias Circuit
M1
M2
M3
M4
M5
M6
Vdd
Vdd
C
Icp
Icp
(a)
(b)
Current Starved Delay Elements
BP
Vdd
6/21
6/21
6/7
BN
Vdd Vdd
d_BP
d_BP
c
AGND
Vctrl+
Vctrl -
WA / LA
2/28
4/28
R2/28
3/28
4/28
6/28
To
Del
ay
Lin
e
Fro
m b
and-
gap
circ
uit
B1 B2I1 I2
IBss
I0'
Vctrl
6/28
3/28
I0''
R
Vdiff
B1
MB1 MB2
MB3 MB4
MB5 MB6
MD1 MD2
MA1 MA2
MS1
MS2
MS3WA / LA
Schematic of a bias circuit with analytic modelSchematic of a bias circuit with analytic model
R
VII ctrl '
01R
VII ctrl ''
02
tnn
B Vk
IV 1
1
11 ICIBAI Bss
224 tntpddp VVV
kA
n
tntpddp
k
VVVkB
22
4
n
p
k
kC
4
1
Bias circuit Bias circuit HSpice simulationHSpice simulation
Charge-discharge current variation in terms of control voltage
Relative approximation error of the reciprocal charge-discharge current variation in terms of control voltage
-0.8 -0.4 0 0.4 0.8 1 14
18
22
26
28
Vctrl [V]
I cp
[A
]
-0.8 -0.4 0 0.4 0.8 1 -4
-3
-2
-1
0
1
2
Vctrl [V]
App
roxi
mat
ion
Err
or
[%]
a)
b)
Current starved VCDL with linear delay regulation Current starved VCDL with linear delay regulation - Complete design -- Complete design -
VBP
VCDE1
VBN
VBP
VCDE2
VBN
VBP VBP
VBNVBN
VCDE3OB1VCDE4
OB4
OB3
OB2
delay line
Vctrl+
VBN
VBP
biasVctrl-
CLKin CLKout1
CLKout2
CLKout3
CLKout4
I VI
V V2
I Schematic of four stage DL
HSpice delay line HSpice delay line simulation simulation
– results relate to – results relate to CLKCLKout4out4 – –
Time delay, Time delay, ttdelay delay , , in term in term
of control voltage of control voltage VVctrlctrl
Relative approximation error Relative approximation error of time delay, of time delay, ttdelay delay , , in term in term
of control voltage of control voltage VVctrlctrl
-0.8 -0.4 0 0.4 0.8 125
30
40
50
60
t de
lay
[ns]
Vctrl [V]
-0.8 0 0.4 0.8 1-1000
-500
0
500
1000
1500
2000
2500
3000
- 0.4Vctrl [V]
td
ela
y [p
s]
a)
b)
Charge Pump
Voltage Controlled Delay Line
Phase Detector
UP
DO
WN
Vctrl+
C1
VBP VBN
CLKin CLKout
Charge Pump
DO
WN
UP
C2
Vctrl-
V I
I V
V2 I
Bia
s ci
rcui
tC
P1
CP
2
PD
VCDL
LP
F1
LP
F2
DLL differential architectureDLL differential architecture
New DLL architecture New DLL architecture with: with:
►differential charge differential charge pump, pump, ►two low-pass filter two low-pass filter and and ►nonlinear bias circuit nonlinear bias circuit with differential inputwith differential input
M11
Vdd
1.5/4
M12
M13
Vdd
M15
1.5/7
1.5/7M14
Vdd
1.5/4M16
1.5/7
1.5/4
M17
M18
Vdd
1.5/7
1.5/4REF
DOWN
BACK
M21
Vdd
1.5/4
M22
M23
Vdd
M25
1.5/7
1.5/7M24
Vdd
1.5/4M26
1.5/7
1.5/4
M27
M28
Vdd
1.5/7
1.5/4
UPREF
BACK
DOWN
UP
REF
BACK
UP
DOWNa) b)
From bias
From bias
Vctrl-
DOWN
Vdd
UP
1.5/16
8/16
8/8
1.5/8
CP_BP
CP_BN
[8]
[8]
[8]
[8]
Charge pump - CP1
DOWN
Vdd
UP1.5/16
8/16
8/8
1.5/8
CP_BP
CP_BN
[8]
[8]
[8]
[8]
Fro
m
phas
e de
tect
or
Charge pump - CP2
Fro
m
phas
e de
tect
or
Vctrl +
Other DLL’s parts:Other DLL’s parts:- dual charge pump - dual charge pump - dynamic phase detector- dynamic phase detector
HSpice simulation of the full DLLHSpice simulation of the full DLL
CLKCLKinin
CLKCLKoutout
VVctrlctrl--
VVctrlctrl++UPUPDOWNDOWN
Conclusion Conclusion ►An implementation of DLL with a linear An implementation of DLL with a linear VCDL is proposed.VCDL is proposed.►Current starved DL is used.Current starved DL is used.►Linearization is achieved by modifying Linearization is achieved by modifying the bias circuit of current starved DL. the bias circuit of current starved DL. ► HSpice simulation results points to the HSpice simulation results points to the fact that for 1.2 fact that for 1.2 m CMOS technology m CMOS technology high delay linearity (error is less then 500 high delay linearity (error is less then 500 ps) within the full range of regulation ps) within the full range of regulation (from 28 to 55 ns) is achieved.(from 28 to 55 ns) is achieved.►Linear DL requests new DLL Linear DL requests new DLL architecture with differential charge architecture with differential charge pump, two low-pass filter and bias circuit pump, two low-pass filter and bias circuit with differential input. with differential input.
Q & AQ & A