Decs Lab Manulas

Sri Venkateswara College of Engineering & Technology R.V.S Nagar, Chittoor M.Tech. I SEMESTER (DECS) DIGITAL SYSTEM DESIGN LAB List of Experiments1. Simulation and Verification of Logic Gates. 2. Design and Simulation of (a) Half adder (b) Full adder (c) Serial Binary adder (d) Carry Look Ahead adder (e) Ripple Carry adder 3. Simulation and Verification of (a) Decoder (b) Mux (c) Encoder 4 Modeling of Flip-Flops (a) SR Flip-Flops (b) D Flip-Flops (c) JK Flip-Flops (d) T Flip-Flops 5. Design and Simulation of Counters (a) Ring Counters (b) Johnson Counters (c) Up-Down Counters (d) Ripple Counters (Asynchronous) 6. Design of a N- bit Register (a) Serial-in Serial-out (b) Serial in Parallel out (c) Parallel in Serial out (d) Parallel in Parallel out 7. Design of Sequence detector. 8. 4-Bit Multiplier (Array) 9. Design of ALU. 10. RAM (Read and Write Operations) 11. Stack and Queue Implementation.

Lab-In-charge

HOD, ECE

LOGIC GATES Ex. No : 01 AIM :To write a VHDL Code for realizing Gates AND, OR, NOT, NAND, NOR, XOR, XNOR And verify the results. AND GATE PROGRAM:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and2 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end and2; architecture data_flow of and2 is begin c