December 3, 2010 Public Conference MAKUHARI MESSE International Conference Hall Assembly and Packaging.

December 3, 2010 Public Conference MAKUHARI MESSE International Conference Hall

Assembly and Assembly and PackagingPackaging


Assembly and Packaging Technical Assembly and Packaging Technical Working Group – 2010 (93 Participants)Working Group – 2010 (93 Participants)

Joseph Adam, Sai Ankireddi, Bernd Appelt, Richard Arnold, Muhannad S. Bakir, Souvik Banerjee, Rozalia Beica, Steve Bezuk, Mario Bolanos-Avila, W.R. Bottoms, Yi-jen Chan, Chi-Shih Chang, Clinton Chao, Carl, Chen, William Chen, Sonjin Cho, Yulkyo Chung, Bob Chylak, Mark De Samber, Krishor Desai, Dan Evans, Bradford Factor, Tatsuhiro Fujiki, Michael Gaitan, Michel Garnier, Steve Greathouse, Tom Gregorich, Richard Grzybowski, George Harman, Shuhya Haruguchi, Ryo Haruta, Tomoo Hayashi, Harold Hosack, Willem Hoving, Mike Hung, John Hunt, Kazuyuki Imamura, Hisao Kasuga, Dan Kilper, Mitchitaka Kimura, Shoji Kitamura, Takanori Kubo, Choon Heung Lee, Ricky S W Lee, Rong-Shen Lee, Russell Lewis, Sebastian Liau, Weichung Lo, David D. Lu, Abhay Maheshwan, Debendra Mallik, Kaneto Matsushita, Masao Matsuura, Lei Mercado, Hirofumi Nakajima, Keith Newman, Luu Nguyen, John Osenbach, Masashi Otsuka, Richard F. Otte, Gilles Poupon, Klaus Pressel, Gamal Refai-Ahmed, Charles Richardson, Peter Robinson, Bernd Roemer, Gurtej Sandu, Naoto Sasaki, Paul Siblerud, Vern Solberg, Simon Stacey, Yoshiaki Sugizaki, Teresa Sze, Coen Tak, Takashi Takata, Patrick Thompson, Claudio Truzzi, Andy Tseng, Shigeyuki Ueda, Shoji Uegaki, Ryosuke Usui, Henry Utsunomiya, Kripesh Vaidyanathan, Freek Van Straten, Julien Vittu, James Wilcox, Max Juergen Wolf, Jie Xue, Zhiping Yang, Hiroshi, Yokota, Eiji Yoshida, Hiroyoshi Yoshida.


Assembly and Packaging Technical Assembly and Packaging Technical Working Group - 2010Working Group - 2010

• 87 Members Participated in 2010 Activities • Focus of activities for 2010

– The only change to tables will be AP1: Difficult Challenges – Preparation for 2011 with expanded coverage for:

• Medical electronics, • 3D integration• Interposers • Automotive electronics • Optoelectronics • Printed electronics• Handling of thinned wafers and die• Embedded components• MEMS integration

– Rewrite of the System in Package paper

• Cross TWG coordination– Major collaborations include ERM, ERD, ESH, Interconnect, Design, Test

• Coordination with other Roadmaps– iNEMI– CTR/MPC– JISSO


The Pace of Innovation is AcceleratingThe Pace of Innovation is AcceleratingToday packaging has become a crucial enabler for both “More Moore” as the industry enters the deep submicron regime and the functional diversification and heterogeneous integration which has been titled “More than Moore”.

In response to these dual challenges we have an unprecedented pace of innovation in assembly and packaging technologies.


Innovation in Wafer level PackagingInnovation in Wafer level PackagingWLCSP and Wafer Level Fan-Out technologies have become main stream. Future directions will be include multi-die (side by side and stacking) fanout. They are becoming an enabling part of the SiP technology portfolio providing:•Miniaturization•lower power•cost reduction•heterogeneous integration

Examples include complex PoPs, embedded Examples include complex PoPs, embedded components, integrated passives, and others. components, integrated passives, and others.


Future Directions in Wafer level Future Directions in Wafer level PackagingPackaging


Progress Continues in Wire Bond Progress Continues in Wire Bond TechnologyTechnology

The rising cost of gold is driving copper wire bonding to replace gold. Conversion from gold wirebond packages to copper requires: • Changes in almost all materials and wirebond equipment • New process engineering• New reliability science to addressing new failure mechanisms

Fine Pitch Copper wire bonds are now in Fine Pitch Copper wire bonds are now in volume productionvolume production


3D Stacking with Wirebonds3D Stacking with Wirebonds3D wirebond stacking with 50um thick wafer3D wirebond stacking with 50um thick wafer


Lead Free Requirements Demands Lead Free Requirements Demands New Interconnect TechnologyNew Interconnect Technology

Copper pillar has become the lead free bump metallurgy of choice for the fine bond pad pitch at deep submicron nodes. The technical challenges include:•New underfill materials

•New processes for cu pillar and under bump metallurgy (UBM)

•Design tools for copper pillar interconnect

This must be accomplished while maintaining This must be accomplished while maintaining adequate margins of safety for dielectric damage and adequate margins of safety for dielectric damage and

package integrity. package integrity.


Copper Pillar ArrayCopper Pillar Array


Expanded Coverage of Emerging Requirements for 2011:Expanded Coverage of Emerging Requirements for 2011:

Medical ElectronicsMedical Electronics• Medical electronics Categories to be addressed:

– Portable medical electronics– Implantable medical electronics (Parkinson’s disease symptom control)

• Selected Issues for Medical electronics – Power requirements: energy scavenging; wireless radiated power; batteries– Safety issues (voltage, biocompatibility, power delivery)– FDA certification– Reliability requirements– Environmental issues– Connectivity (wireless)– Optical components (cameras)– Microfluidics– Implantable micro-robotics – Sensors– MEMS



3D Integration3D Integration

• Selected Issues for 3D Integration– Die stacking methods

• Homogeneous stacking• Heterogeneous stacking

– Test challenges for 3D• Test access• Test cost

– Through silicon Vias– Thermal management for 3D structured– Power integrity– 3D SiP– Bonding methods– Codesign and simulation



InterposersInterposers

• Selected Issues for Interposers:– Systems integration for 2D and 3D– Interposer features

• Redistribution wiring• Passive networks• Thermal management• Stress management

– Materials selection• Si• Ceramic• Glass• Organics

cross section of a fully assembled package with functional devices

IP

package

TSV



Automotive ElectronicsAutomotive Electronics• Automotive electronics Categories to be addressed:

– Internal combustion– Hybrid– All electric

• Selected Issues– Communications (including optical networks)– Thermal management

• In cabin• Hostile environments

– Safety– Sensors– Controls for improved efficiency– Cost

One side air cooling

Cooling on both sides

Liquid immersion cooling



Thin Wafer and Die HandlingThin Wafer and Die Handling

• Selected Issues for Thin Wafer and Die Handling– Testing: contactors with ohmic contact without damage– Holding mechanisms

• Electrostatic chucks • Bernouilli chuck • Temporary bonding (sacrificial layer) • Vacuum chucks (porous ceramic chucks)

– Dicing of thin wafer– Warpage



Embedded ComponentsEmbedded Components• Embedded Component Categories to be addressed:

– Active devices– Passive devices

• Selected Issues for Embedded Components– Performance enhancement due to reduced distance between die and passives– Incorporation of additional functionality (heat pipes; wave guides)– Keep out area around embedded components – Charge source close to the die for current surge– Reduced size by placement of passives under die– Placement accuracy for small thinned die– 3D alignment tolerance for assembly– Improved resistance to shock– Thermal management



MEMS IntegrationMEMS Integration• MEMS Integration Categories to be addressed:

– Sensors– Accelerometers– RF Switches, Oscillators, and filters – Microfluidics– Optical

• Selected Issues for MEMS Integration– Low stress interconnect between MEMS device and package cavities – Low cost, high reliability mechanical mounting– Electrical and environmental connections – low electrical parasitic interconnect– Low cost hermetic cavities – Stress management

Microfluidic pump


Difficult ChallengesDifficult Challenges

Difficult Challenges ≥16 nm Summary of Issues

-Direct wire bond and bump to Cu or improved barrier systems bondable pads

- Dicing for ultra low k dielectric

-Bump and underfill technology to assure ultra low-κ/ air gap dielectric integrity

-Improved fracture toughness of dielectrics

-Interfacial adhesion

-Reliability of first level interconnect (increasing with decreasing contact pitch)

-Mechanisms to measure the critical properties (particularly for thin layers and interfaces)

-Redistribution processing for pad pitch below 50um

-Thermal management (for high power devices used in automotive and other areas)

-Wafer thinning and handling technologies

-TCE mismatch compensation for large die

Impact of BEOL including Cu/low κ on packaging

Wafer level Packaging


Difficult ChallengesDifficult ChallengesDifficult Challenges ≥16 nm Summary of Issues

-Models for Reliability prediction

-Rapid turn around modeling and simulation

-Integrated analysis tools for transient thermal analysis and integrated thermal mechanical analysis

-Electrical (power disturbs, EMI, signal and power integrity associated with higher frequency/current and lower voltage switching)

-System level co-design(cm to nm) is needed now (including mixed signal and simulation).

-EDA for “native” area array is required to meet the Roadmap projections.

-Low cost embedded passives: R, L, C

-Embedded active devices

-Quality levels required not attainable on chip

-Die size for high C, low L integrated circuit matching die size

-Wafer level embedded components

- Wafer/die handling for thin die (must address die warpage)

-Reliability

-stress impact on device performance and assembly yield

-Interconnect thickness and bonding for die stacking

-Testability (ohmic contacts without damage)

Coordinated design tools and simulators to address chip, package, and substrate co-design

Embedded components

Thinned die packaging


Difficult ChallengesDifficult Challenges

Difficult Challenges < 16 nm Summary of Issues

-Increased wireability at low cost

-Improved impedance control and lower dielectric loss to support higher frequency applications

-Improved planarity and low warpage at high process temperatures

-Low-moisture absorption

-Increased via density in substrate core

-Production techniques will require silicon-like production and process technologies

-Electromigration will become a more limiting factor.

-Thermal dissipation

Post CMOS switch devicesThe structures and materials employed will present serious challenges for packaging that will

need to be addressed during this Roadmap period. The specifics of the requirements and challenges are not known at this time.

High current density packages

Close gap between chip and substrate


Thank YouThank You

December 3, 2010 Public Conference MAKUHARI MESSE International Conference Hall Assembly and Packaging.

Documents

packaging slide

packaging technologies

wafer level packaging

medical electronics

richard grzybowski

richard arnold

heterogeneous integration

choon heung lee