DIGITAL ELECTRONICS LAB Ex. No:1 STUDY OF LOGIC GATES Date: AIM: To study about logic gates and verify their truth tables. APPARATUS REQUIRED: THEORY: Circuit that takes the logical decision and the process are called logic gates. Each gate has one or more input and only one output. Page No: 4 SL No. COMPONENT SPECIFICATIO N QTY 1. AND GATE IC 7408 1 2. OR GATE IC 7432 1 3. NOT GATE IC 7404 1 4. NAND GATE 2 I/P IC 7400 1 5. NOR GATE IC 7402 1 6. X-OR GATE IC 7486 1 7. NAND GATE 3 I/P IC 7410 1 8. IC TRAINER KIT - 1 9. PATCH CORD - 14
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
DIGITAL ELECTRONICS LAB
Ex. No:1
STUDY OF LOGIC GATESDate:
AIM: To study about logic gates and verify their truth tables.
APPARATUS REQUIRED:
THEORY:
Circuit that takes the logical decision and the process are called logic gates.
Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level
when any one of the inputs is low.
OR GATE:
Page No: 4
SL No. COMPONENT SPECIFICATION QTY
1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14
DIGITAL ELECTRONICS LAB
The OR gate performs a logical addition commonly known as OR function.
The output is high when any one of the inputs is high. The output is low level when
both the inputs are low.
NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both
inputs are high.
NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both
inputs are low. The output is low when one or both inputs are high.
X-OR GATE:
The output is high when any one of the inputs is high. The output is low when
both the inputs are low and both the inputs are high.
PROCEDURE:(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
AND GATE:
SYMBOL: PIN DIAGRAM:
Page No: 5
DIGITAL ELECTRONICS LAB
OR GATE:
NOT GATE:
SYMBOL: PIN DIAGRAM:
Page No: 6
DIGITAL ELECTRONICS LAB
X-OR GATE :
SYMBOL : PIN DIAGRAM :
2-INPUT NAND GATE:
Page No: 7
DIGITAL ELECTRONICS LAB
SYMBOL: PIN DIAGRAM:
3-INPUT NAND GATE :
NOR GATE:
Page No: 8
DIGITAL ELECTRONICS LAB
RESULT:
Thus the logic gates are studied and their truth tables are verified.
Ex. No: 2 DESIGN OF ADDER AND SUBTRACTOR
Page No: 9
DIGITAL ELECTRONICS LAB
Date:
AIM: To design and construct half adder, full adder, half subtractor and full
subtractor circuits and verify the truth table using logic gates.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 23
THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one
from the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above
circuit is called as a carry signal from the addition of the less significant bits sum from
the X-OR Gate the carry out from the AND gate.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a
time but a half adder cannot do so. In full adder sum output will be taken from X-OR
Gate, carry output will be taken from OR Gate.
HALF SUBTRACTOR:
Page No: 10
DIGITAL ELECTRONICS LAB
The half subtractor is constructed using X-OR and AND Gate. The half
subtractor has two input and two outputs. The outputs are difference and borrow. The
difference can be applied using X-OR Gate, borrow output can be implemented using
an AND Gate and an inverter.
FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full
subtractor the logic circuit should have three inputs and two outputs. The two half
subtractor put together gives a full subtractor .The first half subtractor will be C and A
B. The output will be difference output of full subtractor. The expression AB
assembles the borrow output of the half subtractor and the second term is the inverted
difference output of first X-OR.
LOGIC DIAGRAM:
HALF ADDER
TRUTH TABLE:
A B CARRY SUM
0011
0101
0001
0110
K-Map for SUM: K-Map for CARRY:
Page No: 11
DIGITAL ELECTRONICS LAB
SUM = A’B + AB’ CARRY = AB
LOGIC DIAGRAM:
FULL ADDER USING TWO HALF ADDER
TRUTH TABLE:
A B C CARRY SUM
00001111
00110011
01010101
00010111
01101001
K-Map for SUM: K-Map for CARRY:
Page No: 12
DIGITAL ELECTRONICS LAB
SUM = A’B’C + A’BC’ + ABC’ + ABC CARRY = AB + BC + AC
PROCEEDURE:(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT: Thus the half adder, full adder, half subtractor and full subtractor circuits
are designed and the truth tables are verified.
Page No: 15
DIGITAL ELECTRONICS LAB
Ex. No: 3
DESIGN AND IMPLEMENTATION OF CODE CONVERTORDate:
AIM: To design and implement 4-bit (i) Binary to gray code converter(ii) Gray to binary code converter(iii) BCD to excess-3 code converter(iv) Excess-3 to BCD code converter
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35
THEORY:The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion
circuit must be inserted between the two systems if each uses different codes for same
information. Thus, code converter is a circuit that makes the two systems compatible
even though each uses different binary code.
A code converter is a circuit that makes the two systems compatible even
though each uses a different binary code. To convert from binary code to Excess-3
code, the input lines must supply the bit combination of elements as specified by code
and the output lines generate the corresponding bit combination of code. Each one of
the four maps represents one of the four outputs of the circuit as a function of the four
input variables.
Page No: 16
DIGITAL ELECTRONICS LAB
A two-level logic diagram may be obtained directly from the Boolean
expressions derived by the maps. These are various other possibilities for a logic
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
Page No: 53
DIGITAL ELECTRONICS LAB
RESULT: Thus the 4 bit ripple counter mod 10/ mod 12 ripple counter circuits were
designed and verified successfully.
Ex. No: 10
DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN COUNTERDate:
AIM: To design and implement 3 bit synchronous up/down counter.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35
THEORY:A counter is a register capable of counting number of clock pulse arriving at its
clock input. Counter represents the number of clock pulses arrived. An up/down
Page No: 54
DIGITAL ELECTRONICS LAB
counter is one that is capable of progressing in increasing order or decreasing order
through a certain sequence. An up/down counter is also called bidirectional counter.
Usually up/down operation of the counter is controlled by up/down signal. When this
signal is high counter goes through up sequence and when up/down signal is low
counter follows reverse sequence.
K MAP:
STATE DIAGRAM:
Page No: 55
DIGITAL ELECTRONICS LAB
CHARACTERISTICS TABLE:
Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
LOGIC DIAGRAM:
Page No: 56
DIGITAL ELECTRONICS LAB
TRUTH TABLE:
InputUp/Down
Present StateQA QB QC
Next StateQA+1 Q B+1 QC+1
AJA KA
BJB KB
CJC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
Page No: 57
DIGITAL ELECTRONICS LAB
PROCEDURE:(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT: Thus the 3 bit synchronous up/down counter was designed and implemented
using the IC7476.
Page No: 58
DIGITAL ELECTRONICS LAB
Ex. No: 11
DESIGN AND IMPLEMENTATION OF SHIFT REGISTER Date:
AIM: To design and implement (i) Serial in serial out (ii) Serial in parallel out (iii) Parallel in serial out (iv) Parallel in parallel out
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35
THEORY:A register is capable of shifting its binary information in one or both directions
is known as shift register. The logical configuration of shift register consist of a D-
Flip flop cascaded with output of one flip flop connected to input of next flip flop. All
flip flops receive common clock pulses which causes the shift in the output of the flip
flop. The simplest possible shift register is one that uses only flip flop.
PIN DIAGRAM:
Page No: 59
DIGITAL ELECTRONICS LAB
LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:
TRUTH TABLE:
CLKSerial in Serial out
1 1 02 0 03 0 04 1 15 X 06 X 07 X 1
LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:
Page No: 60
DIGITAL ELECTRONICS LAB
TRUTH TABLE:
CLK DATAOUTPUT
QA QB QC QD
1 1 1 0 0 02 0 0 1 0 03 0 0 0 1 14 1 1 0 0 1
LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:
TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
Page No: 61
DIGITAL ELECTRONICS LAB
LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:
TRUTH TABLE:
CLK
DATA INPUT OUTPUT
DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT: Thus the shift registers were designed and implemented using IC7474 and
verified successfully.
Page No: 62
DIGITAL ELECTRONICS LAB
Ex. No: 12
SIMULATION OF ADDER AND SUBTRACTOR USING VERILOG HDLDate:
AIM: To write the Verilog HDL program for adder and subtractor circuit and
simulate it using ISE simulator.
HARDWARE& SOFTWARE REQUIRED: XILINK 9.1i SimulatorPC WITH WINDOWS-XP
THEORY: HALF ADDER:
From the verbal explanation of a half adder, we find that this circuit needs two binary inputs and two binary outputs. The input variables designate the augends and addend bits; the output variables produce the sum and carry. We assign symbol ‘a’ and ‘b’ to the inputs and S (for sum) and C (for carry) to the outputs. The truth table for the half adder is listed in table. The C output is 1 only when both inputs are 1. The S output represents the least significant bit of the sum.
The simplified Boolean functions for the two outputs can be obtained directly from the truth table. The simplified sums of products expressions are S= a’b + ab’ C= ab
The logic diagram of the half adder implemented in sum of products is shown in figure. It can be also implemented with an exclusive-OR and an AND gate as shown in figure. This from is used to show that two half adders can be used to construct a full adder.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of three inputs and two outputs. Two of the input variables, denoted by ‘a’ and ‘b’, represent the two significant bits to be added. The third input ‘c’ represents the carry from the previous lower significant position. Two outputs are necessary because the arithmetic sum of three binary digits ranges in value from 0 to 3, and binary 2 or 3 needs two digits. The two outputs are designated by the symbols S for
Page No: 63
DIGITAL ELECTRONICS LAB
sum and D for carry. The binary variable S gives the value of the least significant bit of the sum. The binary variable D gives the output carry. The truth table of the full adder is listed in table. The eight rows under the input variables designate all possible combinations of the variables. The output variables are determined from the arithmetic sum of the input bits. When all input bits are 0, the output is 0. The S output is equal to 1 when only one input is equal to 1 or when all three inputs are equal to 1. The D output has a carry of 1 if two or three inputs are equal to 1.
The input and output bits of the combinational circuit different interpretations at various stages of the problem. Physically, the binary signals of the inputs are considered binary digits to be added arithmetically to form a two-digit sum at the output. On the other hand, the same binary values are considered as variables of Boolean functions when expressed in the truth table or when the circuit is implemented with logic gates. The maps for the output of the full adder are shown in below.