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DDR3 Overview
Sebin Kollamana
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DDR Evolution
DDR3 overview
DFI 3.1
Verification of DDR physical layer and
controller
DDR4 overview
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DDR evolution
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SRAM Vs DRAM
Static Random Access Memory (SRAM) is a type of semiconductor memory where the word static
indicates that, unlike dynamic RAM (DRAM), it does not need to be periodically refreshed, as SRAMuses bistable latching circuitry to store each bit.
SRAM is still volatile in the conventional sense that data is eventually lost when the memory is not
powered.
SRAM is more expensive, but faster and significantly less power hungry (especially idle) than
DRAM. It is therefore used where either bandwidth or low power, or both, are principal
considerations
SRAMs are used as the primary caches in CPUs, data buffers of HDD etc
DRAMs stores each bit of data in a separate capacitor within an integrated circuit. Since real
capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed
periodically.
The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required
per bit, compared to six transistors in SRAM. This allows DRAM to reach very high density.
For economic reasons, the large memories(RAM) found in personal computers are DRAMs
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SDR and DDR - DRAMs
SDRAM has a synchronous interface, meaning that it waits for a clock
signal before responding to control inputs and is thereforesynchronized with the computer's system bus.
Single data rate SDRAM can accept one command and transfer one
word of data per clock cycle whereas DDR SDRAMs can transfer a
word per clock edge.
Single data rate SDRAM were once used widely as computer RAMs
but now replaced by DDR memories
SDRAM – Synchronous Dynamic Random Access Memory
DDR-SDRAM – Double Data Rate SDRAM
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DDR-DDR2-DDR3
Frequency supported : DDR - 100/133/166/200MHz DDR2 - 100-
533MHz DDR3 - 300-1066MHz Reduction in power consumption of 30% compared to DDR2 modules due to
DDR3's 1.5 V supply voltage, compared to DDR2's 1.8 V or DDR's 2.5 V.
Higher bandwidth made possible by DDR3's 8-bit wide prefetch buffer, incontrast to DDR2's 4-bit prefetch buffer or DDR's 2-bit buffer.
Typical latencies for a DDR2 device were 5-5-5-15 where as 7-7-7-20(tCAS-
tRCD-tRP-tRAS) for DDR3-1066 and 7-7-7-24 for DDR3-1333
DDR3 latencies are numerically higher because the clock cycles by whichthey are measured are shorter
DDR3 1066 – DDR3 working @533Mhz
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LPDDR2 – LPDDR3
Frequency supported: LPDDR - 0-200MHz LPDDR2 - 0-533MHz
Reduction in power consumption compared to DDR module.
LPDDR uses 1.8 V supply voltage Where as LPDDR2 uses 1.2V as supply
voltage (even less than DDR3’s 1.5V).
LPDDR devices use a single data rate architecture on the Command/Address
where as LPDDR2 devices use a double data rate architecture on the
Command/Address (CA) bus to reduce the number of input pins in thesystem.
LPDDR and LPDDR2-S2 devices have 2n prefetch DQ architecture.
LPDDR2 devices have 4n prefetch DQ architecture.
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DDR3
Terminology and Commands
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Functional Block Diagram
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Interface signals
• Clock – CK, CK# (input)
• RESET#
• Control Signals - CKE, CS#, RAS#, CAS#, WE# (input)
• Address Signals - BA0-BA2, A0-An (input)
• Data signals – D0 –Dn, DM (bi-directional)• Data Strobe – DQS, DQS# (bi-directional)
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DDR3 Commands
DDR2 commands are driven at single data rate, 1
command per clock
Control Signals - CKE, CS#, RAS#, CAS#, WE#
Address Signals - BA0-BA2, A0-An
Activate - Opens a particular row for Read/Write Access Pre-charge - Closes an open row in a particular bank or all
banks
Refresh
Self Refresh
Powerdown
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CAS Latency
CAS Latency is the delay, in clock cycles, between the registration of
a READ command and the availability of the first bit of output data.The CL can be set to 5-14 clocks, depending on the speed grade
option being used.
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Additive Latency
Delays the Read/Write commands internally by Additive latency
number of cycles
Additive Latency can be configured as zero, casl-1, casl-2
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Write Latency
The memory expects write data after write latency number of cycles
after the write command
Write latency can be configured in the range 5 to 12 depending on the
speed bin
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Burst Length
Read and write accesses to the DDR3 SDRAM are burst-oriented,
with the burst length being programmable to either four or eight.
The programmed burst length applies to both read and write bursts
Burst length can be programmed through the mode register or can be
controlled dynamically via a12
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Burst Type – Sequential, Interleaved
The ordering of accesses within a burst is determined by the burst length, the
burst type, and the starting column address
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Mode Register 0 (MR0)
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Mode Register 1 (MR1)
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Mode Register 2 (MR2)
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Mode Register 3 (MR3)
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Questions
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DDR3
Initialization
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Initialization
Assert reset for 200us
After de-asserting the reset, wait for 500us and then drive CKE high
Clocks (CK, CK#) need to be started and stabilized for at least 10 ns or 5tCK (which is larger) before CKE goes active
Once the CKE is registered “High” after Reset, CKE needs to becontinuously registered “High” until the initialization sequence is finished
After CKE is being registered high, wait minimum of Reset CKE Exit time,
tXPR, before issuing the first MRS command to load mode register.(tXPR=max (tXS ; 5 x tCK)
Issue MRS Command to load MR2 with all application settings
Issue MRS Command to load MR3 with all application settings
Issue MRS Command to load MR1 with all application settings and DLLenabled
Issue MRS Command to load MR0 with all application settings and “DLLreset”
Issue ZQCL command to starting ZQ calibration.
Wait for both tDLLK and tZQinit completed
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Initialization
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DDR3
Write and Read
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Write
A single write operation follows three steps Activate –
Write - Precharge
tRRD – time between successive row
access
tRCD – activation of a row to read/write
in that particular row
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Write ck/dq/dqs
1 cycle preamble, dq/dqs relation, 0.5 cycle postamble
tDQSS – time from posedge of ck to
posedge of dqs
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Data Input Timing
Due to routing imbalances, the DQ eye becomes very
small.
The DQ/DM eye has to meet the timing requirements –
tDS, tDH
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Back to Back Write
tCCD – command to command delay
Write commands are placed in such a way that the data
flows seamlessly
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Read
Activate – Read – Precharge
1 cycle read preamble, half cycle postamble
R d ti i
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Read timings
B k t b k d
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Back-to-back reads
Read command placing ensures that data flows
continuously
R d f ll d b W it
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Read followed by Write
Should avoid bus contention
Q ti
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Questions
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DDR3
Refresh, Self-Refresh, Powerdown
R f h
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Refresh
The DRAM requires REFRESH cycles at an average interval of 7.8μs
(maximum when TC ≤ 85°C or 3.9μs maximum when TC > 85°C).(tREFI - maximum average periodic refresh, tRFC – refresh to activate
period)
All banks must be precharged before entering the refresh.
A maximum of eight REFRESH commands can be posted to any
given DRAM, meaning that the maximum absolute interval betweenany REFRESH command and the next REFRESH command is nine
times the maximum average interval refresh rate.
R f h
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Refresh
S lf R f h
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Self-Refresh
The SELF REFRESH command is used to retain data in the DRAM,
even if the rest of the system is powered down. When in self refreshmode, the DRAM retains data without external clocking.
Self refresh mode is also a convenient method used to enable/disable
the DLL as well as to change the clock frequency.
Self Refresh
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Self-Refresh
Power Down
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Power Down
Entering power-down disables the input and output buffers, excluding
CK, CK#, ODT, CKE, and RESET#. NOP or DES commands are required until tCPDED has been
satisfied, at which time all specified input/output buffers are disabled.
(tCPDED – Command pass disable delay)
During power-down entry, if any bank remains open after all in-
progress commands are complete, the DRAM will be in active power-down mode. If all banks are closed after all in-progress commands are
complete, the DRAM will be in precharge power-down mode.
DLL will be on during Active powerdown whereas in Precharge
powerdown mode, DLL can be turned off (slow powerdown entry/exit)
Power Down (active)
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Power Down (active)
Clock Frequency Change
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Clock Frequency Change
The input clock frequency can be changed from one
stable clock rate to another under two conditions: selfrefresh mode and precharge power-down mode.
It is illegal to change the clock frequency outside of those
two modes
Clock frequency change during precharge
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C oc eque cy c a ge du g p ec a gepowerdown
Speed Bin
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Speed Bin
Timing parameters Example
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Timing parameters - Example
Timing parameters Example
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Timing parameters - Example
Questions
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Questions
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DDR3
Flyby topology and training
Flyby Topology
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Flyby Topology
32 bit DDR3 DIMM – Flyby Topology
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32 bit DDR3 DIMM – Flyby Topology
DQ[31:0]/DQS[3:0]
DQ[23:16]
, DQS[2]
DQ[31:24]
, DQS[3]DQ[15:8],
DQS[1]
DQ[7:0],
DQS[0]
DQ[23:16]
, DQS[2]
DQ[31:24]
, DQS[3]
DQ[15:8],
DQS[1]
DQ[7:0],
DQS[0]
DQ[23:16]
, DQS[2]
DQ[31:24]
, DQS[3]DQ[15:8],
DQS[1]
DQ[7:0],
DQS[0]
DQ[23:16]
, DQS[2]
DQ[31:24]
, DQS[3]DQ[15:8],
DQS[1]
DQ[7:0],
DQS[0]
CS#[0]CKE[0]CS#[0]CKE[0] CS#[0]CKE[0]CS#[0]CKE[0]
CS#[1]
CKE[1]
CS#[1]
CKE[1]CS#[1]
CKE[1]
CS#[1]
CKE[1]
CS#[2]
CKE[2]
CS#[2]
CKE[2]CS#[2]
CKE[2]
CS#[2]
CKE[2]
CS#[3]
CKE[3]
CS#[3]
CKE[3]CS#[3]
CKE[3]
CS#[3]
CKE[3]
Control Signals +
CK+ CKE + CS#
Write Leveling
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Write Leveling
The goal is to delay the write DQS/DQS# to match the
CK/CK#. DDR3 has write leveling to achieve this.1. Complete the initialization procedure
2. Enable write leveling mode using the mode register MR1
3. The phy/controller sends dqs pulse to the DRAM
4. DRAM samples the CK @ posedge of DQS and sendsthe result through DQ bus.
5. Phy/controller samples the DQ bus, evaluates the resultand decides whether to delay the DQS further or not
6. Steps 3 to 6 are repeated until the proper delay isdetermined
7. Exit write leveling using MR1
8. Resume operation
Mode Register 1 (MR1)
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Mode Register 1 (MR1)
Write Leveling – write DQS vs CK
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Write Leveling write DQS vs CK
Write Leveling
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Write Leveling
Write Leveling
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Write Leveling
Write Leveling
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Write Leveling
Read DQS gate training
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Read DQS gate training
The read dqs has a 0.9xCK read preamble and 0.5xCK
read postamble. The phy uses the dqs to capture the DQ
The dqs switches from valid to highZ to valid between
write/read.
The phy will open the gate only during the valid time to let
the dqs in.
The idea goal here is to find out the sweet spot for
opening the dqs gate for reads
Read DQS gate training
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Read DQS gate training
Read DQS gate training
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Read DQS gate training
1. Complete the initialization, do write leveling if required
2. Controller/phy issues read commands to the DRAM3. The DRAM responds by sending DQS and DQ (it is a
normal read operation, the DRAM doesn’t know thatgate training is happening)
4. The controller/phy evaluates the read dqs and delays thegate
5. Steps 2 to 4 are repeated until the gate is delayedsufficiently
6. Resume operation
Read DQ Eye Training
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Read DQ Eye Training
The read DQ eye becomes extremely small owing to theuncertainties on board, package, IO, clock jitter etc
The phy uses DQS to capture the read data (DQ)
The goal is to delay the DQS to find the sweet spot forsampling the DQ
1. Complete initialization, write leveling and gate training (ifrequired)
2. Use MR3 to set MPR read. This will make the DRAM to give apre-defined pattern as read data.
3. Issue read command to the DRAM. The DRAM returns thepredefined pattern as read DQ
4. The phy/controller will analyze the sampled dq and delays the
dqs if needed.5. Steps 3,4 is repeated until the pre-defined pattern is correctly
sampled.
6. Resume normal operation
Mode Register 3 (MR3)
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Mode Register 3 (MR3)
Read DQ vs DQS
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ead Q s QS
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DFI 3.1
What is DFI
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Defines the connectivity between a DDR memory
controller (MC) and a DDR physical interface (PHY) formemory devices.
Defines the signals, signal relationships, and timing
parameters required to transfer control information anddata to and from the DRAM devices over the DFI.
Supports an MC and PHY operating in either matched
frequency or a frequency ratio, or both.
DFI Interfaces
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Control Interface
Write Data Interface
Read Data Interface
Update Interface
Status Interface
Training Interface
Low Power Control Interface
DFI Interfaces
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DATA
PHY
Control Interface
Write data interface
Read data interface
Update interface
Status interface
Training interface
Low power control interface
DDR4 Specific interface
Currently this interface is
not part of DFI 2.1
protocol
DFI
Interface C o n t r o
l l e r
Leveling / Training Logic
CMD
PHY
DDR4 Features
Control Interface
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DFI
interface
DRAM
interface
Data Interface - write
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DFI
interface
DRAM
interface
Data interface - read
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Update Interface
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Status Interface
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Status Interface
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Status Interface
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Training interface
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Write leveling
Read gate training Read data eye training
The MC or the PHY may initiate any training operation.
Training may be executed during initialization, frequency change or
during normal operation.
The PHY can request training by driving the dfi_rdlvl_gate_req or
dfi_rdlvl_req or dfi_wrlvl_req
The MC must respond to any of these requests by asserting the
appropriate enable (dfi_rdlvl_en, dfi_wrlvl_en or dfi_rdlvl_gate_en)
Training request timing
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Read gate
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Read training in DFI training mode
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Write Leveling in DFI training mode
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Phy requested training mode
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PHY asserts the dfi_phylvl_req_cs_n[x] associated with the
chip select, and the MC grants the bus to the PHY for trainingusing the following sequence:
1. The MC places the DRAM associated with the requested chipselect in the IDLE state.
2. The MC idles the DFI bus.
3. The MC asserts dfi_phylvl_ack_cs_n[x]. When the PHY completes training for a given chip select, the
PHY uses the following sequence:
1. The PHY de-asserts the dfi_phylvl_req_cs_n[x] signalassociated with the specific chip select.
2. The MC de-asserts the dfi_phylvl_ack_cs_n[x] signals assoon as possible after all dfi_phylvl_req_cs_n signals arede-asserted.
Phy requested training mode
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Low power control
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If the request is acknowledged through the assertion of the
dfi_lp_ack signal, the PHY may enter a low power mode as long as
the dfi_lp_ctrl_req or dfi_lp_data_req signal remains asserted.
Once the dfi_lp_ctrl_req or dfi_lp_data_req signal is de-asserted,
the PHY must return to normal operating mode within the number of
cycles indicated by the dfi_lp_wakeup signal.
Frequency Ratio
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PHY transfers data at a higher data rate relative to the
DFI clock. MC has the option to execute multiple commands in a
single DFI clock cycle.
Supports 1:1 or 1:2 or 1:4 MC to PHY frequency ratio.
The MC -> PHY interface works on DFI clock and thePHY works on DFI PHY clock.
The frequency of DFI PHY clock and the memory clock
should always be the same.
The DFI clock and the DFI PHY clock should be phasealigned.
Frequency ratio - clocks
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Ratio – 1:2
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Ratio 1:2
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Ratio – 1:4
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Ratio – 1:4
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Ratio – 1:4
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Questions
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Verification of DDR PHY/Controller
Verification of DDR PHY
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Verification of Integrated controller and PHY
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DRAM/DIMM model configurations
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Intra-rank and inter-rank flyby delays
The DIMM models (for eg: DENALI) have options to control inter-rank( theflyby delay between multiple chip selects) and intra-rank(flyby delay betweenmodules in the same chip select). Verification need to ensure that bothdelays are configured while doing training tests
DQ/DQS uncertainty
The DRAM specification allows some uncertainty on the read DQS and DQbits. Ensure that the DRAM model has this feature and that it is not turned offby configuration. This is critical for training tests
DRAM initialization
The DRAM initialization typically takes long time to complete due to reset,cke requirements. However after the initial sanity testing, these parameterscan be configured to a lower value to speed up the simulation
Differential signal skew The DRAM model can be configured for tolerating a small amount of skew
between the differential signals – CK/CK#, DQS/DQS#. But ensure that thetolerance limit is within the specifications.
Sources of uncertainty in the testbench
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PLL jitter – spread spectrum clocking
The PLL which generates the clock to the PHY might have some jitter characteristics. This will affect the training logic and the DLLand the CK/CK# going to the DRAM. Hence the verificationenvironment has to model this jitter or use the PLL model itself forgenerating the clock.
Board skew and routing delays (static)
In real world application, there would be certain board delay andskew between the DRAM signals. It is good to model these in theverification environment
Board/IO jitter (dynamic)
The IO/package jitter, board jitter, ISI etc can be translated to asuitable random variation and could be applied on the DRAMinterface signals.
Some jitter can break the training logic, however the phy can do ashort training to compensate this.
Some interesting scenarios
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DLL characterization (DLL inside the PHY) The PHY might be having DLLs and slave delay lines to take care of the dqs, dqs gate delays.
Ensure that the delay lines support the highest and the lowest frequency of operation. Alsomake sure that the delay line can support the maximum board/flyby delay. This becomessignificant while doing GLS at the best corner
DLL ON/OFF mode (DLL inside the DRAM) During normal operation the DLL will be ON, however for low frequency applications such as
FPGA prototyping, the DRAM might be operated in DLL OFF mode.
READ tightly followed by WRITE and then followed by READ
This will test how fast the PHY can switch between READ/WRITE Also tests the valid-highZ-valid switching in the DQS/DQ bus.
Back to back READ/WRITE to test the throughput, power consumption
Dynamically changing the frequency. This will test DLL lock/unlock,powerdown/self-refresh features. Phy has to retrain following a frequency change.
Increasing the board delay/flyby delay can test the read FIFO inside the PHY
Questions
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DDR4
Additional Interface Signals
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C0, C1, C2 (input) – Chip ID, is part of the command code
ACT_n (input) – Activation command RAS_n/A16, CAS_n/A15, WE_n/A14 (input) – Multifunction pins. Axx
when ACT_n is low
DM_n/DBI_n/TDQS_t (input/output) – Data Mask / Data Bus
Inversion/ Termination DQS depending on mode register settings
BG0-BG1 (input) – Bank Group inputs
PAR (input) – Command and Address parity input
ALERT_n (input/output) – CRC Error Flag /Command Address parity
error Flag / as Input during connectivity test
TEN – Connectivity test mode enable
Command Truth Table
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Command Truth table
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Training procedures
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Write Leveling
DQ eye training MPR settings
MPR Read
MPR Write
4 MPRs are available, controlled through MR3
ZQ Calibration
DQ Vref calibration
A MRS command to the mode register bits 5:0 of MR6 are used
to program the vref value. VrefDQ training mode is
enabled/disabled by A7 of MR6 and training range can be
selected by A6 of MR6
Features
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Per DRAM addressability
Allows programmability of a given device on a rank. As anexample, this feature can be used to program different ODT or
Vref values on DRAM devices on a given rank
CAL (CS_n to Command Address latency)
CAL gives the DRAM time to enable the CMD/ADDR receivers
before a command is issued. Once the command and the
address are latched, the receivers can be disabled. For
consecutive commands, the DRAM will keep the receivers
enabled for the duration of the command sequence
Features
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Error Correction (CRC and Parity)
CRC DDR4 supports CRC for write operation, and doesn’t support
CRC for read operation
CRC Error mechanism shares the same Alert_n signal for
reporting errors on writes to DRAM. The controller has no way to
distinguish between CRC errors and Command/Address/Parity
errors other than to read the DRAM mode registers
Features
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Parity
Only for Command [A2:A0] of MR5 are defined to enable or disable C/A Parity in the
DRAM
PAR signal is used to send the parity
Alert_n to flag error
Programmable read and write preamble
Read and write preambles programmable through Mode registers
Both the postambles are fixed
Features
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Connectivity test
The DDR4 memory device supports a connectivity test (CT)mode, which is designed to greatly speed up testing of electrical
continuity of pin interconnection on the PC boards between the
DDR4 memory devices and the memory controller on the SoC
Allows test patterns to be entered in parallel into the test input
pins and the test results extracted in parallel from the test outputpins of the DDR4 memory device at the same time
Features
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ODT
The ODT feature is designed to improve signal integrity of the memory channel byallowing the DRAM controller to independently change termination resistance for
any or all DRAM devices.
Controller can control each RTT condition with WR/RD command and ODT pin
RTT values have priority as following.
1. Data Termination Disable
2. RTT_WR (Termination value for a write regardless of ODT pin)
3. RTT_NOM (value when ODT is high)
4. RTT_PARK (default value when OCT is LOW)
if there is WRITE command along with ODT pin HIGH, then DRAM turns on
RTT_WR not RTT_NOM, and also if there is READ command, then DRAM
disables data termination regardless of ODT pin and goes into Driving mode.
References
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MT41J256M4 – www.micron.com
JESD79-4 –
www.jedec.org DFI 3.1 – www.ddr-phy.org
http://www.micron.com/http://www.jedec.org/http://www.ddr-phy.org/http://www.ddr-phy.org/http://www.ddr-phy.org/http://www.ddr-phy.org/http://www.jedec.org/http://www.micron.com/
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Sebin Kollamana
Thank You