Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 1 DC to DC Power Conversion R. Ely and M. Garcia-Sciveres LECC2006 Valencia – Sept 25-29, 2006 • Introduction • Series Scheme • Charge Pumps • Tests on DC2DC_0 chip • Plans
Jan 15, 2016
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 1
DC to DC Power ConversionR. Ely and M. Garcia-Sciveres
LECC2006Valencia – Sept 25-29, 2006
• Introduction• Series Scheme• Charge Pumps• Tests on DC2DC_0 chip• Plans
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 2
From the Power Board to the outside world
Adapter board … instead of the “bus board”.
Pos 1
Pos 2
Pos 3Pos 4
Pos 6Pos
5
Pos 7Pos 8
Pos 9
Pos 10
Pos 11
Pos 12
Pos 13
The SCT cable is also made by Raydex !
VDD
VDDA
Atlas pixel cable
70% Power
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 3
High Power + Low Voltage = MASS + $$$
• Pixel Electronics operate at ~2V => large current• ~2A low voltage per module (1744 modules) -3488A!
0.1 1 10 100
Distance (m)
Vo
ltag
e (V
)
24
86
Voltage between +ve and ground leads vs. distance from module
Remote sensing rad.-hard linear regulators necessary for safe operation
$$$
mass
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 4
Next time, deliver power at higher voltage
• Migration to smaller feature size in IC design means lower voltage. The .13u process that is considered for a new pixel front end will be either 1.2 or 1.5 vt.
• Need scheme to reduce voltage at the detector
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 5
Two Options
•Serial Power
•Work started with Pixels. Demonstrated with present modules by Bonn group
•Picked up for SCT modules by Marc Weber at RAL
•Incorporated into stave prototypes by RAL and LBNL
•DC-DC converters
•Proposed by LBNL
•Initial simulations shown at Genova (details later)
•Prototype switches fabricated and tested
Sept. 27, 2006 Valencia 2006 Ely, Garcia-Sciveres 6
Serial powering or parallel power bus with DC-DC conversion
Alternatives to IP
M1 M2 M3
M1 M2 M3
M1 M2 M3
IP
PP with DC-DC conversion
(LBL)
SP
(RAL, lbl)
Analog and digital voltage
Constant current for both analog and
digital power
Sept. 27, 2006 Mark Weber - Carmel 2006 7
Four elements
Current source
Shunt regulator and power device (digital power)
Linear regulator (analog power)
AC or opto-coupling of signals
How does SP work?
Sept. 27, 2006 Mark Weber - Carmel 2006 8
Regulators
8V
4V
4V
0V
Chain of modules at different voltages
Chips on a module are connected in parallel (as usual)
analog ground, digital ground and HV ground are tight together for each module (as usual) floating HV supplies
Sept. 27, 2006 Mark Weber - Carmel 2006 9
Serial powering of six ATLAS SCT modules
RAL clean room. This was also used for QA of ~800 SCT modules
Sept. 27, 2006 Mark Weber Carmel 2006 10
Noise performance of 6 SCT modules
<ENC> Vs module number for IP and SP with 6 modules
1420
1440
1460
1480
1500
1520
1540
1560
1580
1600
755 663 159 628 662 006
Module #
<E
NC
> IP
SP
Precise measurements; noise performance of SP is excellent
Sept. 27, 2006 Mark Weber Carmel 2006 11
Future R&D program on powering schemes
Goal: be ready for implementation of advanced SP and DC-DC conversion PP systems in a realistic module assembly in ~ 3 years
Can distinguish three phases:
Generic studies (as presented here and in Carl’s talk) to identify crucial features and challenges “easy”, affordable, “fun”
Develop radiation-hard custom electronics (ABC_Next chip); build and test systems with large number of modules significant effort, serious engineering
Implementation of power distribution schemes on advanced supermodule prototypes “service”, crucial to establish supermodule electrical performance
Sept. 27, 2006 Carl Haber - Carmel 2006 12
Prototyping: Phase 1 Test-bed•Based on existing ATLAS ABCD chip and Run2b R&D*•Develop ATLAS hybrid specific for multi-module•1 sensor + hybrid = 1 module (hybrid glued to Si)•6 modules per side + interface card•Modules linked by embedded bus cable •Total length 66 cm, 6144 channels•Built around carbon fiber/foam laminate
•Measure multi-module performance with ATLAS electronics•Explore assembly and mechanical aspects
*T.Akimoto et al, NIM A 556 (2006) 459-481
Sept. 27, 2006 Carl Haber - Carmel 2006 13
Plans
• Further study of serial powering…• Develop a DC-DC test stave• Preparation for an ATLAS SLHC 1 meter
stave– Aim for construction and test in early 2007– Mechanical design and assembly fixtures (Miller)– 3 cm ATLAS detectors (BNL)– New bus cables and hybrid (with serial power)– ABCD-Next chip? (Dabrowski et al)
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 14
DC-DC Converter options
• Inductor Buck converter – typical in industry– We would have to worry about magnetic field, EMI from
fringe fields, and would have to make our own air-core inductors.
• Switched Capacitor array– not common in industry except for divide by 2– Seems natural choice for us- fewer worries (see below).
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 15
Buck Converter
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 16
DC-DC Converters for Delivery of Low Voltage and High Currents for use in Magnetic field and Radiation environments.
S. Dhawan, D. Lynn b, H. Neal a, R. Sumner c, M. Weber d and R. Weber
Buck RegulatorMicrel 2285 with
538 nH Air Coil
Output Ripple: 20 mV 8 MHz
0. 5 amp LoadOff
On
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 17
Switched Capacitor Options
• Most commercial applications multiply low supply voltage to drive a display. They require low current – switch resistance is not a problem
• We wish to reduce voltage and supply large currents – switch resistance is important
• There are many circuits – M. Makowski and D. Maksimovic’ have shown that with n capacitors the highest voltage ratio which can be achieved is given by the nth Fibonacci number. We have simulated one.
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 18
Divide by 4 Stack
• Phase 1 - Charge
1
+-
1
2
2
+-
1
2
2
+-
1
2
2
+- Load
Vd
Vd
+ -+ - + -+-
Load
+-
+-
+-
+-
Load
• Phase 2 - Discharge
4 capacitors – 10 switches
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 19
CMOS Transistor Switches
• Austria Microsystems H35 Process– Feature size 0.35μ– 3 gate oxides– Vds up to 50 vts– Bulk isolation – Gate oxide breakdown vt > 8vts
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 20
AMS H35 Transistors
Device Name
Min. L
(μ)
Max.
Vgs(vt)
Max
Vds(vt)
On Res.
L = min
W= 50m
Cg (pf)
NMOSI 0.5 3.6 3.6 0.06 125
NMOS50T
0.5 3.6 50 0.54 364
PMOS50T
1.0 3.6 50 0.73 369
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 21
Figures of Merit(for divide by n)
• Voltage efficiency - εv = n*Vout / Vin
– Vout is a function of the load = Vin / n for no load
• Current efficiency - εI = Iout / n*Iin
– Charge is lost charging the gate capacitance of the switches
• Power efficiency - εp = εv * εI
• Ripple - less than Iout*period/C
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 22
Divide by 5 Stack
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 23
V eff and I eff vs period
0
0.2
0.4
0.6
0.8
1
1.2
0 0.2 0.4 0.6 0.8 1
period (us)
effi
cien
cy
V effI eff
Efficiency versus Frequency
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 24
Power Efficiency
Power Efficiency vs transistor width
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0 5 10 15 20 25 30 35
width (mm)
eff
icie
ncy
Peff 8mz
Peff 5mhz
Peff 2.5 mhz
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 25
DC Conversion Conclusions
• At an operating freqency of 5mhz(Co = 4.7uf, C1 = 0.2uf– Voltage efficiency ~.84– Current efficiency ~.92– Ripple = 1.2%– Output impedance = 0.25 ohms (25mv / 100ma)
• Clock generator will reduce efficiency by 10%
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 26
First test chipDC2DC_0 – Test Switches
Divide by 4 Stack AMS 0.35u HV process
Iout = 250 maNo internal clock gen1/4th Size to save moneyPurpose:• Test circuit concept• Characterize transistors• Test radiation hardnessSubmitted March 2006
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 27
DC2DC_0 Performance
• For Ro = 10 ohms– Voltage efficiency = .578– Iin / Iout ~1 - very high
• The large currents are due to a parasitic bipolar in Modni!
• Problem: bulk-drain is forward biased during discharge cycle
• Fix with Bulk bias control
Vout vs Vdd
0
0.5
1
1.5
2
3 5 7
Vdd (vts)
Vout
(vts
)
Ro = 10ohmsRo = 100ohms
Vdd/8Vdd/4
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 28
Transistor Measurements
• Use Agilent 4156c• Measure Modni, Modn50t and Modp50t• Compare with models supplied by AMS for
hspice and eldo.• In general the models for the n channel
devices compare poorly. Especially at low Vds and short channel
• Of most interest is rds, d(vds)/d(ids), at low vds
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 29
Modni .5u/2.4mm
• The difference in Ids between meas and sim at Vg = 0.8 can be explained by a shift of the threshhold by 40mv
• Rds measured is 45% greater than Rds simulated
Modni: resistance vs vg
1
10
100
1000
0 0.5 1 1.5 2 2.5
Vg (vts)
Res
ista
nce
(o
hm
s)
Curve Tracer
Hspice
2.37 ohms
1.63 ohms
Modni: Ids vs Vds by VG
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0 0.2 0.4 0.6 0.8 1 1.2
Vds (vts)
Ids
(am
ps) Vg = .8
Vg =1.6
sim Vg=.8
sim Vg=1.6
DVg = 40 mv
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 30
Modn50t .5u/12.5mm
• The comparison at Vg=.8 agrees with the AMS docs – the model is bad for intermediate Vds
• Rds measured is 40% greater than Rds simulated
Modn50t: Ids vs Vds by VG
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
0 0.2 0.4 0.6 0.8 1 1.2
Vds (vts)
Ids
(am
ps) Vg = .8
Vg =1.6
sim vg=.8
sim vg=1.6
Modn50t: resistance vs vg
1
10
100
0 0.5 1 1.5 2 2.5
Vg (vts)
Res
ista
nce
(o
hm
s)Curve Tracer
Hspice3.42 ohms
2.43 ohms
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 31
Modp50t .5u/12.5mm
• The disagreement at large Vds can be explained by a .12 v shift in the threshhold
• Rds measured is 35% greater than Rds simulated
Modp50t: resistance vs vg
1
10
100
1000
10000
0 0.5 1 1.5 2 2.5
Vg (vts)
Res
ista
nce
(o
hm
s)Curve Tracer
Hspice
4.58 ohms
3.9 ohms
ModP50t: Ids vs Vds by VG
-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
0 0.2 0.4 0.6 0.8 1 1.2
Vds (vts)
Ids
(am
ps)
Vg =2.0
sim vg=2.0
Vg=1.2
sim Vg=1.2
sim Vg=1.1
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 32
Irradiation of DC2DC_0
• Use 55 Mev protons from the 88” cyclotron
• 20 namp up to 1015 p/cm2
• “The best laid schemes of mice and men gang aft agley” - Burns
Reschedule in October
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 33
Conclusion
• We have to increase the size of the switches by 40% to achieve the low resistance required
• This is within the parameter variations advertised for the process
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 34
Future Plans
• Characterize several more chips
• Irradiate DC2DC_0 to 50 Mrad
• Submit a working prototype, DC2DC_1 next November (hopefully!)
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 35
DC2DC_1
• Designed by P. Denes• Divide by 4
• Iout ~ 1 amp (if we can afford it)
• Vout variable from 1-2 vts• Substrate Bias control• Voltage reference block• Level shifted clock drivers• Low dropout regulator
Sept. 27, 2006 LECC2006 - Valencia -- Ely, Garcia-Sciveres 36
Finally, for example,Implement divide by 4 power converter
• Line drop from 16v to 10v with ¼ the mass• 872 amps instead of 3488A!• Deliver 62% of input power instead of 25%.
10 10.7 11.1 11.9513.45
15.95
0
5
10
15
20
0.1 1 10 100
Distance (m)
Volta
ge (V
)
Remote sensing rad.-hard linear regulators necessary for safe operation
$$$
mass