DC Lab_22_4-2013

Department of Electronics and Communication Engineering Digital Communications Lab

EXPERIMENT: 1TIME DIVISION MULTIPLEXING

AIM:

1. To study the operation of time division multiplexing.2. To study the mechanism of level1 (Three wire method) transmission.3. To study the mechanism of level2(Two wire method) transmission.4. To study the mechanism of level3(One wire method) transmission.

APPARATUS:

1. Time division multiplexing modulator and demodulation trainer2. C.R.O3. Patch Cards

THEORY:

One of the greatest benefits to derive from the sampling is that of time division multiplexing (TDM). By inter leaving samples of several source wave forms in time; it is possible to transmit enough information to a receiver, via only one channel to recover all message waveform. This process is called TIME DIVISION MULTIPLEXING.The time allocated to one sample of one message is called a time slot. The time interval over which all message are sampled at least once is called a frame. This position of the time slot not used by any of the sampling pulse is called the guard time. In practical system, some time slot may be allocated to other function like signaling, monitoring, synchronization etc.

Synchronization:

To maintain proper position of sample pulses in the multiplexer it is necessary to synchronize the sampling process. Because the sampling operation is usually electronic, there is typically a clock pulse. In that it serves as a reference for all pulses. In TDM there are three levels of synchronization.

Level 1 (Three wire method):In this method the transmitter clock and synchronization pulses are directly linked to the receiver.

Level 2 (Two wire method):In this method the transmitter synchronization pulse are directly linked to the receiver, But the clock pulses for receiver was derived from the transmitted information.

Level 3 (One wire Method):In this method the synchronizing and clock pulses for the receiver are derived form the transmitted (TDM) information.

Since due to higher costs, for long distance communication level 1 and level 2methods are not economical hence level 3methods is used.

PROCEDURE:

1. Connect the TDM module for three wire method.2. Connect 250Hz, 500Hz,1KHz and DC signal of in function generator to the transmitter.3. Observe the outputs at transmitter and receiver.4. Connect the TDM module for two wire method (By placing PLL input switch at L2 position) and repeat 2 and 3.5. Connect TDM module for one wire method (By placing PLL I/P switch at L3 position) and adjust threshold control for distortion less O/p and repeat 2 and 3.

Methods of synchronization:

OBSERVATIONS:

CHANNELINPUT SIGNALRECEIVER OUTPUT

AMPLITUDE VP-P VOLTSFREQUENCY (Hz)AMPLITUDE VP-P VOLTSFREQUENCY (Hz)

MODEL WAVEFORMS:

RESULT: Operation of TDM is studied. Level 1,2,3 transmission methods are studied.

EXPERIMENT: 2

PULSE CODE MODULATION

AIM:To study pulse code modulation communication system.

APPARATUS:

1. PCM transmitter module (DCL-03)2. PCM receiver module (DCL-04)3. Regulated Power Supply4. Digital Multimeter

THEORY:

Pulse Code Modulation is a technique, where analog signal issampled and samples are transmitted as coded words of finite bit (Binary Digit) length. In pulse code modulation, first the samples are quantized, and they encoded before transmitting as a serial bit stream.Quantizing is the process where the samples are made to assume one of the finite sets of discrete levels. Here is the first the whole signal level is divided into a fixed number of discrete levels. The samples are rounded-off to the nearest discrete level. Then corresponding to the level chosen a code word is assigned to the sample this process is called ENCODING. The process of quantizing and encoding together is called ANLOG TO DIGITAL CONVERSION.The parallel data word available after the analog to digital conversion is converted to a serial data stream after coding and sent through the channel. This coded data stream is said to be PCM coded data and is transmitted by the serially by the PCM transmitter.For recovering the data stream,first the serial data is converted to parallel finite bit length code word. Then receiver identifies the code word and assigns the signal levels for the received code word. The functional block that performs this task of accepting sequences of binary digit and generating appropriate sequences of levels is called DIGITAL TO ANALOGCONVERSION to sequences of levels that appear at the output of the D/A converter is filtered to recover back the base band signal.

Synchronization Techniques:

For the recovery of information from the transmitted data stream, the transmitter and receiver should be perfectly synchronized. Synchronization between transmitter and receiver is achieved in two stages.1. Bit synchronization2. Frame synchronization

Bit Synchronization:

To recover the information from the serial bit stream, the receiver has to know if the received data bit at a given instant of time is one or zero. For determining the data bit, the clocks of transmitter and receiver are to be perfectly synchronized.

For achieving synchronization normally known as bit synchronization the clocks of the transmitter (Tx clock)can be sent along with the data. This calls for an additional channel for clock transmission. So normally a phase locked loop(PLL) is used at the receiver for recovering the clock. This phase locked loop is made to lock with the incoming data whose VCO reproduced the clock at the receiver.

Frame Synchronization:

For ensuring proper recovery of code words and proper assignment of channel informations of the demultiplexing unit, the receiver has to know where the data begins exactly for this, at the start of every frame, a 14bit pseudo ransom sequence(PRBS) is sent, which forms the header of the data pattern. Subsequently what follows is data corresponding to the number of channels multiplexed. The frame sync pulse can be sent by the transmitter along with the data and clock to achieve frame synchronization. But normally it is not sent, since it calls for an additional channel.To recover the frame sync at the receiver from the data stream, a sequence similar to the one transmitted, is generated at the receiver.The PRBS detector compares the generator sequence with the incoming data and locks wherever the incoming data matches with the generated sequence. The PRBS sequence is chosen is such a way that it has minimum correction with the data bits. Once the PRBS detector is locked, it generates a frame sync pulse.BLOCK DIAGRAM:

PROCEDURE:

1. Connect the circuit as shown in the block diagram. Make connections between transmitter (DCL-03) and receiver (DCL-04) and put the clock generator in FAST mode.2. Select parity selection switch to NONE mode on both kits transmitter and receiver. And ensure that all the switched faults are in OFF position. On both transmitter and receiver kits.3. Connect a DC voltage from regulated power supply to the transmitter I/P and vary its voltage from 0 to 1V and 4 to 5V insteps of 40mV.4. Take observation at:

On Transmitter (DCL 03):A. input signal to ADC(10MVx out)B. ADC output (B1 to B7)

On Receiver (DCL 04):A. Input to DAC (B1 TO B7)B. Output to DAC (AT DAC OUTPUT)

5. Draw a graph between A/D input voltage and A/D output data. Find the step size.

OBSERVATIONS:

ADC i/p mVADC OUTPUTDAC INPUTDAC o/p mV

B1B2B3B4B5B6B7B1B2B3B4B5B6B7

MODEL GRAPH:

RESULT: PCM system is studied. Outputs are observed.

EXPERIMENT: 3

DIFFERENTIAL PULSE CODE MODULATION AND DEMODULATION

AIM:

To Study differential pulse code modulation technique

APPARATUS:

ADCL 07 KitConnecting chordsPower supply20MHz Dual Trace OscilloscopeNote: Keep the switch faults in OFF position.

THEORY:DPCM is a good way to reduce the bit rate for voice transmission. However it causes some other problems that deals with voice quality. DPCM quantizes and encodes the difference between a previous sample input signal and a current sample input signal. DPCM quantizes the difference signal using uniform quantization. Uniform quantization generates an SNR that is small for small input sample signals and large input sample signals. Therefore, the voice quality is better at higher signals.

The first part of DPCM works exactly like PCM (that is why it is called differential PCM). The input signal is sampled at a constant sampling frequency (more than the input frequency). Then these samples are modulated. At this point, the DPCM process takes over. The sampled input signals are stored in what is called a predictor. The predictor takes the stored sample signal and sends it through a differentiator. The differentiator compares the previous sample signal and sends its difference to quantizing and coding phase of PCM (this phase can be a uniform quantizing or companding with A-law or-law). After quantizing and coding, the difference signal is transmitted to its final destination. At the receiving end of the network, everything is reversed. First the difference signal is decoded and de-quantized. This difference is added to sample signal stored in the predictor and send through a low-pass filter that reconstructs the original input signal.

BLOCKDIAGRAM:

PROCEDURE:

1. Refer to the block diagram and carry out the following connections and switch settings.2. Connect power supply in proper polarity to the kit ADCL 07 and switch it ON.3. Keep the clock frequency at 512KHz, by changing the jumper position of JP1 in the clock generator section. 4. Keep the amplitude of the onboard sine wave, of frequency 500Hz to 1Vpp

DPCM MODULATION:

5. Connect the 500Hz sine wave to the IN post of Analog Buffer.6. Connect OUT post of Analog Buffer to IN post of DPCM modulator section.7. Observe the sample output at the given test point. The input signal is sampled at the clock frequency of 16KHz.8. Observe the linear predictor output at the PREDICTED OUT post of the linear predictor in the DPCM modulation section.9. Observe the differential pulse code modulated data (DPCM ) at the DPCM OUT post of the DPCM modulator section. 10.Observe the DPCM data at DPCM post by varying input signal from 0 to 12V.

DPCM DEMODULATION:

11. Connect the DPCM modulated data from the DPCM OUT post of the DPCM modulator to the IN post of the DPCM demodulator.12. Observe the demodulated data at the output of summation block.13. Observe the integrated demodulated data at the DEMOD OUT post of the DPCM demodulator.14. Connect the demodulated data from the DEMOD OUT post of the DPCM demodulator to the IN post of the low-pass filter.15. Observe the reconstructed signal at the OUT post of the filter. Use RST switch for clear observation of output.16. Now, simultaneously reduce the clock frequencies from 512KHz to 256KHz, 128KHz and 64KHz by changing the jumper position of JP1 and observe the difference in the DPCM modulated and demodulated data. As the frequency of clock decreases, DPCM demodulated data at DEMOD OUT becomes distorted.17. Observe various waveforms as mentioned below (Fig.1.2)

OBSERVATION:

ON KIT ADCL 07 Observe the following waveforms on the oscilloscope and plot on the paper.

1. 500Hz, 1Vpp input sine wave.2. Sampled out at the provided test point SAMPLER OUT.3.Linear predictor out at PREDICTED OUT post.4.DPCM data DPCM OUT post.5.Line interface out at the given output test point of interface block in DPCM demodulation.6.Demodulated DPCM data at the point of point of summation block in DPCM demodulation.7.Integrated demodulated data at the DEMOD OUT post of DPCM demodulator.8.Reconstructed sine wave at the OUT post of the filter.9.Observe the data at different clock rates.

MODEL GRAPHS AND WAVEFORMS:

RESULT: Differential PCM modulation and demodulation are studied .Outputs are observed at different clock rates.

EXPERIMENT: 4

DELTA MODULATION AND DEMODULATION

AIM:

1. To Study the construction of delta modulation and demodulation circuit.2. To observe the output of integrator, transmitted bit sequence and demodulator output.3. To verify the slope overloading condition.

APPARATUS:

1. Delta Modulation and Demodulation trainer2. C.R.O

THEORY:

Delta modulation is a system of digital modulation developed after pulse code modulation. In this system at each sampling time, say the Kth sampling time, the difference between the sampling time K and the sample value at the previous sampling time(K-1) is just encoded into just a single bit.A serious problem in delta modulation schemes arises due to the rate of raise overloading. When input signal is changing, then integrator output follows the input signal is step wise fashion as long as successive samples of input signal do not differ by an amount greater than the step size , then the integrator can no longer follow the input signal. This type of overload is not determined by the amplitude of message signal but grater by it, slope. Hence the name comeslope overload.

BLOCK DIAGRAM:

PROCEDURE:

Delta Modulator:

1. Connect the clock signal from clock generator, to the delta modulator clock input.2. In order to ensure for correct operation of the system connect data input of delta modulator to 0 Volts DC. Then adjust the level control in bipolar converter, until the integrator output(at TPQ) will be a triangle wave centered around 0I,e the output from the transmitters BISTABLE circuit(at TP7) will now be a steam of 1 and 0.3. Now apply a sinusoidal modulating signal of amplitude 1vp-p and observe the output of delta modulator (At TP7) and integrator output (at TP9).4. Repeat the step 3 with modulating signal amplitude.

Slope overloading condition:

1. Increase the modulating signal amplitude until, the integrator output is a perfect triangle and the modulator output is a stream of 1 or 0.2. Find the modulating signal amplitude at that condition. Verify the slope overloading condition with theoretical value.

OBSERVATIONS:

Modulating signal frequency (fx)= ___________________ Clock or sampling frequency (fs)= ___________________ Step Size ()= ________________ At slope overloading condition, the amplitude of modulating signal:Theoretical =______________ Practical = _______________

MODEL GRAPH:

RESULT: Construction of Delta modulation and demodulation are studied. Slope overloading condition is verified.

EXPERIMENT: 5

FREQUENCY SHIFT KEYING

AIM:To find the construction of FSK modulator and demodulator circuit and their operation.

APPARATUS:

1. FSK modulator and demodulator trainer2. C.R.O3. Patch Cards

THEORY:

Binary FSK is a form of constant amplitude angle modulation and the modulating signal is a binary pulse stream that varies between two discrete voltage levels but not continuous changing analog signal. In FSK the carrier amplitude (Vc) remain constant with modulation and the carrier radian frequency (c) shift by an amount equal to /2. The frequency shift (/2) is proportional to the amplitude and polarity of the input binary signal. For example a binary 1 could +1 Volt producing frequency shift of +/2 and -/2 respectively. The rate at which the carrier frequency shift is equal to the rate of change of the binary input signal Vm(t)(that is the input bit rate). Thus the output carrier frequency deviates (shift) between c+/2 and c-/2 at the rate equal to fm.BLOCK DIAGRAM:

PROCEDURE:

1. Measure the frequency and amplitude of the carrier signal.2. Connect the modulator circuit shown in the fig., and select data by using dip switches.3. Observe the output of FSK modulator on the CRO and find the frequency of the carrier where 1 is transmitted and 0 is transmitted.4. Repeat 2 and 3 for different input data values.5. Connect the output of modulator to demodulator and observe the output of demodulator. We can observe that the output of demodulator is similar to transmitted data.

OBSERVATIONS:

1. Carrier Signal Amplitude = _________________ 2. Carrier Signal Frequency = _________________ 3. Carrier Signal Frequency (fmax) = _______________ (1) is transmitted)4. Carrier Signal Frequency(fmin)= __________________ (0 is transmitted)

Frequency Deviation (f)=

Demodulation:

DATA INPUTDEMODULATOR OUTPUT

0101010111000110001101001110011100110011

MODEL WAVEFORMS:

RESULT: Construction of FSK modulator and demodulator circuit and their operation are studied.

EXPERIMENT: 6

PHASE SHIFT KEYING

AIM:

To study the construction of PSK Modulator and demodulator circuit and theiroperation.

APPARATUS:

1. PSK Modulator and Demodulator trainer2. C.R.O3. Patch Cards

THEORY:

To transmit the digital data from one place to another, we have to choose the transmission medium. The simplest possible method to connect the transmitter to the receiver with a piece of wire. This works satisfactorily for shot distance in some cases. But for long distance communication and in situations like communication feasible. Here we hence to Opt for the radio transmission.It is not possible to send the digital data directly over the antenna because the antenna of practiced size works on very high frequencies, much higher than our data transmission rate.To be able to transmit the data over antenna, we have to module the signal i.e. Phase Shfit, frequency or amplitude etc., is varied in accordance with the digital data. At receiver we separate the signal from digital information by the process of demodulation. After this process we are left with high frequency signal (Called as carrier signal) which we discard and the digital information, which we utilize.The variation of particular parameter variation of the carrier wave give rise to various modulation techniques. Some of the basic modulations techniques are ASK,FSK,PSK,DPSK AND QPSK.

Phase Shift Keying (PSK):

Phase Shift Keying is a relatively new system, ion which the carrier may be phase shifted by +900 for a mark, and by -900 for a space. PSK has a number of similarities to FSK in many aspects, as in FSK, frequency of the carrier is shifted according to the modulating square wave.

BLOCK DIAGRAM:

PROCEDURE:

1. Connect the modulator circuit as shown in the fig.2. Observe the output of modulator for different data input.3. Connect the demodulator circuit as shown in the fig. 4. Observe the demodulator output for different data input

OBSEVASTION:

DATA INPUTDEMODULATOR OUTPUT

1010110101

1010010100

1100011000

1000010000

MODEL GRAPH:

RESULT:Construction of PSK Modulator and demodulator circuit and their operation are studied.

EXPERIMENT: 7

DIFFERENTIAL PHASE SHIFT KEYING

AIM:

To study operation of differential phase shift keying modulation and demodulation techniques.

APPARATUS:

1. DPSK Modulation and Demodulation trainer.2. C.R.O3. Patch Cards.

THEORY:

The DPSK is a non-coherent version of PSK. The DPSK eliminates the need of coherent response signal at the receiver by combining two basic operations at the transmitter.1. Differential encoding of the input binary wave2. Phase shit keyingThe DSPK transmitter and receiver are equipped with storage capability, So that it can measure the relative difference between the wave forms received during two successive bit intervals.In the transmitter circuit the output of modulator(i,e with 180 phase shift carrier) is 0 when the present data bit d(t) and previous modulator output bit b(t-Tb) are equal or it is equal 1 when d(t) and b(t-Tb) are different, because b(t) is generated according to the rule.

b(t)= d(t) b(t-Tb)

BLOCK DIAGRAM:

PROCEDURE:

1. Apply a data input to the modulator and observe the output of modulator and compare with theoretical value.2. Connect the modulator input to demodulator and compare the demodulator output with modulator data input.3. Repeat 2 and 3 for different data input

OBSERVATION:

CASE-I

DATA INPUT d(t)1100110000

B(t-Tb)0100010000

DIFFERENTIAL DATA OUTPUT b(t)1000000000

DEMODULATOR OUTPUT1100110000

CASE-II

DATA INPUT d(t)1111000000

B(t-Tb)0101000000

DIFFERENTIAL DATA OUTPUT b(t)1010000000

DEMODULATOR OUTPUT1111000000

CASE-III

DATA INPUT d(t)1100000000

B(t-Tb)0100000000

DIFFERENTIAL DATA OUTPUT b(t)1000000000

DEMODULATOR OUTPUT1100000000

CASE-IV

DATA INPUT d(t)1010101010

B(t-Tb)0110011001

DIFFERENTIAL DATA OUTPUT b(t)1100110011

DEMODULATOR OUTPUT1010101010

MODEL GRAPH:

RESULT: Operation of differential phase shift keying modulation and demodulation techniques are studied. Output waveforms are observed.

EXPERIMENT: 8COMPANDING

AIM:Implementation of -law companding and expansion of signal.

PROGRAM:

#include #include #define M 255Float orignal [100], x[100], y[100], com[100], ex[100];Void main (){int 1;float amp;intsgn[100], sgn_y[100];FILE *fp;fp=fopen (D:\\ M_low_companding.text,wr);fprintf(fp, \ Ninput sine\ t COMPANDING\ t OUTPUT SINE\n);printf(Enter amplidude level=);scanf(%f,&amp);for (i=0; i0.0)sgn[i]=1;else{if(x[i]