DC E-meter SMPS design using LM5017 in Isolated buck topology ...

Application ReportSNVA711–April 2014

DC E-Meter SMPS Design Using LM5017 in Isolated BuckTopology for Telecom Shelters

Singh Harmeet

ABSTRACTA cell site/telecom shelter consists of electronic infrastructure which includes base station (BTS),microwave radio equipment, switches, antennas, transceivers for signal processing and transmission, andnon-electronic infrastructure which includes tower, shelter, air-conditioning equipment, diesel electricgenerator, battery, electrical supply and so on.

The AC and DC energy consumption for different operators and competitors depends on the loadconnected to it. DC energy consumptions for loads like BTS, Microwave, and so on is calculated using aDC energy meter by connecting appropriate shunts in the negative path of loads. The voltage drop acrossthe shunt is fed to DC energy meter input terminals. The DC Energy Meter is a micro-controller basedproduct which measures Battery DC voltage, 4 channels DC currents for different operators and displaysthem on a 16x2 backlit LCD.

The DC Energy Meter also requires an isolated RS-485 port for communication with the master deviceusing MODBUS-RTU protocol. This calls for two output power supplies; a non-isolated +5 V at 200mA–400 mA, and an isolated +5 V at 100 mA for RS485 interface with input DC voltage varying from 12 Vto 75 V as the batteries can be 24 V or 48 V.

An isolated buck converter (Fly-Buck™) uses a synchronous buck converter, LM5017, with coupledinductor windings to create isolated outputs. Isolated converters utilizing Fly-Buck topology use a smallertransformer, no need for an optocoupler or auxiliary winding as compared to a Flyback converter, resultingin a smaller solution size and cost.

This application note presents a step-by-step procedure for designing a two-output 2.6-W isolated buckconverter. For understanding of the operation of Fly-Buck topology, refer to application Note SNVA674BAN-2292 Designing an Isolated Buck (Fly-Buck) Converter.

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Contents1 Two Output Isolated Buck Design ......................................................................................... 3

1.1 Feedback Resistors ................................................................................................ 31.2 Frequency Selection................................................................................................ 31.3 VCC and Bootstrap Capacitor ...................................................................................... 41.4 Input Capacitor ...................................................................................................... 41.5 UVLO Resistors ..................................................................................................... 41.6 Output Diode ........................................................................................................ 41.7 Coupled Inductor Design .......................................................................................... 41.8 Output Capacitor .................................................................................................... 51.9 Ripple Components Rr, Cr, Cac .................................................................................. 6

2 Conclusion .................................................................................................................... 93 References ................................................................................................................... 9Appendix A Experimental Results ............................................................................................. 10

List of Figures

1 Two Output Isolated Buck Reference Schematic........................................................................ 32 Current Waveforms for COUT1 Ripple....................................................................................... 63 Secondary Current Waveforms for COUT2 Ripple Calculation........................................................... 64 Type III Ripple Circuit ....................................................................................................... 75 Complete DC Energy Meter Power Supply Schematic ................................................................. 86 Efficiency versus IOUT1 at IOUT2 = 50 mA .................................................................................. 107 Efficiency versus IOUT1 at IOUT2 = 100 mA................................................................................. 108 Load Regulation of VOUT1 at IOUT2 = 50 mA............................................................................... 109 Load Regulation of VOUT1 at IOUT2 = 100 mA ............................................................................. 1110 Steady State Waveform (VIN = 12 V, IOUT1 = 400 mA, IOUT2 = 100 mA)............................................... 1111 Steady State Waveform (VIN = 24 V, IOUT1 = 400 mA, IOUT2 = 100 mA)............................................... 1212 Steady State Waveform (VIN = 48 V, IOUT1 = 400 mA, IOUT2 = 100 mA)............................................... 1213 Steady State Waveform (VIN = 75 V, IOUT1 = 400 mA, IOUT2 = 100 mA)............................................... 1314 VOUT1 Rise Waveform at IOUT1 = 400 mA and IOUT2 = 100 mA .......................................................... 1315 VOUT1 Ripple at IOUT1 = 400 mA and IOUT2 = 100 mA ..................................................................... 14

List of Tables

1 DC Energy Meter Power Supply Design Specifications ................................................................ 22 Coupled Inductor Details.................................................................................................... 53 Bill of Materials of Complete Schematic .................................................................................. 9

Table 1. DC Energy Meter Power Supply Design Specifications

Design SpecificationsInput voltage range (VIN) 12 V–75 VPrimary output voltage (VOUT1) 5 VSecondary output voltage (VOUT2) 5 VPrimary load current (IOUT1) 400 mAPrimary load current (IOUT2) 100 mA

2 DC E-Meter SMPS Design Using LM5017 in Isolated Buck Topology for SNVA711–April 2014Telecom Shelters Submit Documentation Feedback


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OUTSW

ON

Vƒ

K R=

´

MAXSW(MAX)

ON(MIN)

Dƒ

T=

MAXSW(MAX)

OFF(MIN)

1 Dƒ

T

-

=

OUTFB2

FB1

V 1.225VR

R 1.225V

-

=

FB2 FB1OUT

FB1

R RV 1.225V

R

+

= ´

12V - 75V

GND GND

VOUT1

VOUT2

Np

Ns

RrCr

Cac

D2

RUV2

RUV1

COUT1

GND

VIN

UVLO

RON FB

VCC

BST

SW

9

LM5017

CIN

COUT2

D1

CVCC

CBST

RONRFB2

RFB1

VIN

T1

www.ti.com Two Output Isolated Buck Design

Figure 1. Two Output Isolated Buck Reference Schematic

1 Two Output Isolated Buck Design

1.1 Feedback ResistorsThe output voltage (VOUT) is set by two external resistors (RUV1, RUV2). The regulated output voltage iscalculated as follows:

(1)

(2)

Choosing RFB1 = 1 kΩ gives RFB2 = 3.08 kΩ

1.2 Frequency SelectionAt the minimum input voltage, the maximum switching frequency of LM5017 is restricted by the forcedminimum off-time (TOFF (MIN)) as given by:

(3)

DMAX is the ratio of output voltage to minimum input voltage, that is, setting DMAX = 5/12 and TOFF (MIN) as200 ns gives fSW(MAX) as 2.9 MHz.

Similarly, at maximum input voltage, the maximum switching frequency of LM5017 is restricted by theminimum TON as given by:

(4)

DMIN is the ratio of output voltage VOUT to max input voltage, that is, setting DMIN = 5/75 and TON(MIN) is 100ns gives fSW(MAX) as 600 kHz.

Resistor RON sets the nominal switching frequency based on Equation 5:

(5)



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OUT2 OUT1 F

N2V V V

N1= -

( ) UV2VIN

UV1

RI UVLO, rising 1.225V 1

R

æ ö= ´ +ç ÷

è ø

IN HYS UV2V (HYS) I R= ´

OUT(MAX)IN

SW IN

IC

8 ƒ V³

´ ´ D

Two Output Isolated Buck Design www.ti.com

where K = 1 x 10–10. Operation at high switching frequency results in lower efficiency while providing thesmallest solution. For this example a conservative 150 kHz was selected, resulting in RON = 333 kΩ.Selecting a standard value for RON = 330 kΩ results in a nominal frequency of 152 kHz.

1.3 VCC and Bootstrap CapacitorThe VCC capacitor provides charge to the bootstrap capacitor as well as internal circuitry and low side gatedriver. A good value for CVCC is 1 μF, 16 V as per the data sheet (SNVS783). The same value is chosenhere.

The bootstrap capacitor provides charge to the high-side gate driver. A good value for CBST is 0.01 μF,16 V as per the data sheet. The same value is used here.

1.4 Input CapacitorInput capacitor should be large enough to limit the input voltage ripple:

(6)

Choosing a ΔVIN = 0.5 V gives a minimum CIN = 0.86 μF. A standard value of 2.2 μF is selected. The inputcapacitor should be rated for the maximum input voltage under all conditions. A 100 V, X7R dielectricshould be selected for this design.

The input capacitor should be placed directly across VIN and RTN (pin 2 and 1) of the IC. If it is notpossible to place all of the input capacitors close to the IC, a 0.47 μF capacitor should be placed near theIC to provide a bypass path for the high frequency component of the switching current. This helps limit theswitching noise.

1.5 UVLO ResistorsThe UVLO resistors RUV1 and RUV2 set the UVLO threshold and hysteresis according to the followingrelationship:

(7)

and

(8)

Where IHYS = 20 μA. Setting UVLO hysteresis of 2.0 V and UVLO rising threshold of 11.5 V results in RUV1= 14.3 kΩ and RUV2 = 120 kΩ. Selecting standard value of RUV1 = 14 kΩ and RUV2 = 120 kΩ results inUVLO threshold and hysteresis of 11.7 V and 2.5 V, respectively.

1.6 Output DiodeThe isolated output VOUT2 is linked with VOUT1 by Equation 9:

(9)

Putting VOUT2 = 5.5 V, VF = 0.5 V, VOUT1 = 5 V gives N2/N1 = 1.2

The reverse voltage across the output diode is VOUT2 + VIN max.

This comes out to be 80.5 V. With margin a 100-V Schottky DLFS1100-7 is selected.

1.7 Coupled Inductor DesignA coupled inductor or a flyback-type transformer is required for this topology. Energy is transferred fromprimary to secondary when the synchronous switch of the buck is ON.

The peak inductor ripple current is given by:



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LOUT

SW ripple

IC

8 ƒ V

D=

´ ´ D

( )IN(MAX) OUT OUTL1

SW IN(MAX)

V V VI

L1 ƒ V

-D =

´

( )IN(MAX) OUT OUT

L1 SW IN(MAX)

V V VL1

I ƒ V

-=

D ´

L1 OUT1 OUT2

N2I 0.7 I I 2

N1

æ öD = - - ´ ´ç ÷

è ø

L1sw(peak) L1(peak) OUT1 OUT2

IN2I I I I

N1 2+ +

D= =


(10)

Using Equation 10 for the peak inductor current equation, the maximum inductor current ripple that can betolerated is given by

(11)

Substituting IOUT1 = 0.4 A, IOUT2 = 0.1 A and N2/N1 = 1.2 gives ΔIL1 = 0.36 A

Using Equation 10 for the peak-to-peak inductor current ripple equation, the minimum inductor value isgiven by:

(12)

Substituting various values in Equation 12 gives L1 as 86.4 µH. For our design, a 100-μH value isselected for primary inductance.

For this chosen primary inductance, the primary inductor current ripple during TON is given by Equation 13.

(13)

Choosing primary inductance as 100 µH gives ΔIL1 = 0.31 A.

Table 2 lists the coupled inductor details in EPCOS EE13 core, N87 material.

Table 2. Coupled Inductor Details

Flyback Transformer –Ferrite CoreCore Bobbin Type Material PinsEE1304 N87 or 8 pins vertical/horizontal

EquivalentWinding Start Pin End Pin Turns Wire AWG InductanceWinding 1 1 4 24 30x4 100 µH ±5%Winding 2 8 5 29 30

Insulation 1,4 Shorted–5,8 1.5 kV Ensure proper insulation tapes are used between theshorted windings.

Winding Instructions: (Assuming same direction of winding in all cases.)Winding 1 Start with pin 1, take 4 strands of 30-AWG wire and make 24 turns ending

at pin 4Winding 2 Start on pin 8 and make 29 turns with 1 strand of 30-AWG wire and end at

pin 5. Spread the winding evenly across the length of the core bobbin.

1.8 Output CapacitorThe output capacitor is selected to minimize the capacitive ripple across it. The maximum ripple isobserved at maximum input voltage and is given by:

(14)

Where ΔVripple is the voltage ripple across the capacitor. Substituting ΔVripple = 50 mV gives COUT1 = 5.16μF.

Figure 2 shows the primary winding current waveform (IL1). The reflected secondary winding current addsto the primary winding current. Because of this, the output voltage ripple is not the same as in a non-isolated buck converter. The output capacitor value calculated in Equation 14 should be used as thestarting point. A better approximation of the primary output capacitor is given by:



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OUT2 ON(MAX)OUT2

OUT2

I TV

C

´D =

( )N2out2 ON(MAX)N1

OUT1OUT1

I TV

C

´ ´D =


(15)

Equation 15 gives voltage ripple as 64 mV.

Keeping DC bias, temperature and aging factor into consideration, 10 μF standard value is selected. AnX5R or X7R type capacitor with a voltage rating 16 V or higher should be selected.

Figure 2. Current Waveforms for COUT1 Ripple

Figure 3 shows a simplified waveform for secondary output current (IOUT2) and the current in the secondarywinding.

Figure 3. Secondary Current Waveforms for COUT2 Ripple Calculation

The secondary output current (IOUT2) is sourced by COUT2 during on time TON. The secondary outputcapacitor ripple voltage is calculated using Equation 16:

(16)

Therefore, targeting 250 mV at VOUT2 gives COUT2 as 1.1 μF. The standard value 2.2 µF is chosen takingcare of DC bias, temperature and aging effect. Higher ripple current has been taken as the LDO is used atVOUT2 for precise regulation. In this case, the LP2985-50 a 150 mA low-drop and low-noise LDO is chosen.

1.9 Ripple Components Rr, Cr, CacType 3 ripple method uses Rr and Cr and the switch node (SW) voltage to generate a triangular ramp.This triangular ramp is ac coupled using Cac to the feedback node (FB). Since this circuit does not use theoutput voltage ripple, it is ideally suited for applications where low output voltage ripple is required.



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I dV

C dt=

( )IN OUTV VI

Rr

-=


Figure 4. Type III Ripple Circuit

The design procedure for Type III ripple circuit is fairly simple. The impedance of the integrator capacitorCr should be small compared to the feedback divider impedance at the desired switching frequency. Sincethe divider in this case is around 750 Ω (1 kΩ in parallel with 3.08 kΩ) the impedance for Cr was chosento be roughly 100 Ω at 150 kHz. That calculates to around 10 nF. Since VIN – VOUT is very large comparedto the ripple voltage being produced you can think of the resistor Rr as being a current source.

The current I is given by:

(17)

The desired ripple voltage chosen to be 50 mV pk-pk. A charging capacitor obeys the following:

(18)

At 75 V input the on time is 444 ns.

The dV term is the 50 mV ripple, and C is 10 nF. Solving for I yields approximately 1.13 mA.

Rr = (75 V – 5 V) / 1.13 mA, so use Rr = 62 kΩ.

The AC coupling capacitor Cac should be 4 to 5 times larger than the integrator so a 0.1 μF was chosen.None of these values are very critical.



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12V - 75V

GND

VOUT1

VOUT2

5V@400mA

5V@100mA

DNP

1 4

8 5

U1

SW

EN

D2

R1120k

R214K

C11

10uF

R102K

1 GND

2 VIN

3 UVLO

4 RON 5FB

6VCC

7BST

8SW

99

LM5017

C12.2µF

100V

C50.47µF

C42.2µF

D1

ICGND

FB

C61uF

C20.01µF

16V

R3

330K R4

3.08K

R5

1K

VIN

GND

C80.1uF

C9

2200pF

C7

0.01µF

R8

62K

T1

100uH EE13

1 VIN

2 GND

3 ON/ 4BYPS

5VOUT

U2

LP2985A-50DBV

C3 2.2µF


The final schematic for the isolated power supply is shown in Figure 5.

Figure 5. Complete DC Energy Meter Power Supply Schematic



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www.ti.com Conclusion

Table 3. Bill of Materials of Complete Schematic

Item Description Mfg. Part Number Package ValueU1 Sync Switching Texas Instruments LM5017 SO PowerPAD-8 100V, 0.6A

RegulatorU2 LDO Texas Instruments LP2985-50DBVR SOT23-5 5V 150mAT1 Coupled Inductor Custom Made STD 100µH 0.7AD1 Schottky Diode Diodes Inc. DLFS1100-7 Pwr-DI123 100V 1AC1 Ceramic Capacitor TDK C3225X7R2A225K 1210 2.2µF 100V X7RC2 Ceramic Capacitor TDK C1608X7R1C103K 603 0.01 µF 16V X7RC3 Ceramic Capacitor AVX 1206Y226KAT2A 1206 2.2µF 16V X7RC4 Ceramic Capacitor AVX 1206Y226KAT2A 1206 2.2µF 16V X7RC5 Ceramic Capacitor Murata GRM21BR72A474KA73L 805 0.47µF 100V X7RC6 Ceramic Capacitor TDK C1608X7R1C105K 603 1 µF 16V X7RC7 Ceramic Capacitor TDK C1608X7R1C103K 603 0.01 μF 16V X7RC8 Ceramic Capacitor AVX 0603YC104KAT2A 603 0.1 μF 16V X7RC9 Ceramic Capacitor Johanson 202R29W222KV4E 1808 2200pF 2000VC11 Ceramic Capacitor AVX 1206Y107KAT2A 1206 10µF 16V X7RR1 Resistor Vishay/Dale CRCW0805120KFKEA 805 120kΩ, 1%R2 Resistor Vishay/Dale CRCW0805014KFKEA 805 14kΩ, 1%R3 Resistor Vishay/Dale CRCW0805330KFKEA 805 330kΩ, 1%R4 Resistor Panasonic ERJ-3EKF3081V 603 3.08kΩ, 1%R5 Resistor Panasonic ERJ-3EKF1001V 603 1kΩ, 1%R8 Resistor Panasonic ERJ-3EKF6201V 603 62kΩ, 1%R10 Resistor Panasonic ERJ-6GEYJ202V 805 2kΩ, 1%

2 ConclusionA detailed design procedure along with the experimental results were presented for a 2.6-W, two-outputFly-Buck power supply for a DC energy meter with a primary output 5 V and an isolated output 5 V forRS485 interface using a 100 V synchronous buck regulator IC LM5017. An isolated buck converter can beused to replace a flyback converter for low-power isolated regulator applications with potential savings incomplexity, number of components, and cost. If the load requirement is less, then the devices in the samefamily LM5018 and LM5019 can be considered for reducing the cost still further.

3 References1. LM5017: 100V,600mA Constant On-Time Synchronous Buck Data Sheet (SNVS783)2. AN-2292 Designing an Isolated Buck (Fly-Buck) Converter (SNVA674B)3. AN-1481 Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT)

Regulator Designs (SNVA166A)



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Appendix A Experimental Results

A.1 Efficiency

Figure 6. Efficiency versus IOUT1 at IOUT2 = 50 mA

Figure 7. Efficiency versus IOUT1 at IOUT2 = 100 mA

A.2 Load Regulation

Figure 8. Load Regulation of VOUT1 at IOUT2 = 50 mA



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www.ti.com Waveform at SW Node

Figure 9. Load Regulation of VOUT1 at IOUT2 = 100 mA

A.3 Waveform at SW Node

Figure 10. Steady State Waveform (VIN = 12 V, IOUT1 = 400 mA, IOUT2 = 100 mA)



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Waveform at SW Node www.ti.com





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www.ti.com VOUT Slope


A.4 VOUT Slope

Figure 14. VOUT1 Rise Waveform at IOUT1 = 400 mA and IOUT2 = 100 mA



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VOUT Ripple www.ti.com

A.5 VOUT Ripple

Figure 15. VOUT1 Ripple at IOUT1 = 400 mA and IOUT2 = 100 mA



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DC E-meter SMPS design using LM5017 in Isolated buck topology ...

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