Dc biasing of bjt

DC Biasing of BJTs

BiasingBiasing

Biasing:Biasing: T The DC voltages applied to a transistor in order to turn it on so that it can amplify the AC signal.

Operating PointOperating Point

The DC input establishes an operating or quiescent point called the Q-pointQ-point.

The Three States of OperationThe Three States of Operation

• Active or Linear Region OperationActive or Linear Region OperationBase–Emitter junction is forward biased

Base–Collector junction is reverse biased

• Cutoff Region OperationCutoff Region OperationBase–Emitter junction is reverse biased

• Saturation Region OperationSaturation Region OperationBase–Emitter junction is forward biasedBase–Collector junction is forward biased

No matter what type of configuration a transistor is used in, the basic relationships between the currents are always the same, and the base-to-emitter voltage is the threshold value if the transistor is in the “on” state

BC

CBE

BE

IIIII

VV

)1(

7.0

• The operating point defines where the transistor will operate on its characteristics curves under dc conditions.

• For linear (minimum distortion) amplification, the dc operating point should not be too close to the maximum power, voltage, or current rating and should avoid the regions of saturation and cutoff

DC Biasing CircuitsDC Biasing Circuits

• Fixed-bias circuit• Emitter-stabilized bias circuit• Voltage divider bias circuit• DC bias with voltage feedback

I. Fixed BiasI. Fixed Bias

• The fixed-bias configuration is the simplest of transistor biasing arrangements, but it is also quite unstable•For most configurations the dc analysis begins with a determination of the base current

•For the dc analysis of a transistor network, all capacitors are replaced by an open-circuit equivalent

Fixed-bias circuit

The dc equivalent circuit of the fixed bias circuit where the capacitor is replaced with an open-circuit

The Base-Emitter LoopThe Base-Emitter Loop

From Kirchhoff’s voltage law:

+VCC – IBRB – VBE = 0

Solving for base current:

B

BECCB R

VVI

Collector-Emitter LoopCollector-Emitter Loop

Collector current:

BIIC

CCCCCE RIVV


0 CCCCCE VRIV

Example: Determine the following for the fixed-bias configuration of the figure shown:

(a) IBQ and ICQ (b) VCEQ (c) VB and VC (d) VBC

= 75

SaturationSaturation• Saturation conditions are normally avoided because the base-collector junction is no longer reverse-biased and the output amplified signal will be distorted

•For a transistor operating in the saturation region, the current is a maximum value for the particular design. Change the design and the corresponding saturation level may rise or drop

•The highest saturation level is defined by the maximum collector current as provided by the specification sheet

SaturationSaturation

00

satCC

CECE I

VIVR

C

CCC R

VIsat

SaturationSaturation

When the transistor is operating in saturation, current through the transistor is at its maximum possible value.

CRCCV

CsatI

V 0CEV

In the previous example, the saturation level for the network is given by:

mAkV

RVIC

CCCsat

45.52.2

12

Load Line AnalysisLoad Line Analysis

CCCCCE RIVV

The variables IC and VCE are related by the equation:


IICsatCsat

ICC = VCCCC / RCC

VCECE = 0 V

VVCEcutoffCEcutoff

VCECE = VCCCC

ICC = 0 mA

The Q-point is the operating point:• where the value of RB sets the value of IB

• that sets the values of VCE and IC

The end points of the load line are:

Circuit Values Affect the Q-PointCircuit Values Affect the Q-Point

[Movement of the Q-point with increasing level of IB]


[Effect of an increasing level of RC on the load line the Q-point]


[Effect of lower values of VCC on the load line the Q-point]

II. Emitter-Stabilized Bias CircuitII. Emitter-Stabilized Bias Circuit

Adding a resistor (RE) to the emitter circuit stabilizes the bias circuit.

Base-Emitter LoopBase-Emitter Loop


0 RI-V-RI- EEBEBBCC V

0R1)I(-V-RI-V EBBEBBCC Since IE = ( + 1)IB:

EB

BECCB 1)R(R

V-VI

Solving for IB:



0 CCVCRCI CEV EREI

Since IE IC:

)R (RI– V V ECCCCCE

Also:

EBEBRCCB

CCCCECEC

EEE

V V RI– V VRI - V V V V

RI V

Example: Determine the following for the emitter bias network of the figure shown:

(a) IB (b) IC (c) VCE (d) VC (e) VE (f) VB (g) VBC

+16 V

= 75

Improved Biased StabilityImproved Biased Stability Stability refers to a circuit condition in which the currents and voltages will remain fairly constant over a wide range of temperatures and transistor Beta () valuesAdding RE to the emitter improves the stability of a transistor

IB(A) IC(mA) VCE(V)75 30.24 2.27 9.91

100 28.81 3.63 9.11

[For Emitter Bias Case]

IB(A) IC(mA) VCE(V)75 47.08 3.53 4.23

100 47.08 4.71 1.64

[For Fixed Bias Case]

Saturation LevelSaturation Level

EC

CCC RR

VIsat

Load-line AnalysisLoad-line Analysis

VCEcutoff:: ICsat:

The endpoints can be determined from the load line.

mA 0 IV V

C

CCCE

ERCRCCV

CI

CE V 0V

)( ECCCCCE RRIVV

III. Voltage Divider BiasIII. Voltage Divider Bias

This is a very stable bias circuit.

The currents and voltages are nearly independent of any any variations in .

Exact Analysis:

21 || RRRTh 21

22 RR

VRVE CCRTh

)( ECCCCCE RRIVV

0 EEBEThBTh RIVRIE

Applying Kirchhoff’s voltage law in the clockwise direction in the Thevenin network,

ETh

BEThB RR

VEI)1(

(Substituting IE = (+1)IB)

Approximate Analysis:

Approximate AnalysisApproximate Analysis Where IB << I1 and I1 I2 :

Where RE > 10R2:


21

CC2B RR

VRV

E

EE R

VI

BEBE VVV

EECCCCCE RI RI V V

)R (RIV VII

ECCCCCE

CE

Voltage Divider Bias AnalysisVoltage Divider Bias Analysis

Transistor Saturation LevelTransistor Saturation Level

EC

CCCmaxCsat RR

VII


Cutoff:Cutoff: Saturation:Saturation:

mA0IVV

C

CCCE

V0VCE

ERCRCCV

CI

IV. DC Bias with Voltage Feedback IV. DC Bias with Voltage Feedback

Another way to improve the stability of a bias circuit is to add a feedback path from collector to base.

In this bias circuit the Q-point is only slightly dependent on the transistor beta, .

Base-Emitter LoopBase-Emitter Loop

)R(RRVV

IECB

BECCB

From Kirchhoff’s voltage law:From Kirchhoff’s voltage law:

0RI–V–RI–RI– V EEBEBBCCCC

Where IWhere IBB << I << ICC::

CIBICICI'

Knowing IKnowing ICC = = IIBB and I and IEE I ICC, the loop , the loop equation becomes: equation becomes:

0RIVRIRI– V EBBEBBCBCC

Solving for ISolving for IBB::


Applying Kirchoff’s voltage law:Applying Kirchoff’s voltage law:

IERE + VCE + I’CRC – VCC = 0

Since ISince ICC I ICC and I and IEE I ICC::

IC(RC + RE) + VCE – VCC =0

Solving for VSolving for VCECE::

VCE = VCC – IC(RC + RE)

Base-Emitter Bias AnalysisBase-Emitter Bias Analysis

Transistor Saturation LevelTransistor Saturation Level

EC

CCCmaxCsat RR

VII


Cutoff:Cutoff: Saturation:Saturation:

mA 0IVV

C

CCCE

V 0VCE

ERCRCCV

CI

Bias Stabilization Bias Stabilization The stability of a system is a measure of the sensitivity of a network to variations in its parametersIn any amplifier employing a transistor the collector current IC is sensitive to each of the following parameters:• : increase with increase in temperature• |VBE| : decrease about 2.5 mV per oC

increase in temperature• ICO (reverse saturation current): doubles in value for every 100 increase in tempearture

Shift in dc-bias point (Q-point) due to change in temperature: (a) 250C; (b) 1000C

A better bias circuit is one that will stabilize or maintain the dc-bias initially set, so that the amplifier can be used in a changing-temperature environment

Stability Factors: S(ICO), S(VBE), and S()

CO

CCO I

IIS

)(BE

CBE V

IVS

)(

CIS )(

Networks that are quite stable and relatively insensitive to temperature variations have low stability factorsThe higher the stability factor, the more sensitive is the network to variations in that parameter

S(ICO):

Emitter-Bias Configuration

)/()1()/(1)1()(EB

EBCO RR

RRIS

)1()( COIS

1)1(

1)1()(

COIS

E

BCO R

RIS )(

For RB/RE >> (+1),

For RB/RE << 1,

For the range where RB/RE ranges between 1 and (+1),

[Variation of stability factor with the resistor ratio RB/RE for the emitter-bias configuration]

)1()( COIS

)/()1()/(1)1()(ETh

EThCO RR

RRIS

)/()1()/(1)1()(CB

CBCO RR

RRIS

Fixed-Bias Configuration:

Voltage-Divider Bias Configuration:

Feedback-Bias Configuration:

S(VBE):

EBBE RRVS

)1()(

Emitter-bias configuration:

Fixed-Bias Configuration:B

BE RVS

)(

EBBE RRVS

)1()(

)1(//)(

EB

EBE RR

RVS

E

EEBE R

RRVS 1/)1(

/)(

For (+1)>>RB/RE

This shows that the larger the resistance RE, the lower is the stability factor and the more stable is the system

S():

Emitter-bias configuration:

)/1()/1(

)(21

1

EB

EBCC

RRRRIIS

1

1)(

CIS

)/1()/1(

)(21

1

ETh

EThC

RRRRI

S

Fixed-Bias Configuration:

Voltage-Divider Bias Configuration:

Feedback-Bias Configuration:

))1(()(

)(21

1

CB

CBC

RRRRI

S

SummaryThe total effect on the collector current can be determined using the following equation:

)()()( SVVSIISI BEBECOCOC

Dc biasing of bjt

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