Dayle Kotturi and Stephanie Allison Facility Advisory Committee Meeting [email protected], [email protected]April 20-21, 2006 Timing Outline Block diagram overview of the timing system Where were we at time of last FAC? What has happened since then? How will this work anyway? How does it look from a users point of view? What do we still not know? Tasks remaining: plans/schedule
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Dayle Kotturi and Stephanie Allison Facility Advisory Committee Meeting [email protected]@slac.stanford.edu, [email protected] April 20-21,
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What has happened since then?Received the EVG/EVR 200 series VME hardware (which sends up to 2K data buffer)Adapted driver and device support to:
send the PNET data buffer (measured 66 µs transfer) be OSI (running on mvme6100, RTEMS4.7) with help from Till Straumann, Eric Bjorklund, Timo Korhonen, Jukka Pietarinen and Bob Dalesio
Wrote Timing Trigger System Engineering ManualReceived the EVR 200 series PMC moduleInstalled fiber optic network in Bldg 280 for testing
What has happened since then? (2)Stephanie is setting up a hardware teststand with separate IOCs for EVG and EVR in Bldg 34 for CPE engineers to do:
Timing comparison with existing CAMAC timing system (MPG/PDU)Timing measurements – jitter, etcShakedown by the experts
Test stand to include:EVG, PNET, EVR, EVR transition module, EVG fanout laterInputs: PNET pattern from CAMAC timing system, fiducial trigger, and 476Mhz clockOutputs: EVR front panel and back transition moduleInfrastructure: VME crates, dedicated terminal server, dedicated PC, fiber between EVG and EVREPICS: test databases and displays, EVR done, EVG in-progress
Interface Control Document + review, MayEVG input and outputHW and SW trigger list per subsystemApplications using the timing patternRecord (maybe IOC) timestampingBeam-synchronous acquisition and controlUse writeup provided by Bob Dalesio
Design Document + review, JuneBeam-Synchronous Control: rules and algorithm for creating EVG trigger sequences on a pulse-to-pulse basis – algorithm changes based on user requestsBeam-Synchronous Acquisition: mechanism for users to request pulse-by-pulse acquisition (single-shot or buffered) across multiple IOCs based on specified conditionsProper timing pattern in-place before a fiducial for record processing after fiducial
Implementation of above design plus:Integration with SLC-aware BPM acquisitionMissing functionality in existing EVG and EVR records for HW upgradeUser-friendly database layer on top of low-level EVR records