Day10 - Penn Engineering · 2012. 9. 26. · Day10.pptx Author: Andre DeHon Created Date: 9/26/2012 11:44:57 AM ...

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Penn ESE370 Fall2012 -- DeHon 1

ESE370: Circuit-Level

Modeling, Design, and Optimization for Digital Systems

Day 10: September 26, 2012 MOS Transistor Basics

Today

•  MOS Transistor Topology •  Threshold •  Operating Regions

– Resistive – Saturation – Velocity Saturation – Subthreshold

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Last Time

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•  Depletion region excess carriers depleted Penn ESE370 Fall2012 -- DeHon

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Refinement

Body Contact

•  Fourth terminal •  Also effects fields •  Usually common across transistors

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No Field

•  VGS=0, VDS=0

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2

Apply VGS>0

•  Accumulate negative charge – Repel holes (fill holes)

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+ + + + + + + +

- - - - - - - - -

Channel Evolution Increasing Vgs

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Gate Capacitance

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Changes based on operating region. Happy if you treat as parallel plate Capacitor for HW4.

Inversion •  Surface builds electrons

–  Inverts to n-type – Draws electrons from n+ source

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Threshold

•  Voltage where strong inversion occurs threshold voltage – Around 2ϕF

– Engineer by controlling doping (NA)

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€

φF = φT lnNA

ni

⎛

⎝ ⎜

⎞

⎠ ⎟

Resistive Region

•  VGS>VT, VDS small

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€

IDS = µnCOXWL

⎛

⎝ ⎜

⎞

⎠ ⎟ VGS −VT( )VDS −

VDS2

2⎡

⎣ ⎢

⎤

⎦ ⎥

€

COX =εOXtOX

3

Resistive Region •  VGS>VT, VDS small

•  VGS fixed looks like resistor – Current linear in VDS

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€

IDS = µnCOXWL

⎛

⎝ ⎜

⎞

⎠ ⎟ VGS −VT( )VDS −

VDS2

2⎡

⎣ ⎢

⎤

⎦ ⎥

€

COX =εOXtOX

Linear (Resistive) Region

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Blue curve marks transition from Linear to Saturation

Linear (Resistive) Region

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Dimensions

•  Channel Length (L) •  Channel Width (W) •  Oxide Thickness (Tox)

Preclass

•  Ids for identical transistors in parallel?

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Preclass

•  Ids for identical transistors in series? –  (Vds small)

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4

Transistor Strength (W/L)

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€

IDS = µnCOXWL

⎛

⎝ ⎜

⎞

⎠ ⎟ VGS −VT( )VDS −

VDS2

2⎡

⎣ ⎢

⎤

⎦ ⎥

S D

€

COX =εOXtOX

Transistor Strength (W/L)

•  Shape dependence match Resistance intuition – Wider = parallel resistors decrease R – Longer = series resistors increase R

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€

IDS = µnCOXWL

⎛

⎝ ⎜

⎞

⎠ ⎟ VGS −VT( )VDS −

VDS2

2⎡

⎣ ⎢

⎤

⎦ ⎥

€

R =ρLA

S D

Ldrawn vs. Leffective

•  Doping not perfectly straight •  Spreads under gate •  Effective L smaller than draw gate width

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Channel Voltage •  Voltage varies along channel •  Think of channel as resistor

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Preclass 2 •  What is voltage in the middle of a

resistive medium? –  (halfway between terminals)

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Voltage in Channel

•  Think of channel as resistive medium – Length = L – Area = Width * Depth(inversion)

•  What is voltage in the middle of the channel? – L/2 from S and D ?

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Channel Voltage •  Voltage varies along channel •  If think of channel as resistor

– Serves as a voltage divider between VS and VD

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Impact on Inversion •  What happens when

– Vgs=2Vth ? – Vds=2Vth?

•  What is Vmiddle-Vs?

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Channel Field

•  When voltage gap VG-Vxdrops below VTH, drops out of inversion – Occurs when: VGS-VDS< VTH

– What does this mean about conduction?

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Preclass 3

•  What is Vm?

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Channel Field •  When voltage gap VG-Vxdrops below VT,

drops out of inversion – Occurs when: VGS-VDS< VT

– What is voltage at Vmiddle if conduction stops? – What does that mean about conduction?

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Contradiction?

•  Vg-Vx < Vt cutoff (no current) •  No current Vg-Vx=Vgs •  Vg-Vx=Vgs > Vt current flows

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Way out?

•  Vg-Vx < Vt cutoff (no current) •  No current Vg-Vx=Vgs •  Vg-Vx=Vgs > Vt current flows

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Act like Vds at Vgs-Vt

Channel Field

•  When voltage gap VG-Vxdrops below VT, drops out of inversion – Occurs when: VGS-VDS< VT

– Channel is “pinched off”

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Channel Field

•  When voltage gap VG-Vxdrops below VT, drops out of inversion – Occurs when: VGS-VDS< VT

– Channel is “pinched off” – Current will flow, but cannot increase any

further

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Pinch Off

•  When voltage drops below VT, drops out of inversion – Occurs when: VGS-VDS< VT

•  Conclusion: – current cannot increase with VDS once

VDS> VGS-VT

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Saturation

•  In saturation, VDS-effecitve=Vx= VGS-VT

•  Becomes:

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€

IDS = µnCOXWL

⎛

⎝ ⎜

⎞

⎠ ⎟ VGS −VT( )VDS −

VDS2

2⎡

⎣ ⎢

⎤

⎦ ⎥

€

IDS = µnCOXWL

⎛

⎝ ⎜

⎞

⎠ ⎟ VGS −VT( )2 −

VGS −VT( )2

2

⎡

⎣ ⎢ ⎢

⎤

⎦ ⎥ ⎥

Saturation

•  VDS> VGS-VT

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€

IDS = µnCOXWL

⎛

⎝ ⎜

⎞

⎠ ⎟ VGS −VT( )2 −

VGS −VT( )2

2

⎡

⎣ ⎢ ⎢

⎤

⎦ ⎥ ⎥

€

IDS =µnCOX

2WL

⎛

⎝ ⎜

⎞

⎠ ⎟ VGS −VT( )2[ ]

7

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Blue curve marks transition from Linear to Saturation

Saturation Region Preclass 3

•  What is electrical field in channel? – Leff=25nm, VDS=1V – Field = VDS/L

•  Velocity: v=F*µ – Electron mobility: µn = 500 cm2/V

•  What is electron velocity?

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Short Channel

•  Model assumes carrier velocity increases with field –  Increases with voltage

•  There is a limit to how fast carriers can move – Limited by scattering to 105m/s

•  How relate to preclass 3 velocity? •  Encounter when channel short

– Modern processes, L is short enough

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S D

Velocity Saturation

•  Once velocity saturates:

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€

IDS ≈νsatCOXW VGS −VT −VDSAT

2⎛

⎝ ⎜

⎞

⎠ ⎟

€

VDSAT ≈Lνsatµn

Velocity Saturation

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Below Threshold

•  Transition from insulating to conducting is non-linear, but not abrupt

•  Current does flow – But exponentially dependent on VGS

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Subthreshold

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IDS = ISWL

⎛

⎝ ⎜

⎞

⎠ ⎟ e

VGSnkT / q⎛

⎝ ⎜

⎞

⎠ ⎟

1− e−VDSkT / q⎛

⎝ ⎜

⎞

⎠ ⎟

⎛

⎝ ⎜

⎞

⎠ ⎟ 1+ λVDS( )

Subthreshold

•  W/L dependence follow from resistor behavior (parallel, series) – Not shown explicitly in text

•  λ is a channel width modulation effect

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€

IDS = ISWL

⎛

⎝ ⎜

⎞

⎠ ⎟ e

VGSnkT / q⎛

⎝ ⎜

⎞

⎠ ⎟

1− e−VDSkT / q⎛

⎝ ⎜

⎞

⎠ ⎟

⎛

⎝ ⎜

⎞

⎠ ⎟ 1+ λVDS( )

S D

Subthreshold Slope

•  Exponent in VGS determines how steep the turnoff is – Every S Volts – Divide IDS by 10

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€

IDS = ISWL

⎛

⎝ ⎜

⎞

⎠ ⎟ e

VGSnkT / q⎛

⎝ ⎜

⎞

⎠ ⎟

1− e−VDSkT / q⎛

⎝ ⎜

⎞

⎠ ⎟

⎛

⎝ ⎜

⎞

⎠ ⎟ 1+ λVDS( )€

S = n kTq

⎛

⎝ ⎜

⎞

⎠ ⎟ ln 10( )

Subthreshold Slope

•  Exponent in VGS determines how steep the turnoff is – Every S Volts (S not related to source) – Divide IDS by 10

•  n – depends on electrostatics – n=1 S=60mV at Room Temp. (ideal) – n=1.5 S=90mV – Single gate structure showing S=90-110mV

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€

S = n kTq

⎛

⎝ ⎜

⎞

⎠ ⎟ ln 10( )

IDS vs. VGS

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Admin

•  Text 3.3.2 – highly recommend read – Second half on Friday

•  HW3 due Thursday •  HW4 out

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9

Big Idea •  3 Regions of

operation for MOSFET –  Subthreshold –  Resistive –  Saturation

•  Pinch Off •  Velocity Saturation

–  Short channel

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