TO-220FP 1 2 3 AM15572v1_no_tab D(2) G(1) S(3) Features Order code V DS @T Jmax R DS(on) max. I D STF18N60M2 650 V 0.280 Ω 13 A • Extremely low gate charge • Excellent output capacitance (C OSS ) profile • 100% avalanche tested • Zener-protected Applications • Switching applications • LCC converters • Resonant converters Description This device is an N-channel Power MOSFET developed using MDmesh M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Product status link STF18N60M2 Product summary Order code STF18N60M2 Marking 18N60M2 Package TO-220FP Packing Tube N-channel 600 V, 0.255 Ω typ., 13 A MDmesh M2 Power MOSFET in a TO-220FP package STF18N60M2 Datasheet DS9710 - Rev 4 - June 2019 For further information contact your local STMicroelectronics sales office. www.st.com
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Datasheet - STF18N60M2 - N-channel 600 V, 0.255 Ω typ., 13 A … · Table 7. Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 13
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DescriptionThis device is an N-channel Power MOSFET developed using MDmesh M2technology. Thanks to its strip layout and an improved vertical structure, the deviceexhibits low on-resistance and optimized switching characteristics, rendering itsuitable for the most demanding high efficiency converters.
Product status link
STF18N60M2
Product summary
Order code STF18N60M2
Marking 18N60M2
Package TO-220FP
Packing Tube
N-channel 600 V, 0.255 Ω typ., 13 A MDmesh M2 Power MOSFET in a TO-220FP package
STF18N60M2
Datasheet
DS9710 - Rev 4 - June 2019For further information contact your local STMicroelectronics sales office.
Figure 13. Test circuit for resistive load switching times
AM01468v1
VD
RG
RL
D.U.T.
2200μF VDD
3.3μF+
pulse width
VGS
Figure 14. Test circuit for gate charge behavior
AM01469v1
47 kΩ1 kΩ
47 kΩ
2.7 kΩ
1 kΩ
12 V
IG= CONST100 Ω
100 nF
D.U.T.
+pulse width
VGS
2200μF
VG
VDD
Figure 15. Test circuit for inductive load switching anddiode recovery times
AM01470v1
AD
D.U.T.S
B
G
25 Ω
A A
B B
RG
GD
S
100 µH
µF3.3 1000
µF VDD
D.U.T.
+
_
+
fastdiode
Figure 16. Unclamped inductive load test circuit
AM01471v1
VD
ID
D.U.T.
L
VDD+
pulse width
Vi
3.3µF
2200µF
Figure 17. Unclamped inductive waveform
AM01472v1
V(BR)DSS
VDDVDD
VD
IDM
ID
Figure 18. Switching time waveform
AM01473v1
0
VGS 90%
VDS
90%
10%
90%
10%
10%
ton
td(on) tr
0
toff
td(off) tf
STF18N60M2Test circuits
DS9710 - Rev 4 page 7/12
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,depending on their level of environmental compliance. ECOPACK specifications, grade definitions and productstatus are available at: www.st.com. ECOPACK is an ST trademark.
– Modified: typical value for Ciss, Coss eq., Qg, Qgs, Qgd
– Modified: Figure 10 and 11
– Minor text changes
28-Feb-2014 3
– Modified: note 1 in Table 2
– Rthj-case value in Table 3
– Minor text changes
19-Jun-2019 4
Modified Figure 8. Normalized gate threshold voltage vs. temperature,Figure 9. Normalized on-resistance vs temperature and Figure 11. NormalizedV(BR)DSS vs temperature.
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