datasheet

APPLICATION NOTE

Digital Video Encoder Module System:

7128MOD2AN 97085

Abstract

Module System: 7128MOD2

Philips Semiconductors

Application NoteAN 97085

2

Philips Electronics N.V. 1998

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copy-right owner.

The information presented in this document does not form part of any quotation or contract, is believed to beaccurate and reliable and may be changed without notice. No liability will be accepted by the publisher for anyconsequence of its use. Publication thereof does not convey nor imply any license under patent- or other indu-strial or intellectual property rights.

This application note is intended to provide application support for Philips´ Digital Video Decoders and Encoders. It contains a description of one evaluation board as well as I²C-bus programming of the respective device.

The Digital Video Decoder converts an analog video input signal into a digital output signal. This signal can be processed by a wide range of applications and fed to the Digital Video Encoder, which delivers analog video signals to TV receivers or video cassette recorders.

This note gives a detailed description of the schematics and some hints how to design the PCB (Printed Circuit Board) with mixed analog and digital signal processing.

Keywords


Author:

Digital Video Encoder Application NoteAN 97085

3

APPLICATION NOTE

Digital Video Encoder Module System:

7128MOD2

Dietmar SpellerMPC-E, Hamburg,

Germany

Digital Video Encoder (DENC)SAA7128/29SAA7138/39SAA7120/21SAA7126/27

I²C-busMultiMedia

Date: 5th December 1997

AN 97085

Summary




4

This application note is intended to provide application support for Philips´ Digital Video Decoders and Encoders. It contains a description of one evaluation board as well as I²C-bus programming of the respective device.

The Digital Video Decoder converts an analog video input signal into a digital output signal. This signal can be processed by a wide range of applications and fed to the Digital Video Encoder, which delivers analog video signals to TV receivers or video cassette recorders.

This note gives a detailed description of the schematics and some hints how to design the PCB (Printed Circuit Board) with mixed analog and digital signal processing.



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1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2. Digital Video Encoder Module 7128MOD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.3 Input- and Output- Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.1 VG96 Input Connector on 7128MOD2 . . . . . . . . . . . . . . . . . . . . . . . . . 102.3.2 CVBS Subclick Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.3.3 SCART Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4 I²C-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.5 I²C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.6 Clock- and Synchronization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.7 Jumperlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3. Interfacing Input Data with a Y-module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4. Tips for a PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.1 Analog and digital signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.2 IIC bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5. Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.1 Programming tables for SAA7128/29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.2 Summary of Registerfunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6. Appendix: Schematics and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.1.1 Top Sheet of 7128MOD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.1.2 Connector In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326.1.3 Connector Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.1.4 SAA7138/39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.1.5 SAA7128/29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356.1.6 Output Filter 1..6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366.1.7 5MHz Lowpass Filter1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376.1.8 5MHz Lowpass Filter2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.1.9 5MHz Lowpass Filter3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396.1.10 5MHz Lowpass Filter4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406.1.11 5MHz Lowpass Filter5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416.1.12 5MHz Lowpass Filter6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426.1.13 I²C - EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436.1.14 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456.2.1 Top Placement of 7128MOD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456.2.2 Routing of Top Layer of 7128MOD2 . . . . . . . . . . . . . . . . . . . . . . . . . . 466.2.3 Top Solder Mask of 7128MOD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.2.4 Bottom Placement of 7128MOD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486.2.5 Bottom Layer of 7128MOD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496.2.6 Bottom Solder Mask of 7128MOD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 506.2.7 Ground plane layer of 7128MOD2 (Mid Layer1) . . . . . . . . . . . . . . . . . . . . 516.2.8 Routing of Power Supply Layer of 7128MOD2 (Mid Layer2) . . . . . . . . . . . . . . 52

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1. IntroductionThe Digital Video Decoder/Encoder Modules provide the basis to evaluate various Philips Digital Video Decoders and Encoders and give the opportunity to simply insert the modules into customized applications and systems.

On the following pages the assembly and function of a Digital Video Encoder Module is shown. The module can operate in stand alone mode (colourbar generator) as well as extension to other systems like PCI-bridges, MPEG decoders or Video input/output systems.

The module has a socket for an I²C-bus EEPROM (e.g. PCF8582, PCF8594, PCF8598, X24164) in order to store data for initialization and for simple control functionality operated by a (future) microcontroller module.

Software for IBM compatible personal computers enables access to all features and settings of the devices. It handles the I²C-bus via a printer port adaptor. This adaptor and a fitting cable is part of the accessory.

This modular concept was designed to combine different video decoders with various video encoders. Some modules (e.g. the 7128MOD2) can be configured for several devices and packages without the necessity of having a new PCB. This could be achieved by using multiple footprints for one IC and some configurational parts. For interfacing a 96-pin module connector is used.

The modules need a 5V analog and a 5V digital supply voltage. A respective power connector is placed at each backend (encoder-) module whereas frontend modules are supplied via the 96-pin module connector.

If necessary, an internal voltage regulator generates the required 3.3V onboard. Alternatively it is also possible to bypass the regulators on some encoder modules and connect 3.3V supply directly to the respective pins. You can find a fitting power connector cable as a part of the accessory as well.

2. Digital Video Encoder Module 7128MOD2 The digital encoder module 7128MOD2 contains the Philips Digital Encoder SAA7128/29, SAA7138/39,SAA7120/21or SAA7126/27 (the even-numbered types include Macrovision Pay-per-View copy protection, whilethe odd-numbered types do not).All listed encoders are CMOS 3.3V devices with 3.3V input stages but differ (among others) in following features:

SAA7128/29 PAL/NTSC/SECAM encoder with six DACs for CVBS(CSYNC), VBS(CVBS), C(CVBS), R(Cr),G(Y), B(Cb) (signals in brackets optionally) and a 54MHz double speed multiplexed D1 interface. It features alsoa versatile fader for fading of two data streams (at double speed port MP) against each other. QFP44 package.

SAA7138/39 PAL/NTSC/SECAM encoder with six DACs for CVBS(CSYNC), VBS(CVBS), C(CVBS), R(Cr),G(Y), B(Cb) (signals in brackets optionally) and a 54MHz double speed multiplexed D1 interface. It features alsoa versatile fader for fading of two data streams (at double speed port MP or through the additional port DP) againsteach other. QFP64 package.

SAA7120/21 PAL/NTSC encoder with three DACs for CVBS, Y, C. QFP44 package.

SAA7126/27 PAL/NTSC encoder with four DACs for CVBS(CSYNC, VBS), R(Cr, C), G(Y, VBS) and B(Cb,CVBS) (signals in brackets optionally) and a 54MHz double speed multiplexed D1 interface. QFP44 package.

The digital data is fed via the 96-pin input connector. The circuits accept CCIR compatible YUV data with 720active pixels per line in 4:2:2 multiplexed formats, for example MPEG decoded data. For interfacing an ECL - TTLconverter can be used (accessory). At a 54MHz (double speed) multiplexed D1 input port the circuits accept twoCCIR compatible CbYCr data streams for example MPEG decoded data with overlay, whereas one datastream is

8




latched at the rising, the other one at the falling clock edge. Therefore a special Y-module is designed (availableJan. ’98). This Y-module will provide two input module connectors with multiplexer, an EPROM with CCIR 656data and a centronic interface to generate a 54MHz interlaced data stream (see chapter 3.).After passing the analog postfilters (to be be disabled with jumper) the output signal is available simultaneouslyas CVBS, Y/C (and RGB) at the respective connectors (SCART for CVBS, Y/C, RGB and additionally a subclickconnector for CVBS output). An adaptor from SCART to Mini Din and Cinch is part of the accessory. To preventa wrong termination, be sure that the CVBS0 signal is not switched to the CVBS output connector and the SCARToutput (CVBS output or RGB-SYNC) at the same time (JP14, JP15).

Fig.1 Location of ICs, jumpers and connectors on the 7128MOD2 PCB

Fig.1 shows the location of IC’s, jumpers and connectors on the application module 7128MOD2. The function of the used connectors is described on page 10. The function of jumpers is shown in a jumper list on page 16.

a b c

DIL

20 SPARE

71__MOD2 V1.0

DIL

8

DGND AGND

A0A1A2

U5

CVBS

US

NE

WO

LD

+5VD

DGND

+5VA

AGND

-5VA

27 MHz

RESETC

VB

S

C

Filter off ||Filter on =

Y

R

B

G

SC

AR

T

Filter

Source

RESNSwitch

Extern

I²C5V

3,3V

U4

SAA7120/21SAA7126/27SAA7128/29SAA7138/39

PHILIPS MPC-E/PDOctober 1997

TERMLLC_2

TERMLLC_1

CVBS1

CVBS2

S5/

O10

SA

LLCB

CLKOUT

LLCA

LLCOUT

LLC_1

XCLK

LLC_2

HS to RCV2

VSRCV1ODD

CVBS1CVBS2

CVBS0

Y/C / RGB

Y/C / CVBS

RGB

active

Y/CSAA7126/27

I²C EEPROM

I²C

-CO

N



9


2.1 Power supplyThe +5V analog and digital power supply should be kept separate at the power connector. Analog and digital ground must be connected once near the power supply units.

A negative voltage (-5V) is one part of the MPC module system supply voltages but is not necessary for this application.

All supply voltages are available at the VG96 input connector according to the pinning on page 10.

2.2 ResetThere are two different ways to reset the device:

Using this module in conjunction with a MPC decoder module, preferably the ’Reset Not’ generated by the deco-der should be used (JP26 = Extern). Therefore a dedicated pin exists at the VG96 input connector.

In case of a stand alone operation (e.g. colourbar generator) or in conjunction with other systems the Reset push-button can be used (JP26 = Switch).

During reset (RESN = LOW) and after reset is released, all digital I/O stages are set to input mode, PAL-Black-burst on CVBS, VBS and C; all analog outputs are set to high impedance. A reset forces the I²C-bus interface to abort any running bus transfer and sets register 3A to 03H, register 61 to 06H and registers 6BH and 6EH to 00H. All other control registers are not influenced by a reset.

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2.3 Input- and Output- Connectors

2.3.1 VG96 Input Connector on 7128MOD2

TABLE 1 Pinning of the VG96 module input connector (bottom view)

*: only for SAA7138/39

IN a b c

32 -5V ANALOG

31 GND ANALOG

30 +5V ANALOG

29GND DIGITAL

28

27+5V DIGITAL

26

25 SDA RESN SCL

24 VP7

23 VP6 CLKOUT*

22 VP5

21 VP4

20 VP3 LLC_2*

19 VP2

18 VP1

17 VP0 LLC_1

16 ODD

15

14

13 RTCI

12 VS

11 HS

10 SOURCE*

9

8 MP7 TTXRQ

7 MP6 TTX

6 MP5 RCV2

5 MP4 RCV1

4 MP3

3 MP2

2 MP1

1 MP0



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TABLE 2 Description of signals on the VG96 module input connector

*: only for SAA7138/39

Signal Specification

SDA I2C-bus serial data.

SCL I2C-bus serial clock.

RESNReset Not Input (active LOW). After Reset is applied, all digital I/O’s are in input mode; PAL-Blackburst on CVBS, VBS and C; RGB outputs set to lowest voltage. The I²C-bus receiver waits for the START condition.

MP (7..0)

Double speed 54MHz MPEG port. Input for CCIR 656 style multiplexed Cb, Y, Cr data. Data are sampled at the rising and falling clock edge; data sampled on the rising edge then are sent to the encoding part of the device, data sampled on the falling edge are sent to the RGB part of the device (or vice versa, depending on programming)

DP* (7..0) Data port input for CCIR 656 style multiplexed Cb, Y, Cr data.

LLC_1 Line-Locked clock input 1; this is the 27MHz master clock (via JP13A)

LLC_2*Line-Locked clock input 2; this is the alternative source for the 27MHz master clock (via JP13)

CLKOUT*Line-Locked clock output, this is the buffered output for the selected 27MHz master clock (via JP13A)

SOURCE*Fast switch between DP and MP port. If the fader is bypassed, a HIGH selects MP port, a LOW selects DP port.

HS Horizontal Synchronous signal for synchronization via RCV2.

VS Vertical Synchronous signal for synchronization via RCV1 (JP9).

ODD ODD/EVEN Field Identification, for synchronization via RCV1 (JP9).

RCV1 Raster Control 1, this pin provides or receives a VS, FS or FSEQ signal.

RCV2Raster Control 2, this pin provides an HS pulse of programmable length or receives an HS pulse.

RTCI

Real Time Control input. If the LLC clock is provided by a digital video decoder like SAA7111A, supporting this function. RTCI should be con-nected to the RTCO pin of the respective decoder to get information con-cerning actual subcarrier, PAL-ID, and more, depending on the video decoder.

TTXRQ Teletext Request output, indicating when the bit stream is requested.

TTX Teletext bit stream input.

12




2.3.2 CVBS Subclick Connector

This is the output for the CVBS signal that passed the 5MHz LOWPASS FILTER and the JP14 (CVBS_out). This jumper selects the CVBS output (CVBS0 or optionally CVBS1,2 at Y/C lines). A simultaneous load at this conne-xctor and the SCART connector should be avoided.

2.3.3 SCART Connector

Fig.2 Output Connector

The figure above shows the analog output circuit with Subclick- and SCART- connector. The main CVBS line should not be switched to both Subclick and SCART (CVBS output or CSYNC) at the same time. The SAA7128/29 and SAA7138/39 offer additional CVBS outputs on Y and C pins as option (JP14). To enable RGB input to a SCART TV plug, close JP16. In this case JP17 must be in position ’RGB’

SAA7120/21: This device provides no other signals than CVBS and Y/C one time so the jumper configuration is JP14 = CVBS0 and JP17 = Y/C.

SAA7126/27: This device provides CVBS and Y/C or RGB signals at the respective connectors. For Y/C output JP31 and JP32 must be closed.

A

CVBS0

CVBS1

CVBS2

RGB

Y / C

"place sideby side"

Y / C CVBS

YCOUT1

YCOUT0

RGBOUT1

RGBOUT0

RGBOUT2

P4

SCART

CVBS out19

CVBS Gnd17

RED15

RED Gnd13

GRN11

GRN Gnd9

BL7

BL Gnd5

L out3

R out1

CVBS in20

ST RGB Gnd18

ST RGB16

D²B Gnd14

D²B12

D²B10

CTRL I/O8

L in6

LR Gnd4

R in2

GND21

P3

CVBS_CON1

2

12

JP16

RGB active

12

JP15

1 32

JP17

13

2

JP14

13

2

CVBSOUT

YCOUT[1..0]

RGBOUT[2..0]

VDD

A



13


2.4 I²C-Bus Two I²C-bus slave addresses are selected:

88H: LOW at pin SA

8CH: HIGH at pin SA

Systems running in a 3.3V environment probably require the same voltage for the I²C-bus. In this case, JP29 must be changed from default position to 3.3V in order to adjust the I²C supply voltage. A new Single Master Interface with the IC 74HC9114D can be used then, it replaces the former Single Master Interface with the IC 74LS05, which is only suited for 5V. The new interface operates on the I²C-bus from 1.8V to 5V.

Please note that there are no additional pullup resistors on this board, thus supply of the I²C-bus is provided once at the (single master-) I²C-bus interface.

On this backend module, two connectors can be used for I²C-bus control (alternative). The first one is a 6pin Mini DIN connector with the pinning shown on the right side of Fig.3. In order to consider different existing pinnings, the STOKO connector has a combined footprint for the standards ’Old’, ’New’ and ’US’. Please note that modules from the Philips Application Lab. Hamburg use the norm ’NEW’ while the default configuration of the MPC module system is ’OLD’.

Fig.3 Pinning of I²C-STOKO and Mini-DIN connector

2.5 I²C EEPROMA DIL 8 socket on each module is provided for adding an EEPROM with I²C interface. It can be used to store data for initialization and simple control functionality operated by a (future) microcontroller module. Several EEPROM types can be assembled depending on their memory size (e.g. PCF8582, PCF8594, PCF8598, X24164). Additio-nally, the I²C-bus device address can be adapted by using the jumper 1..3 (EEP-Adr).

COMBI-FOOTPRINT

VCCGNDSCLSDA

SDAVCCGNDSCL

VCCSDAGNDSCL

NEW OLD US(Top View)

GND

SCL SDA

GNDVCC

(Solder View)

14




2.6 Clock- and Synchronization signalsThere are two operating modes for the encoder on this board. In master mode, V- and H- signals are output of the RCV1 and RCV2 pins in order to synchronize an external source (e.g. memory or teletext).

In slave mode the synchronization signals H and V are generated out of the frame sync code embedded into the CCIR-656 data stream or fed to the encoder via RCV1 and RCV2 (after passing JP23 and JP24). The configura-tion of RCV1 and RCV2 (direction, polarity etc.) is handled in Reg. 6BH (Some information about register-functions can be found on page 25). After a reset the RCV pins are programmed as inputs.

Regardless of master or slave mode operation, the system clock LLC can come from external or from the chip’s own oscillator. Figures 4 and 5 show the respective jumper to configure clock direction. When an external clock is received, JP27 and JP28 allow termination of LLC_1 and LLC_2 by adding a 240R resistor to ground. In addition to this, series resistors (22R) terminate these clock lines.

Fig.4 Clock switching for SAA7138/39

Possible applications are:

- The internal oscillator provides the master clock by connecting XCLK and LLC1 (or LLC2). The buffered clock signal at pin LLCOUT is switched to VG96 pin LLC for other circuits.

- An external oscillator can clock the device via VG96 pin CLK2_IN and JP13. Like in the first case, the buffe-red clock signal at pin LLCOUT is switched to VG96 pin LLC for other circuits.

- An external oscillator can clock an external device (e.g. MPEG decoder). The clock signal comes in via CLK2_IN and out via the buffered clock output LLCOUT and the VG96 pin CLKOUT.

a b c

SAA 7138/39

LLC2

XCLK

LLC1

LLCout

CLK2 IN (B20)

LLC (B17)

CLK OUT (B23)

JP13

JP13A



15


Fig.5 Clock switching for SAA7128/29 (’26/’27, ’20/’21)

If types other than SAA7138/39 are being used,only jumper (JP13) is essential. In master mode the internal osci-llator generates the clock at pin XCLK and jumper (JP13) is used to connect the device and external circuits via LLC_1. The shown shortcut is done by a 0R resistor.

In slave mode this jumper must be open.

a b c

SAA 7128/29 SAA 7126/27 SAA 7120/21

XCLK

LLC1

LLC_1 (B17)

shortcut

16




2.7 Jumperlist

TABLE 3 Jumperlist 7128MOD2Jumper Name Description

JP1,2 ’C’ 5MHz lowpass filter 1 ON/OFF

JP3,4 ’Y’ 5MHz lowpass filter 2 ON/OFF

JP5,6 ’CVBS’ 5MHz lowpass filter 3 ON/OFF

JP7,8 ’B’ 5MHz lowpass filter 4 ON/OFF

JP9,10 ’G’ 5MHz lowpass filter 5 ON/OFF

JP11,12 ’R’ 5MHz lowpass filter 6 ON/OFF

JP13 XCLK/CLK2IN Handles clock direction together with JP13A

JP 13A CLOCK I/O (5 pins) Handles clock directions acc. to Fig.

JP14 CVBS out Connects default CVBS1 or opt. CVBS2,3 to SubClick

JP15 Y/C / CVBS SCART output: CVBS0 or Y

JP16 RGB active Activates RGB input of e.g. TV if closed

JP17 Y/C / RGB SCART output: RED or C

JP18 A0 EEPROM address A0



JP21 S5/O10 CVBS2 Closed: CVBS2 out; open: for Y/C out (C-path)

JP22 S5/O10 CVBS1 Closed: CVBS1 out; open: for Y/C out (Y-path)

JP23 HS to RCV2 Connects HS line to RCV2 device-pin

JP24 ODD/VS Connects ODD line or Vertical Sync to RCV1 device-pin

JP25 SA I²C slave address select, closed = 88H, open = 8CH

JP26 RESN Selects source for Reset Not signal (push-b./inp.conn.)

JP27 TERMLLC_1 Termination of 1st LLC line with 240R

JP28 TERMLLC_2 Termination of 2nd LLC line with 240R

JP29 IIC 5V/3V Supply voltage for I²C-bus (default: 5V)

JP30 SOURCE Fast Switch Input Port (only for SAA7138/39)

JP31 Y/C SAA7126 Y/C output from SAA7126/27 (C-path)

JP32 Y/C SAA7126 Y/C output from SAA7126/27 (Y-path)



17


3. Interfacing Input Data with a Y-moduleThe following drawings show some principal ways how to connect a Chameleon Digital Video Encoder to one or two video/overlay data sources.

Within SAA7128/29 (eventually within a device indicated here as SAA7138/39), the two video data streams can be directed separately to RGB outputs and Y/C/CVBS outputs. A hard keying or versatile chroma keying and fading is available for combing both data streams

Mode 1:

Clock LLC comes from SAA7111A (or a similar Philips Digital Video Decoder), the SAA7128/29 video encoder is slaved to the sync code (frame sync) embedded into the CCIR-656 data stream from SAA7111A. Output H - sync and V- sync from SAA7128/29 master a memory controller and memory for output of overlay data. Memory con-troller and associated memory can also be considered to be represented by the OSD/overlay part of an MPEG decoder.

The two data streams, one from SAA7111A, the second from the overlay generator, are multiplexed to a physical 54 MHz data stream, using LLC as a control signal for the external multiplexer.

Mode 2:

The on-chip LLC clock generator of SAA7128/29 is used to clock the MPEG decoder and the memory, providing OSD/overlay signals. Both MPEG decoder and separate overlay source are slaves of SAA7128/29 H- and V- syncs.

This seems to be a rather uncommon configuration, in practice Mode 3 will be more of interest.

Mode 3:

LLC clock is coming from the on-chip crystal oscillator of SAA7128/29, which should be able to be fine-tuned in a certain range. (LLC could also come from an external oscillator of similar properties). The MPEG decoder is sla-ved to SAA7128/29 w.r.t. H- sync and V- sync.

A 54 MHz multiplexed data stream, carrying e.g. video with overlay data at the rising clock edge and video wit-hout overlay data at the falling clock edge, is directly fed to the 54 MHz input port of SAA7128/29.

Mode 4:

As the device indicated here SAA7138/39 has two separate 8 bit D1 ports, ‚MP' and ‚VP', external demultiplexing is not necessary.

The video decoder SAA7111A is master for the video encoder w.r.t. LLC clock and H-sync and V-sync (embed-ded frame sync in the CCIR-656 data coming out of the video decoder and going into VP input).

The encoder-internal clock chip buffers the clock as LLCOUT for the OSD/overlay source. SAA7138/39 is sync master for the OSD/overlay source, which is sending its data to the MP input.

Again, this configuration seems to be uncommon (for test purposes, only), and Mode 5 should be focused on the more.

Mode 5:

Again, the video decoder SAA7111A is clock and sync master for SAA7138/39, providing clock LLC to clock input LLC_1, and video and sync via input port VP.

Through H- and V- sync coming out of SAA7138/39, additional OSD/overlay data can be taken from the MPEG decoder in order to overlay it to the (digitized) analog video. In this case, LLCOUT for the MPEG decoder is derived from LLC_1. The OSD/overlay data can come with the rising or falling edge of LLCOUT or with both edges.

If the active video source is MPEG video, the SAA7111A video decoder will idle, and clock for SAA7138/39 is LLCO, fed to the LLC_2 input of the encoder-internal clock multiplexer. For this operational mode, also the on-chip crystal oscillator instead of an external oscillator could be used.

18




Interfacing 54MHz data via Y-module with SAA7128/29 operating as a clock slave / master (mode1 + 2)

I

SAA7111A

MEMORYCONTROL

MEMORY

CENTRONICS

EPROM

MP2

MP1

27MHz data(8bit)

LLC

54MHzmultiplexed data

(8bit)

RCV1,2H(1), V

LLC

SAA7128/29

(2)

(1): delayed via 74 574(2): delayed via 74 240

MUX

MPEG DECODER

MEMORYCONTROL

MEMORY

CENTRONICS

EPROM

MP2

MP1

MPEGdecoded data LLC


(8bit)

RCV1,2H(1), V

LLC

SAA7128/29

(2)

(1): delayed via 74 574(2): delayed via 74 240

H, V

MUX



19


Interrfacing 54MHz data via Y-module with SAA7128/29 operating as a clock master (mode 3)

Interfacing 54MHz data via Y-module with SAA7138/39 operating as a clock slave (mode 4)

MPEG DECODER

MEMORYCONTROL

MEMORY

CENTRONICS

EPROM

MP1

MPEG decoded data54MHz multiplexed

8bit LLC


8bit

RCV1,2H(1), V

LLC

SAA7128/29

(1): delayed via 74 574

H, V

MUX

SAA7111A

MEMORYCONTROL

MEMORY

CENTRONICS

EPROM

MP2

MP: 27MHz data 8bit

RCV1,2H(1), V

SAA7138/39


LLC

VP: 27MHz data 8bit

LLC_1

LLCOUT

27MHz data 8bit

MUX

20




Interfacing 54MHz data via Y-module with SAA7138/39 operating as a clock slave (mode 5)

SAA7111A

MEMORYCONTROL

MEMORY

CENTRONICS

EPROM

MP1MP: 27/54MHz data 8bit

RCV1,2H(1), V

SAA7138/39


LLC

VP: 27MHz data 8bit

LLC_1

LLCOUT

27MHz data 8bit

MPEG DECODER

27/54MHzMPEG decoded data

H, VLLCILLCO

LLC_2

MUX



21


4. Tips for a PCB layout

4.1 Analog and digital signal processing- use separate ground planes for analog and digital supply in one layer (no overlapping!)

- use separate supply planes for analog and digital with the same shape (or smaller) as ground

(no overlap of analog supply with digital ground and vice versa!)

- if there are different (asynchronous) clock domains, use separate ground and supply planes(place the analog areas not in a direct neighborhood; separate the clock domains)

- always use the inner layers for ground and supply planes (no signal layer in between!)

- try to keep digital signals away from analog areas

- place analog areas close to the border of a PCB

- avoid long tracks for analog signals

- place decoupling capacitors (22nF to 100nF) close to the power pins of the ICs

- prepare several provisions for connecting places for analog and digital ground on the PCB for further optimization on the final board.

4.2 IIC busalways supply the I²C-bus with pull-up resistors, but avoid too high currents. The values of resistors Rp and Rs depend on the following parameters:

- supply voltage

- bus capacitance

- number of connected devices (input current + leakage current)

please see I²C-bus specification (e.g. chapter 10.1 in the Philips data handbook: ’Maximum and minimum values of resistors Rp and Rs’).

4.3 Application informationApplication environment of all possible encoders on this board is shown at the end of the datasheet of the respective device.

22




5. SoftwareThe enclosed disk contains the latest version of the Universal Register Debugger Software (URD) and some files and macros for easy debugging Philips encoders and decoders in conjunction with the I²C-bus Parallel Port adaptor.

For this module please open the file SAA7128.urd to get a default setup as described on the following page. The information will be transmitted by clicking the ’WD’ (write default) push button.

To change this setting (e.g. for NTSC or SECAM encoding) there exist macros as shown on pages page 24 and following. The program is caused to perform a macro operation by clicking the push button right in front of the macro name.

For editing single values use +/- on your keyboard and then click ’WN’ (write now).

You can find further details concerning the software in the doc-file on the disk.



23


5.1 Programming tables for SAA7128/29

SAA7128/29:init data

PALSlave: 88H or 8CH

Sub Data Sub Data

Reg 26H 0DH Reg 5CH AFH

Reg 27H 00H Reg 5DH 2DH

Reg 28H 1FH Reg 5EH 3FH

Reg 29H 1FH Reg 5FH 3FH

Reg 2AH 75H Reg 60H 7BH

Reg 2BH 3FH Reg 61H 02H

Reg 2CH 06H Reg 62H 46H

Reg 2DH 3FH Reg 63H CBH

Reg 38H 1AH Reg 64H 8AH

Reg 39H 1AH Reg 65H 09H

Reg 3AH 13H Reg 66H 2AH

Reg 42H 00H Reg 67H 77H



Reg 45H 97H Reg 6AH 41H

Reg 46H 4CH Reg 6BH 12H

Reg 47H 18H Reg 6CH 02H

Reg 48H 9BH Reg 6DH 20H

Reg 49H 93H Reg 6EH A0H

Reg 4AH 9FH Reg 6FH B4H

Reg 4BH FFH Reg 70H 41H

Reg 4CH 7CH Reg 71H C3H

Reg 4DH 34H Reg 72H 00H

Reg 4EH 3FH Reg 73H 3EH

Reg 4FH 17H Reg 74H B8H

Reg 50H 00H Reg 75H 1EH




Reg 54H 8CH Reg 79H 16H

Reg 55H 0FH Reg 7AH 2BH

Reg 56H C3H Reg 7BH D9H

Reg 57H 06H Reg 7CH 80H

Reg 58H 02H Reg 7DH 00H

Reg 59H 80H Reg 7EH 00H

Reg 5AH 34H Reg 7FH 00H

Reg 5BH 7DH

The table shows a default setup for the SAA7128/29. with following settings:

• 8-bit input data format

• working as clock slave

• detection of sync. signals (H, V) out of datastream

• Output format = PAL

• WSS, TTX and Closed Caption disabled

• Internal colour bar off (LUT’s programmed to 100% colourbar

• not listed registers must be programmed to 00H

To activate the programmable colour bar generator the MSB of register 3AH must be set to ’1’.

Bold signed registers must be edited for changing the output format (NTSC, SECAM)

The most important changes e.g. concerning output format are shown in the next tables.

24




TABLE 4 Changes for NTSC and SECAM

The tables show the registers that are changed when performing a macro function.

SAA7182/83:changes for NTSCSlave: 88H or 8CH

SAA7182/83:changes for SECAMSlave: 88H or 8CH

Sub Data Sub Data

Reg 5AH Reg 5AH

Reg 5BH Reg 5BH

Reg 5CH Reg 5CH

Reg 5DH Reg 5DH

Reg 5EH Reg 5EH

Reg 5FH Reg 5FH

Reg 61H Reg 61H

Reg 62H Reg 62H

Reg 63H Reg 63H

Reg 64H Reg 64H

Reg 65H Reg 65H

Reg 66H Reg 66H

Reg 6CH Reg 6CH

Reg 6DH Reg 6DH

Reg 6EH Reg 6EH

Reg 7AH Reg 7AH

Reg 7BH Reg 7BH



25


5.2 Summary of RegisterfunctionsIn the following table the usage of registers is described in order to get a quick view of the most important functions and give help for programming the device. The table does not contain whole information about the function or determination of values but should give background information. The subaddress is the location according to the described function but not exclusive in every case. For further details see chapter ’Slave Recei-ver’ in the datasheet.

TABLE 5 Registers of the SAA7128/29

Function SubAdr Description

Status byte (read only)

00H

NULL 01H - 25H Always program with 00H in order to avoid unexpected effects

Wide Screen Signal 26H - 27HWSSON enables or disables completely the WSS encoding; for meaning of the individual bits refer to the table given in ETS-300 294

Real Time Control 28H

If RTCE is set to high, Real Time Control (RTC) of the generated subcar-rier frequency is enabled. RTC should be used whenever the clock for the video encoder is generated by a digital line-locked video decoder to ensure stable encoding phase for clean colors.From a decoder supporting the new function DECCOL, a flag indicating that color was detected can be received if DECCOL=high.If DECFIS=high, the field frequency information detected by a decoder can be received.

Burst Start / End 28H - 29HThe begin and the end of the color burst can be adjusted in a certain range at an accuracy of LLC clock cycles; the suggested defaults should be used

Copy Generation 2AH - 2CH

CG19-CG0: LSB’s of the respective bytes are encoded immediately after run-in, the MSB’s of the respective bytes have to carry the CRCC bits, in accordance with the definition of Copy Generation Management System encoding format.CGEN set low disables the insertion.

Output Port Control 2DH

All DAC outputs can be set individually to high impedance through bits BTRI (Blue or Cb), GTR (Green or Y), RTRI( Red or Cr) YTRI( VBS or CVBS), CVBSTRI (CVBS or CSYNC).If CVBSEN0 is set low, the C signal is directed to the DAC normally used for this signal; if CVBSEN0 is set high, a CVBS signal is directed to this DAC as an alternative.If CVBSEN1 is set low, the VBS signal is directed to the DAC normally used for this signal; if CVBSEN1 is set high, a CVBS signal is directed to this DAC as an alternative.

NULL 2EH - 37H Always program with 00H in order to avoid unexpected effects

Gain Luma and Gain Colour Diff. of RGB

38H - 39H

Common practice is to set GY=GCD in order to adjust both luminance con-trast and color saturation, when RGB output mode is chosen.The suggested nominal values given in the datasheet are based on the proposed external resistor circuitry (23 Ohm series, 75 Ohm load).

26




Input Port Control 1 3AH

(0, 1): setting these bits high for straight binary data, inverts the MSB inter-nally for correct processing; setting these bits low passes the data as it is.(2): when this bit is set low, a CVBS signal is directed to the DAC normally used for this signal; if it is set low, a composite sync only is directed to this DAC as alternative.(3): when this bit is set high, the color dematrix is by-passed, and video input is only up-sampled to 27 MHz data rate for output instead of RGB.(4): when this bit is set high, in slave mode the encoder is triggered by an embedded frame sync code within the CCIR-656 data input. If the embed-ded frame sync is not available, this bit must be set low and appropriate signals have to be provided at RCV1 and RCV2 inputs.(6): SAA7138/39 only: this bit set low enables the fader function; if it is set high, two input signals can be hard-keyed via the pin SOURCE.(7): setting this bit high decouples the video input and inserts a test signal defined by eight color-programmable bars, e.g. a 100/75 color bar.

Key Colour 42H - 4DH

Two 24 bit (True Color) color ranges KEY1 and KEY2 are defined, which together with the weighting factors Fade1 and Fade2 determine the YUV color range of the first input signal to be blended with the second input signal.

Fade 4EH - 50H

FADE1, FADE2 and FADE3 are 6 bit multiplicators, defining the trans-parancy of the two input signals. While FADE1 and FADE3 operate in the YUV color space defined through the borders of the Key Color parameters, FADE3 blends the color stored in the internal LUT against one of the input signals.If CFADEV is set high, the first input signal (MP1) at port MP is mixed enti-rely with the color stored in the internal LUT, using FADE3 as multiplicator, regardless of the defined Keying range.If CFADEV is set high, the second input signal (MP2) at port MP is mixed entirely with the color stored in the internal LUT, using FADE3 as multipli-cator, regardless of the defined Keying range.

Look up table for Key Colour

51H - 53HTrue color value of the internal Lookup table that is used for blending if a color within color range KEY2 is detected in the first input signal.

Input Port Control 2 54H

If EDGE1 set low, data of the first input signal at MP port are sampled at the rising clock edge, otherwise at the falling clock edge.If EDGE2 set low, data of the second input signal at MP port are sampled at the rising clock edge, otherwise at the falling clock edge.Only SAA7138/39:If VPSEL set low, Fader input VP is fed with data app-lied to DP port, if VPSEL set high, Fader input VP is fed with data applied to MP2 input .If DELIN set low, data at DP port are by-passing the fader; if DELIN set high, data of MP2 are by-passing the fader.If RGBIN set low and DELIN set low, data to the RGB processor come from the DP port; if RGBIN set low and DELIN set high, data to the RGB processor are MP2 data;If RGBIN set high, the output of the fader is fed data to the RGB processor.




27


Video Programming System Data Inser-tion

54H - 59H

VPSEN set to high enables the insertion of data for Video Programming System.Five bytes VPS5, VPS11, VPS12, VPS13, and VPS14 can be loaded acc. to the specification of VPS

Chroma Phase 5AH

This register defines the absolute subcarrier phase w.r.t. the synchroniza-tion pulse scheme. Although in practice the absolute subcarrier phase is almost never relevant, values for the most common standards NTSC-M and European PAL are given. Please note that the value is different when the internal color bar function is active.

Gain_U, Gain_V 5BH - 5EH

These registers directly influence the amplitude of the internal color diffe-rence baseband signals and thus of the generated subcarrier for quadra-ture modulated standards (for SECAM, the frequency deviation is influenced!)Usually, the nominal settings given in the datasheet should be used; in case that an analog post filter contributes noticeable attenuation around the subcarrier frequency, both GAINU and GAINV should be enlarged accordingly.Note that the sign bit (0=positive, 1=negative) is located in 5DH for GAINU and in 5EH for GAINV.

Black Level 5DHThis parameter adds a certain offset to the luminance signal w.r.t. to the sync tip, but leaves the peak-peak amplitude unaffected.

Real Time Control 5DH - 5EH

IF DECOE=high, the odd/even information can be received from a deco-der supporting this function.If DECPH=high, a subcarrier oscillator phase reset initiated on the decoder side will reset the phase of the encoder oscillator.

Blanking Level 5EH - 5FH

This parameter adds a certain offset to the luminance blanking level w.r.t. the sync tip.Note that this parameter has to be set twice, i.e. outside (5EH) and inside (5FH) the vertical blanking interval. Usually, both blankings are identical.

NULL 60H Always program with 00H in order to avoid unexpected effects

Standard Control 61H

(0): configures the internal pixel counter either to 858 pixels/line (high) or 868 pixels/line (low)(1): this bit set to high enables the PAL specific process of inverting the V color difference component line by line.(2): usually set to high for standard-compliant chroma bandwidth; in some cases (e.g. for best S-Video quality), it can be set to low.(3): this bit set to high enables the SECAM processing; it overrides bit PAL(4): this bit selects one of two possible gain factors for the luminance black-to-white amplitude; when set to high, luminance is adjusted for 92.5 IRE output amplitude, and when set to low for 100 IRE output amplitude.(5): only relevant when RTCE bit is high; usually set to low.(6): if set to high, internally a constant code corresponding to the lowest possible output voltage at the DACs for CVBS, Y/C is applied.(7): if set to high,internally a constant code corresponding to the lowest possible output voltage at the DACs for R, G, B is applied.


28




Real Time Control Enable

62H

If RTCE is set to high, Real Time Control (RTC) of the generated subcar-rier frequency is enabled. RTC should be used whenever the clock for the video encoder is generated by a digital line-locked video decoder to ensure stable encoding phase for clean colors.

Burst Amplitude 62H

These registers directly influence the amplitude of the color burst for qua-drature modulated standards (for SECAM, the amplitude of the color burst cannot be modified!)Usually, the nominal settings given in the datasheet should be used; in case that an analog post filter contributes noticeable attenuation around the subcarrier frequency, this parameter should be enlarged accordingly.

Subcarrier Fre-quency

63H - 66HThe subcarrier frequency is synthesized by a 32 bit Discrete Time Oscilla-tor; all four bytes are fully programmable

Line 21 Encoding 67H - 6AHClosed Caption and Extended Data Service bytes to be downloaded inclu-ding parity bit at the MSB position of each byte.

RCV-Port Control 6BH

Handles input- or output signal of RCV1 and RCV2 pins (see correspon-ding table in the datasheet).Although the usual definition for master mode stands for trigger I/O’s to be switched to output, the device allows for a kind of mixed mode as to be sla-ved by a frame sync applied to pin RCV1 and simultaneously to output a horizontal pulse on pin RCV2.

H-Trigger Control 6CH - 6DHSets the Horizontal Trigger phase related to signal on RCV1 or RCV2. If a vertical sync is applied to RCV1, an additional horizontal sync at RCV2 is needed to adjust the position of video horizontally.

V- Trigger Control 6DHSets the Vertical Trigger phase related to the input signal on RCV1; value VTRIG - counting half lines - should be even, only.

Field Length Control 6EHInterlaced operation or two different non-interlaced modes are selectable for 525/60 signals or 625/50 signals.

Luma Delay 6EHdepending on LDEL1 and LDL0 bits, an extra delay of the luminance signal portion (for VBS or CVBS) can be added in order to compensate for group delay distortions of the analog post filter.

Phase Reset Mode of the colour subcar-rier generator

6EHThese two bits should exactly be set acc. to the table in the datasheet. For NTSC signals, both ’two-line reset’ or ’four-field reset’ are possible.

BLCKON 6EHthis bit set to low ensures normal operation, while set to high forces the all signals to blanking level.

V-Blanking Definition 6EH

setting this bit to low will define the Vertical Blanking Interval by the values loaded into registers FAL and LAL; if this bit is set to high, the Vertical Blanking Intervall is forced acc. to CCIR-624 (50Hz) or acc. to RS170A (60Hz)

Individual Line 21 Encoding

6FHTwo bits enabling field-dependent insertion of Closed Caption/ Eyxtended data.

Teletext Enable 6FHFor any line with Teletext insertion, this bit must be set to high, as it is a master switch. The actual selection for activated Text lines is made below.




29


Line Select for Clo-sed Caption or exten-ded data

6FHThis parameter selects one out of 32 possible position for Closed Caption encoding; usually it is line 21 for NTSC corresponding to 11h.

Start / End RCV2 70H - 72HThese registers define start and end of a pulse repeating at line frequency:Note that if ’Start’ is greater than ’End’, the pulse will be inverted.

Start / DelayTTXRQ 73H - 74H

Every high-state of the signal at pin TTXRQ - depending on the chosen Text format - initiates the transfer of a new Teletext bit stream bit; as this bit stream must match to the internal pixel counter, the start of the first request pulse is programmable by TTXHD to accomodate to indiviual lat-encies of the bit stream source. TTXHS is an internally needed parameter and should be taken as given in the datasheet.

VSYNC shift 75H

In master mode (RCV1 and RCV2 as outputs), sometimes the phase of the horizontal pulse on RCV2 must be shifted against the phase of the ver-tical sync pulse on RCV1 in steps of 27 MHz clock cycles. This can be accomblished with this parameter in 3 steps.

CSYNC advanced 75HIn order to compensate for shorter propagation of RGB signals through a TV SCART input, the alternative CSYNC signal on the (usually) CVBS DAC can be advanced up to 31 LLC clock cycles.

TTX odd / even request VS/VE

76H-79H, 7CH

For the odd and even field, the lines to carry Teletext information can be determined individually.Note that it is possible to nearly use the complete inactive and the com-plete active fields for Teletext insertion instead of video.

First / Last Active Line

7AH - 7CH

These parameters define the Vertical Blanking Interval if bit SBLBN = low. Main purpose is to widen the range for active video input, as the input data are ignored during the lines that are dedicated to belong to the Vertical Blanking Interval. E.g., Time code could be inserted through the video input port when FAL is programmed to start before the normal first active line.

TTX mode 7CH

TTXO set to low enables the universal TTX protocol: At every rising edge of TTXRQ a single TTX bit is requested.TTXO set to high enables the older TTX protocol for compatability rea-sons: The encoder provides a high state window of TTXRQ, and the length of the window depends on the chosen Text standard.Depending on the selected field frequency (Bit FISE), the Teletext stan-dard is being selected through TTX60

NULL 7DH Always program with 00H in order to avoid unexpected effects

Disable TTX Line 7EH - 7FH

Starting with line line 8, ending with line 23 inclusive, each of these lines can be disabled for Teletext insertion (the respective bit set to high), although enabled by the global window definitions for Teletext. This can be useful in order to allow e.g. other information entering through the video input to be inserted between lines containing Teletext.


30




6. Appendix: Schematics and Layout

The schematics (made in ORCAD) can be delivered on request.

For a board layout GERBER files are available.

31




6.1 Schematic

6.1.1 Top Sheet of 7128MOD2

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32




6.1.2 Connector In

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P1A M O D U L IN -C O N 96

A32

A31

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

P1B M O D U L IN - C O N 96

B32

B31

B30

B29

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

P1C M O D U L IN -C O N 96

C32

C31

C30

C29

C28

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

TP

TP

TP

TP

TP

TP

TP

TP

TP

TP

JP30

1 2

JP13

13

2

MP

[7..0

]

RE

SN

SC

L

SY

NC

[3..0

]

RC

V[2

..1]

TT

XT

TX

RQ

VD

D

VD

DA

VD

DA

N

SD

A

VP

[7..0

]

CLK

[3..0

]

SO

UR

CE

33




6.1.3 Connector Out

Tuesday

, A

pri

l 02, 1996

11

A4

914

Thu

rsday, O

cto

ber

09, 1997

O:\O

RC

AD

_97\C

HA

ME

LE

ON

\7128M

OD

2_IB

A.D

SN

CO

NN

_OU

T

PH

ILIP

S M

PC

-E

spe

ller

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

Mod

ify

:

Pat

h

Des

igne

r

A

A

D

DA

CVB

S0

CVB

S1

CVB

S2

RG

B

Y / C

"pla

ce s

ide

by s

ide"

Y / C

CVB

S

YC

OU

T1

YC

OU

T0

RG

BO

UT1

RG

BO

UT0

RG

BO

UT2

P4

SC

AR

T

CV

BS

out

19

CV

BS

Gnd

17

RE

D15

RE

D G

nd

13

GR

N11

GR

N G

nd

9

BL

7

BL G

nd

5

L o

ut

3

R o

ut

1

CV

BS

in

20

ST

RG

B G

nd

18

ST

RG

B16

D²B

Gnd

14

D²B

12

D²B

10

CT

RL I/O

8

L in

6

LR

Gnd

4

R in

2

GN

D21

P5

I2C

4P

CO

N

VC

C1

SD

A2

SC

L4

GN

D3

P6

I2C 6PCON

SD

A3

SC

L4

VC

C2

VC

C1

GN

D6

NC

5

U2

I2C

4P

CO

N_

NE

W

SD

A1

VC

C2

SC

L4

GN

D3

U1

I2C

4P

CO

N_

US

VC

C1

GN

D2

SD

A4

SC

L3

P2

5P

CO

NN

11

22

33

44

55

P3

CV

BS

_C

ON

1

2

12

JP

16

RG

B a

ctive

12

JP

15

13

2

JP

17

13

2

JP

14

13

2

JP

29

13

2

CV

BS

OU

T

SD

A

SC

L

VD

DA

VD

DA

N

YC

OU

T[1

..0]

RG

BO

UT

[2..0]

VD

D3,3

VD

D

34




6.1.4 SAA7138/39

Tue

sday

, A

pril 0

2, 1

996

11

A4

1314

Fri

day

, O

ctob

er 1

0, 1

997

O:\O

RC

AD

_97

\CH

AM

ELE

ON

\712

8MO

D2_

IBA

.DS

N

SAA

7128

/29

38/3

9

PHIL

IPS

MPC

-E

spel

ler

Title

Size

Doc

umen

t N

umbe

rR

ev

Dat

e:Sh

eet

o

fM

odif

y:

Pat

h

Des

igne

rD

D

A

D

D

D

D

D

A

MP7

MP6

MP5

MP4

MP3

MP2

MP1

MP0

VD

D3,

3

VD

D5

VDD

3,3

VDD

5

SYN C 3

SYN C 1

SYN C 0

SYN C 2

VDD

3,3

VD D 3,3

CLK

3

YC

1

YC

0

RG

B1

RG

B0

RG

B2

CLK

2

CLK

0

CLK

1

VP6

VP2

VP7

VP4

VP3

VP0

VP1

VP5

RC

V2R

CV1

CLK

0C

LK1

CLK

2C

LK3

VD

D3,

3V

DD

A3,3

VDD

A3,

3VD

D3,

3

R17

4k7

S1

RE

SE

T

C25

100

n

C26

100n

R23

0

R13

ope

n

R14

4k7

R15

4k7

R16

4k7

R18

4k7

C21

10p

L13

10µ

C22

1n

C23

100n

C24

100

n

R2

124

0R

R20

22R

CP

1

22µ

+

C20

10p

Y1

27M

Hz

R22

240R

R1

922

R

U5

SA

A71

38/

39

CHAMELEON_64

SAA 7138/39

res47

S CL58S DA59

RC

V2

12

RC

V1

11

V DD356

V SS 1 9

TT

X61

TT

XR

Q60

MP

713

MP

614

MP

515

SA 29

res 33res 19res 16

MP

420

MP

321

MP

222

MP

123

MP

024

V DD225

V SS 2 26

RT

CI

27

AP 7SP 6

RE SN 57

B (

Cb)

40

V DDA453 V DDA342 V DDA239 V DDA136

G (

Y)

37

R (

CR

)3

4

C (

CV

BS

)3

5

CV

BS

(C

SY

NC

)4

1

VS SA 2 44VS SA 1 30

VP

05

res48res 32

res50 res49

LLC1 8V DDI2C28

LLC2 17

LLCOUT 18

SOURCE 31

V DD110

V SS 3 55

VP

14

VP

23

VP

32

VP

41

VP

564

VP

663

VP

762

XT

AL

52

XT

ALI

51

VS SA 3 45

VB

S (

CV

BS

)3

8

VS SA 4 46

XC

LK5

4

res43

C3

1

100n

C33

100n

C3

2

100

n

JP23

HS

12

JP2

5

SA

1 2

JP27

TE

RM

LLC

1

12

JP28

TE

RM

LLC

2

12

JP24

OD

D / V

S1

3

2

JP

26R

ES

N

1 3

2

L16

open

SD

A

MP

[7..0]

VD

D5

SC

L

RC

V[2

..1]

SY

NC

[3..0]

VD

D3

,3V

DD

A3,

3

TT

X

CV

BS

YC

[1..0]

RG

B[2

..0

]

RE

SN

VP

[7..0]

SO

UR

CE

CLK

[3..0]

TT

XR

Q

35




6.1.5 SAA7128/29

Tuesday, S

epte

mber

02, 1997

11

A4

12

14

Tuesday, O

cto

ber

07, 1997

O:\O

RC

AD

_97\C

HA

ME

LE

ON

\7128M

OD

2_IB

A.D

SN

SA

A71

28/2

9 38

/39

PH

ILIP

S M

PC

-E/P

Dspeller

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

Mod

ify

:

Pat

h

Des

igne

r

U4

SA

A 7

128/2

9

CH

AM

ELE

ON

_44

AP 3SP 2

TT

X44

MP

79

MP

610

MP

313

MP

511

SA 21

RESN 40

CV

BS

(C

SY

NC

)30

VB

S (

CV

BS

)27

C (

CV

BS

)24

LLC 4

SCL41

SDA42

MP

412

MP

214

MP

115

MP

016

RC

V1

7R

CV

28

XT

AL

34

XT

ALI

35

VSS1 5

VDD217 VDD339

VDD16

VSSA2 32

TT

XR

Q43

RT

CI

19

VSSA1 22

res. 1

VDDA125 VDDA228 VDDA331 VDDA436

VSS2 18

G (

Y)

26

VDDI2C20

VSS3 38

R (

CR

)23

B (

Cb)

29

XC

LK

37

VSSA3 33

36




6.1.6 Output Filter 1..6

Wed

nesd

ay,

Apri

l 03

, 19

96

11

A4

11

14

Thu

rsday

, O

cto

ber

09, 1

997

O:\O

RC

AD

_97\

CH

AM

ELE

ON

\7128

MO

D2_I

BA

.DS

N

OUT

PUT

FILT

ER

PHIL

IPS

MPC

spel

ler

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

Mod

ify:

Path

Des

igne

r

A 5M

Hz

LOW

PA

SS

FIL

TE

R1

FIN

FO

UT

B 5M

Hz

LOW

PA

SS

FIL

TE

R2

FIN

FO

UT

C 5M

Hz

LOW

PA

SS

FIL

TE

R3

FIN

FO

UT

D 5M

Hz

LOW

PA

SS

FIL

TE

R4

FIN

FO

UT

E 5M

Hz

LOW

PA

SS

FIL

TE

R5

FIN

FO

UT

F 5M

Hz

LOW

PA

SS

FIL

TE

R6

FIN

FO

UT

YC

OU

T1

YC

OU

T0

RG

BOU

T2

RG

BOU

T1

RG

BOU

T0

YC

1

YC

0

YC

1

YC

0

RG

B1

RG

B0

RG

B2

R6

10R

R8

10R

R9

4,7

R

R10

22R

R12

22R

R7

10R

R5

10R

R11

22R

JP

21

5 R

12

JP

22

5 R

12

JP

31

Y/C

12

JP

32

SA

A71

26/2

71

2

CV

BS

YC

OU

T[1

..0]

CV

BS

OU

T

RG

B[2

..0]

RG

BO

UT

[2..0

]

YC

[1..0]

37




6.1.7 5MHz Lowpass Filter1

Wednesday, A

pri

l 03, 1996

11

A4

214

Thurs

day, O

cto

ber

09, 1997

O:\O

RC

AD

_97\C

HA

ME

LE

ON

\7128M

OD

2_IB

A.D

SN

5MH

z LO

WP

AS

S F

ILTE

R1

PH

ILIP

S M

PC

speller

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

Mod

ify

:

Pat

h

Des

igne

r

A

C2

390p

C3

560p

C1

120p

L1

2µ

H7

L2

2µ

H7

JP

1

JM

PIN

12

JP

2

JM

PO

UT

12

FO

UT

FIN

38





Wednesday, A

ugust 20, 1997

11

A4

314

Thurs

day, O

cto

ber

09, 1997

O:\O

RC

AD

_97\C

HA

ME

LE

ON

\7128M

OD

2_IB

A.D

SN

5MH

z LO

WP

AS

S F

ILTE

R2

PH

ILIP

S M

PC

-E/P

Dspeller

Title

Siz

eD

ocum

ent

Num

ber

Rev

Da

te:

She

et

o

fM

odif

y:

Pat

h

Des

igne

r

A

C5

390p

C6

560p

C4

120p

L3

2µ

H7

L4

2µ

H7

JP

3

JM

PIN

12

JP

4

JM

PO

UT

12

FO

UT

FIN

39





Wednesday, A

pri

l 03, 1996

11

A4

414

Thurs

day, O

cto

ber

09, 1997

O:\O

RC

AD

_97\C

HA

ME

LE

ON

\7128M

OD

2_IB

A.D

SN

5MH

z LO

WP

AS

S F

ILTE

R3

PH

ILIP

S M

PC

speller

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

Mod

ify

:

Pat

h

Des

igne

r

A

C8

390p

C9

560p

C7

120p

L5

2µ

H7

L6

2µ

H7

JP

5

JM

PIN

12

JP

6

JM

PO

UT

12

FO

UT

FIN

40





Wednesday, A

ugust 27, 1997

11

A4

514

Thurs

day, O

cto

ber

09, 1997

O:\O

RC

AD

_97\C

HA

ME

LE

ON

\7128M

OD

2_IB

A.D

SN

5M

Hz

LO

WP

AS

S F

ILT

ER

4

PH

ILIP

S M

PC

-E/P

Dspeller

Title

Siz

eD

oc

um

ent

Num

ber

Rev

Da

te:

Sheet

of

Modif

y:

Path

Desig

ner

A

L8

2µ

H7

JP

7

JM

PIN

12

C10

120p

C12

560p

C11

390p

JP

8

JM

PO

UT

12

L7

2µ

H7

FO

UT

FIN

41





Wednesday, A

ugust 27, 1997

11

A4

614

Thurs

day, O

cto

ber

09, 1997

O:\O

RC

AD

_97\C

HA

ME

LE

ON

\7128M

OD

2_IB

A.D

SN

5MH

z LO

WP

AS

S F

ILTE

R5

PH

ILIP

S M

PC

-E/P

Dspeller

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

Mod

ify

:

Pat

h

Des

igne

r

A

C13

120p

JP

10

JM

PO

UT

12

C14

390p

L10

2µ

H7

JP

9

JM

PIN

12C15

560p

L9

2µ

H7

FO

UT

FIN

42





Wedn

esday, A

ugust 27, 1

997

11

A4

71

4T

hu

rsday, O

cto

ber

09, 1997

O:\O

RC

AD

_97\C

HA

ME

LE

ON

\7128M

OD

2_IB

A.D

SN

5MH

z LO

WP

AS

S F

ILTE

R6

PH

ILIP

S M

PC

-E/P

Dspeller

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

Mod

ify

:

Pat

h

Des

igne

r

A

C17

390p

C18

560

p

C16

120p

L11

2µ

H7

L12

2µ

H7

JP

11

JM

PIN

12

JP

12

JM

PO

UT

12

FO

UT

FIN

43




6.1.13 I²C - EEPROM

Monday, M

arc

h 0

4, 1996

11

A4

10

14

Thurs

day, O

cto

ber

09, 1997

O:\O

RC

AD

_97\C

HA

ME

LE

ON

\7128M

OD

2_IB

A.D

SN

EE

PR

OM

PH

ILIP

S M

PC

-Espeller

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

Mod

ify

:

Pat

h

Des

igne

r

D

C19

3.3

n

U3

PC

F8598E

EE

PR

OM

SDA5 SCL6

VDD8 VSS 4

A0

1

A2

3

A1

2

PT

C7

R1

10K

R2

10K

R3

10K

R4

56k

JP

20

A2

12

JP

19

A1

12

JP

18

A0

12

SD

A

VD

D5

SC

L

44




6.1.14 Supply

Mond

ay,

Marc

h 04,

199

6

11

A4

1414

Thur

sda

y, O

cto

ber

09, 1

997

O:\O

RC

AD

_97\C

HA

ME

LE

ON

\712

8MO

D2_I

BA

.DS

N

SU

PP

LY

PH

ILIP

S M

PC

-Espel

ler

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

Mod

ify:

Path

Des

igne

r

A

D

DA

D

Fer

rit

Ferr

it

C27

470

n

CP

2

47µ

+

R24 0

L14

Ferr

it 2

.2µ

P9

DG

ND

GND TP

P10

AG

ND

GND TP

R25 0

CP

7

47µ

+

L15

Ferr

it 2

.2µ

RE

G2

LM

394

0V

I1

VO

3

GND 2

C29

470

n

C30

100

n

CP

4

100

µ

+

C28

100

n

RE

G1

LM

394

0V

I1

VO

3

GND 2

CP

3

100µ

+

VD

DA

VD

DV

DD

3,3

VD

D5

VD

DA

3,3

45




6.2 Layout

6.2.1 Top Placement of 7128MOD2

46




6.2.2 Routing of Top Layer of 7128MOD2

47




6.2.3 Top Solder Mask of 7128MOD2

48




6.2.4 Bottom Placement of 7128MOD2

49




6.2.5 Bottom Layer of 7128MOD2

50




6.2.6 Bottom Solder Mask of 7128MOD2

51




6.2.7 Ground plane layer of 7128MOD2 (Mid Layer1)

52




6.2.8 Routing of Power Supply Layer of 7128MOD2 (Mid Layer2)



53


datasheet

Documents

7128mod2 application

application note

analog video signals

analog video input signal

digital output signal

digital signal processing

different video decoders

various video encoders