Datapath Components · Datapath Components Multipliers, Counters, Timers, Register Files. 8 Multipliers ... slide) Instead, ALU design uses single adder, plus logic in front of adder’s

DatapathComponents

Multipliers,

Counters, Timers,

Register Files

8

Multipliers

� An N x N multiplier �Multiplies two N bit binary inputs�Generates an N+N bit result

� Creating a multiplier using two-level logic from a truth table results in too complex a design.

� A reasonably sized circuit can be designed by evaluating how humans do multiplication.

+

Multiplication Process

� Multiply two 4-bit numbers: 1100 and 0101

1100 (multiplicand)x 0101 (multiplier)

1100 (multiply multiplicand by the multiplier LSB)0000 (shift by one digit and multiply by next multiplier bit)

1100 (repeat)+ 0000 (repeat)00111100 (sum all the partial products)

� Each intermediary value is known as a partial product.� Partial Products can be obtained by ANDing the

corresponding multiplier bit with the multiplicand.

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Multiplication Process Revisited

� The process we just evaluated can be rewritten in terms of bit positions as:

a3 a2 a1 a0

b3 b2 b1 b0

b0a3 b0a2 b0a1 b0a0 (pp1)

b1a3 b1a2 b1a1 b1a0 (pp2)

b2a3 b2a2 b2a1 b2a0 (pp3)

b3a3 b3a2 b3a1 b3a0 (pp4)

p7 p6 p5 p4 p3 p2 p1 p0

� After generating the partial products, we sum them together

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Multiplier Circuit

5

A B

P*

Block symbol

+ (5-bit)

+ (6-bit)

+ (7-bit)

0 0

0 0 0

0

a0a1a2a3

b0

b1

b2

b3

0

p7..p0

pp1

pp2

pp3

pp4

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Arithmetic Logic Unit (ALU)

� An ALU is a combinational component designed to perform many different mathematical operations.

� Generally built one of three ways:� All mathematical operations are done in parallel and one

result is selected using a mux.

� Based on a single adder with combinational logic that controls the mode.

� A combination of the previous two methods

Parallel Computation ALU

� Can build using separate components for each operation, and muxes� Too many wires, also wastes power

computing operations when only use one result at given time

� Inefficient for large designs

DIP switches

1

0

8-bit register

8-bit 8x1

CALC

LEDs

e

z

yx

clk

Id

s0s1s2

1 0 0 1 2 3 4 5 6 7

NOTXORORAND+1+

8 8

8

88

8

8

8 88

88

A B

A lot of wires

Wastedpower—

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Single Adder ALU� More efficient design uses a single adder

� ALU design not just separate components multiplexed (same problem as previous slide)

� Instead, ALU design uses single adder, plus logic in front of adder’s A and B inputs� Logic in front is called an arithmetic-logic extender

� Extender modifies A and B inputs so desired operation appears at output of the adder

(a)

ALU

IA IB

IS

Adder cin

A B

S

xyz

AL-extender

abext abext abext cinext

AL-extender

ia7 ib7

a7 b7

ia6 ib6

a6 b6

ia0 ib0

a0 b0

cin

(b)

xyz

a

Arithmetic-Logic Extender

� xyz=000 Want S=A+B : just pass a to ia, b to ib, and set cin=0� xyz=001 Want S=A-B : pass a to ia, b’ to ib and set cin=1 (two’s complement)

� xyz=010 Want S=A+1 : pass a to ia, set ib=0, and set cin=1� xyz=011 Want S=A : pass a to ia, set ib=0, and set cin=0� xyz=100 Want S=A AND B : set ia=a*b, b=0, and cin=0� Others: likewise� Based on above, create logic for ia(x,y,z,a,b) and ib(x,y,z,a,b) for each abext, and create

logic for cin(x,y,z), to complete design of the AL-extender component

abext abext abext cinext

xyz

AL-extender

ia7 ib7

a7 b7

ia6 ib6

a6 b6

ia0 ib0

a0 b0

cin

(b)

(a)

ALU

IA IB

IS

Adder cin

A B

AL-extender

S

xyz

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Bit shifter

� A combinational logic construct to shift bits.� Similar to a shift register, but has no storage� Associated with the symbols

� << M (Shift Left M bits)� >> M (Shift Right M bits)

� Simple Shifter� Shifts N-bit data by a fixed amount, M� May be designed to shift left, right, or not at all.

� Shift Multiplication� Shifting by one bit multiplies or divides by 2

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Barrel Shifter

� An N-bit shifter that can shift any number of positions.

� Constructed by using multiple simple bit shifters that shift by powers of two, if enabled.

Left Barrel Shifter

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Counters

� Counters are sequential components that maintain an internal count variable that can be incremented or decremented.

� Types� UP only� Down only � Bidirectional

� Counters “roll over” when exceeding their bit resolution� i.e. a 4 bit up-counter goes from 0 to 15 and then wraps back around to

0.� Think of it as a clock rolling from 12 to 1.

� Counters generally have a bit that indicates they have reached the extent of their range.

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N-bit Up Counter

� The count output (C) counts up from zero to 2N.

� Terminal Count (tc) is asserted when the count is equal to 2N.

C[0]

C[1]

C[2]

C[3]

C[3:0]D[3:0] Q[3:0]

QN[7:0]

Load

Rst

D_Reg_PL_Rst_4bit

AND4

S[3:0]

co

a[3:0]

Incr_4bit

tc

C

clk

cnt

clr

+

N-bit Down Counter

� To create a down counter from an UP counter� Replace the incrementer with a decrementer.

� Replace the AND with a NOR

D[3:0] Q[3:0]

QN[7:0]

Load

Rst

D_Reg_PL_Rst_4bit

S[3:0]

co

a[3:0]

Decr_4bit

clr

cnt

clk

C

tcNOR4

C[3:0]

C[3]C[2]

C[1]C[0]

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N-bit Bidirectional Counter

� Implement the logic of both UP and DOWN counters

� Select between them using MUXes

D

I0

I1

S

mux_2_1

C[3:0]

C[0]

C[1]

C[2]

C[3]

C[0]C[1]

C

tc

clr

cnt

clk

D[3:0] Q[3:0]

QN[7:0]

Load

Rst

D_Reg_PL_Rst_4bit

AND4

S[3:0]

co

a[3:0]

Incr_4bit

S[3:0]

co

a[3:0]

Decr_4bit

NOR4

D[3:0]

I0[3:0]

I1[3:0]

S

mux_2_1_4bit

C[2]C[3]

dir

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Counter with Load

� Add a mux to the register input.�Select between loading next count of a new

value.

D[3:0] Q[3:0]

QN[7:0]

Load

Rst

D_Reg_PL_Rst_4bit

AND4

S[3:0]

co

a[3:0]

Incr_4bit

OR

D[3

:0]

I0[3

:0]

I1[3

:0]

Smux_2_1_4bit

clr

load

L[3:0]

cnt

clk

C

tc

C[0]

C[1]

C[2]

C[3]

C[3:0]

Up counter with load

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Modulo Counter

� Some times it is desirable to stop counting before the end of the counter’s bit range. � This can be done using external logic to reset the counter when the

desired upper limit is reached.

� Example: Design a circuit that counts from 0 to 9 using the given counter.

� Question: Can you design a circuit that starts counting at 2 instead of 0?

cnt

load

clk

C[3:0]L[4:0]

clr

up_cnt_4bit

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Clock Divider

� It is often useful to generate a slower clock.�For a small duty cycle, you can use the tc

output as a clock signal.

�For a large duty cycle, extra combinational logic is required to generate the clock cycle

� Example: Create a circuit using a 4-bit counter to create a % 4 clock divider.

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Measuring Time

� Counters may also be used to measure time.

� We know the frequency of the clock signal, so we know how long it takes between counts.

� Example: If we have a 25 MHz clock (40 ns period), how much time has passed in 15 clock ticks?

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Timers

� Timers repeatedly assert a signal, Q, after a predetermined time.�Can be made in a similar fashion to the modulo

counter.�When count is reached, reset the circuit and

assert Q.

� Example: Create a timer that asserts Q after 120ns using a 25Mhz clock.

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Variations on the Basic Timer

� One-shot�Only asserts the output Q once and then must

wait to be enabled again.

� Pulse Width Modulator�Has a second register that sets the amount of

time Q is held HIGH.� Very similar to a clock divider� Allows you to control the duty cycle.

姐Ϸ

Register Files

� Register Files are an array of memory.�Provides quick, efficient access to storage.

�Generally defined as M x N, where M is the number of registers in the file and N is the bit-length of each register.

�A particular register is accessed via its address, a unique binary code that represents the register.

�Generally allows both read & write access.

裰Ћ

Why Use Register Files?

� Why not just use a lot of registers?�Theoretically, a gate has infinite input impedance

and zero output impedance� If true, a gate output could drive an unlimited number of

gate inputs.

�Realistically, gates have limited fan-out.� It is not possible for a single gate to drive a large

number of registers.� Register files solve this by ensuring only one gate is

read or written at a time.

泀ϵ

Register File Symbol

� MxN register file: Efficient design for one-at-a-time write/read of many registers

N

log2(M)

W_data

W_addr

W_en

N

log2(M)

R_data

R_addr

R_en16×32

register filea

N-bit data to write

log2(M) -bit “address” specifies

which register to write

Enable (load) line: Reg

written on next clock

M-bit address to specifies

which register to read

Enable read

N-bit data that is read

Called “write port”

“read port”

25

C

d0

d1

d2

d3e

i0

i0

i1

i2

i3

a0

a1

load

i1

2×48

8

8

8

8Dd

8

x y

s1 s0

8-bit4×1

load

load

load

load

reg0

reg1

reg2

reg3

T

A

I

M

Register Files� Addresses are inputs to

decoders to select the correct register� Write decoder sets the

load signal.� Read multiplexor enables

one and only one buffer to drive the read output.

� Accessing one of several registers is:� OK if just a few registers

� Problematic when many

� Ex: 16 registers� Too much fanout (branching of wire):

Weakens signal

� Many wires: Congestion

4.10

4 32-bit registers tolerable

congestion

too muchfanout

huge mux

C

d0

d15e

i0

i15load

i3-i0

4x1632

32

32

32

4

Dd

s3-s0

32-bit16x1

load

load

reg0

reg15

a

16 32-bit registers

begins to have fanout and wire

problems

9

9

9

99

9

16*32 =

512 wires

�Ї

26

Register File

� Internal design uses drivers and bus

a

a

d0

d1

d2

d3e

i0

d0

d1

d2

d3

W_en

W_addr

W_data

i1

2x4

3232

32

32

32

32

i1i0

e

2x4

load

load

load

load

reg0

reg1

reg2

reg3

R_en

R_addr

R_data

driver

bus

writedecoder

readdecoder

4x32 register file

Internal design of 4x32 RF; 16x32 RF follows similarly

1

1

9

1

q

c=1: q=d

c

c=0: q= Z′

d

′ d qd q

like no connection

three-state driver

q

q=d

d

driver

Boosts signal

9

9

99

9

Note: Each driver in figure

actually represents 32 1-bit drivers

1

1

1

1

9

19

9 9

Notice the shared bus.R_data is written to by multiple three state buffers, but only one at a time.

+

27

Register File Timing Diagram

� Can write one register and read one register each clock cycle� May be same

register

32

2

32

2

W_data

W_addr

W_en

R_data

R_addr

R_en4x32

register file

0:

1:2:3:

?

??9

0:

1:2:3:

?

22?9

0:

1:2:3:

?

22?9

0:

1:2:3:

?

22?9

0:

1:2:3:

?

221779

0:

1:2:3:

?

22177555

0:

1:2:3:

?

??

?

9

3

Z

X

22

1 X

X

X 2 3

X 177 555

Z Z Z9 9 55522

X X3 31

cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6clk

W_data

R_data

W_addr

R_addr

W_en

R_en

1 2 3 654