ACPL-333J 2.5 Amp Output Current IGBT Gate Driver Optocoupler with Integrated (V CE ) Desaturation Detection, UVLO Fault Status Feedback, Active Miller Clamp and Auto-Fault Reset Data Sheet Features • 2.5 A maximum peak output current • 2.0 A minimum peak output current • 250 ns maximum propagation delay over temperature range • 1.7A Active Miller Clamp.Clamp pin short to V EE if not used • Desaturation Detection • Under Voltage Lock-Out Protection (UVLO) with Hysteresis • Open Collector Isolated fault feedback • “Soft” IGBT Turn-off • Automatic Fault Reset after fixed mute time , typical 26ms • Available in SO-16 package • 100 ns maximum pulse width distortion (PWD) • 15 kV/µs minimum common mode rejection (CMR) at V CM = 1500 V • I CC(max) < 5 mA maximum supply current • Wide V CC operating range: 15 V to 30 V over temperature range • Wide operating temperature range: –40°C to 105°C • Safety approvals: UL approval, 3750 V RMS for 1 minute, CSA approval, IEC/EN/DIN-EN 60747-5-2 approval V IORM = 891 V PEAK Applications • Isolated IGBT/Power MOSFET gate drive • AC and brushless DC motor drives • Industrial inverters and Uninterruptible Power Supply (UPS) Description The ACPL-333J is an advanced 2.5 A output current, easy- to-use, intelligent gate drivers which make IGBT V CE fault protection compact, affordable, and easy-to implement. Features such as integrated V CE detection, under voltage lockout (UVLO), “soft” IGBT turn-off, isolated open collector fault feedback, active Miller clamping and Auto- fault reset provide maximum design flexibility and circuit protection. The ACPL-333J contains a GaAsP LED. The LED is optically coupled to an integrated circuit with a power output stage. ACPL-333J are ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The voltage and current supplied by these optocouplers make them ideally suited for directly driving IGBTs with ratings up to 1200 V and 150 A. For IGBTs with higher ratings, the ACPL-333J can be used to drive a discrete power stage which drives the IGBT gate. The ACPL-333J have an insula- tion voltage of V IORM = 891 V PEAK . Block Diagram SHIELD SHIELD D R I V E R V E DESAT V CC2 V OUT V CLAMP V EE V CC1 V S FAULT ANODE CATHODE V CLAMP V LED 6, 7 5, 8 2 3 1, 4 13 11 14 9, 12 10 16 15 DESAT UVLO LED1 LED2 SHIELD SHIELD D R I V E R V E DESAT V CC2 V OUT V CLAMP V EE V CC1 V S FAULT ANODE CATHODE V CLAMP V LED 6, 7 5, 8 2 3 1, 4 13 11 14 9, 12 10 16 15 DESAT UVLO LED1 LED2 CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product
24
Embed
Data Sheet - docs-europe.electrocomponents.comdocs-europe.electrocomponents.com/webdocs/0db7/... · ACPL-333J 2.5 Amp Output Current IGBT Gate Driver Optocoupler with Integrated (VCE)
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
ACPL-333J2.5 Amp Output Current IGBT Gate Driver Optocoupler with Integrated (VCE) Desaturation Detection, UVLO Fault Status Feedback, Active Miller Clamp and Auto-Fault Reset
TheACPL-333JcontainsaGaAsPLED.TheLEDisopticallycoupledtoanintegratedcircuitwithapoweroutputstage.ACPL-333J are ideally suited for driving power IGBTs andMOSFETsused inmotorcontrol inverterapplications.Thevoltageandcurrentsuppliedbytheseoptocouplersmakethem ideally suited for directly driving IGBTs with ratingsupto1200Vand150A.ForIGBTswithhigherratings,theACPL-333J can be used to drive a discrete power stagewhichdrivestheIGBTgate.TheACPL-333Jhaveaninsula-tionvoltageofVIORM=891VPEAK.
Block Diagram
SHIELD
SHIELD
DRIVER
VE
DESAT
VCC2
VOUT
VCLAMP
VEE
VCC1
VS
FAULT
ANODE
CATHODE
VCLAMP
VLED
6, 7
5, 8
2
3
1, 4
13
11
14
9, 12
10
16
15
DESAT
UVLO
LED1
LED2
SHIELD
SHIELD
DRIVER
VE
DESAT
VCC2
VOUT
VCLAMP
VEE
VCC1
VS
FAULT
ANODE
CATHODE
VCLAMP
VLED
6, 7
5, 8
2
3
1, 4
13
11
14
9, 12
10
16
15
DESAT
UVLO
LED1
LED2
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Lead (Pb) FreeRoHS 6 fullycompliant
RoHS 6 fully compliant options available;-xxxE denotes a lead-free product
PREHEATING RATE 3 °C + 1 °C/ - 0.5 ° C/SEC.REFLOW HEATING RATE 2.5 °C ± 0.5 ° C/SEC.
217 °C
RAMP-DOWN6 °C/SEC. MAX.
RAMP-UP3 °C/SEC. MAX.
150 - 200 °C
260 +0/-5 °C
t 25 °C to PEAK
60 to 150 SEC.
20-40 SEC.
TIME WITHIN 5°C of ACTUALPEAK TEMPERATURE
tp
tsPREHEAT
60 to 180 SEC.
tL
TL
TsmaxTsmin
25
Tp
TIME
TEMP
ERAT
URE
NO TES:THE TIME FROM 25°C to PEAK TEMPERATURE = 8 MINUTES MAX.Tsmax = 200 °C, Tsmin = 150 °C
Note:Non-halidefluxshouldbeused.
5
Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*
Description Symbol Characteristic UnitInstallationclassificationperDINVDE0110/1.89,Table1forratedmainsvoltage≤150Vrmsforratedmainsvoltage≤300Vrmsforratedmainsvoltage≤600Vrms
* Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.SurfacemountclassificationisclassAinaccordancewithCECCOO802.
airflow.SeetheThermalModelsectionintheapplicationnotesattheendofthisdatasheetfordetailsonhowtoestimatejunctiontemperatureandpowerdissipation.InmostcasestheabsolutemaximumoutputICjunctiontemperatureisthelimitingfactor.Theactualpowerdissipationachievablewilldependontheapplicationenvironment(PCBLayout,airflow,partplacement,etc.).SeetheRecommendedPCBLayoutsectionin the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC powerdissipationdoesnotrequirederating.
3. Maximum pulse width = 10 µs.This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. Deratelinearlyfrom3.0Aat+25°Cto2.5Aat+105°C.ThiscompensatesforincreasedIOPEAKduetochangesinVOLovertemperature.
threshold of 12.5V. For High Level OutputVoltage testing,VOH is measured with a dc load current.When driving capacitive loads,VOH willapproachVCCasIOHapproacheszerounits.
voltagedependent.20. FaultReset:This is theamountof timewhenVOUTwillbeasserted lowafterDESAT threshold isexceeded.See theDescriptionofOperation
(FaultReset)topicintheapplicationinformationsection.21. Commonmodetransient immunity inthehighstate is themaximumtolerabledVCM/dtofthecommonmodepulse,VCM,toassurethatthe
outputwillremaininthehighstate(i.e.,VO>15VorFAULT>2V).A100pFanda2.1kΩpull-upresistorisneededinfaultdetectionmode.22. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse,VCM, to assure that the
Figure 2. IOH vs. temperature Figure 3. IOL vs. temperature
Figure 4. VOH vs. temperature Figure 5. VOL vs. temperature
1.0
1.5
2.0
2.5
3.0
-40 -20 0 20 40 60 80 105TA - TEMPERATURE - oC
I OH
-OUT
PUT
HIGH
CURR
ENT
-A
0
1
2
3
4
5
-40 -20 0 20 40 60 80 105TA - TEMPERATURE - o C
I OL
-OUT
PUT
LOW
CURR
ENT
-----VOUT =VEE +15V___VOUT =VEE +2.5V
0
0.05
0.1
0.15
0.2
0.25
-40 -20 0 20 40 60 80 105TA - TEMPERATURE - o C
V OL
-OUT
PUT
LOW
VOLT
AGE
-V
Figure . VOUT propagation elay waveforms
IF
V OUT
tPHLtPLH
t ft r
10%
50%
90%
T A - TEMPERATURE - o C
(VOH
-VCC
)-HI
GHOU
TPUT
VOLT
AGE
DROP
-V
-2.5
-2
-1.5
-1
-0.5
0
-40 -20 0 20 40 60 80 100
____I OUT = -650uA
11
Figure 8. ICL vs. temperature
0
1
2
3
4
-40 -20 0 20 40 60 80 105
TA -TEMPERATURE- o C
I CL-C
LAMP
LOW
LEVE
NSI
NKIN
GCU
RREN
T
15 20 25 302.25
2.35
2.45
2.55
2.65
VCC2 - OUTPUR SUPPLY VOLTAGE - V
I CC2 -
OUT
PUT S
UPPL
Y CU
RREN
T - m
A
---------I Cc 2H_________ICC2L
2.00
2.25
2.50
2.75
3.00
3.25
3.50
-40 -20 0 20 40 60 80 105TA - TEMPERATURE - oC
I CC2
-OUT
PUTS
UPPL
YCU
RREN
T-mA - ---- ----I CC2 H
_________ICC2L
-0.35
-0.30
-0.25
-0.20
-40 -20 0 20 40 60 80 105
TA - TEMPERATURE - o C
I CH-B
LANK
ING
CAPA
CITO
RCH
ARGI
NGCU
RREN
T-m
A
Figure 9. ICC2 vs. temperature
Figure 0. ICC2 vs. VCC2 Figure . ICHG vs. temperature
28.0
28.5
29.0
29.5
30.0
0 0.2 0.4 0.6 0.8 1
IOH - OUTPUT HIGH CURRENT - A
V OH -
HIG
H OU
TPUT
VOL
TAGE
DRO
P - V
_ _ _ _ 100 oC______ 25 oC--------- -40 oC
Figure 6. VOH vs. IOH Figure 7. VOL vs. IOL
0
1
2
3
4
5
6
7
8
0 0.5 1 1.5 2 2.5IoL - OUTPUT LOW CURRENT - A
V OL -
LOW
OUT
PUT
VOLT
AGE
DROP
- V
_ _ _ _ 100 o C______ 25 o C--------- -40 o C
12
Figure 4. Propagation elay vs. supply voltage
100
150
200
250
300
15 20 25 30Vcc - SUPPLY VOLTAGE - V
T P -
PROP
AGAT
ION
DELA
Y - n
s
----------t PLH_______t PHL
100
150
200
250
300
0 10 20 30 40 50LOAD RESISTANCE - ohm
T P -
PROP
AGAT
ION
DELA
Y - m
s ----------t PLH_______t PHL
Figure 5. Propagation elay vs. loa resistance
Figure 6. Propagation elay vs. loa capacitance
0
100
200
300
0 10 20 30 40 50LOAD CAPACITANCE - nF
----------t PLH_______t PHL
T P -
PROP
AGAT
ION
DELA
Y - m
s
Figure 2. DESAT threshol vs. temperature Figure 3. Propagation elay vs. temperature
6.0
6.5
7.0
7.5
-40 -20 0 20 40 60 80 105TA - TEMPERATURE - o C
V DES
AT-D
ESAT
THRE
SHOL
D-V
100
150
200
250
300
-40 -20 0 20 40 60 80 105TA - TEMPERATURE - o C
T P-P
ROPA
GATI
ONDE
LAY
-ns
----------t PLH_______t PHL
1
Figure 8. DESAT sense to 0% VOUT elay vs. temperature
1.0
1.5
2.0
2.5
3.0
-40 -20 0 20 40 60 80 105
T A - TEMPERATURE - o C
TDESA
T-D
ESAT
Sens
eto1
0%Vo
Delay
-us
-------Vcc2 =15V_____Vcc2 =30V
Figure 9. DESAT sense to 0% VOUT elay vs. loa resistance
0.0
1.0
2.0
3.0
4.0
10 20 30 40 50
LOAD RESISTANCE - ohm
-------Vcc2 =15V_____V cc2 =30V
TDESA
T10%
- DE
SAT
Sens
e to 1
0% V
o Dela
y - us
0.000
0.004
0.008
0.012
0 10 20 30 40 50
LOAD CAPACITANCE - nF
-------V cc2 =15V_____V cc2 =30V
TDESA
T10%
- DE
SAT
Sens
e to 1
0% V
o Dela
y - m
s
Figure 20. DESAT sense to 0% VOUT elay vs. loa capacitance
100
150
200
250
300
-40 -20 0 20 40 60 80 105
TA - TEMPERATURE - o C
TDESA
T90%
-DES
ATSe
nset
o90%
VoDe
lay-n
s
Figure 7. DESAT sense to 90% VOUT elay vs. temperature
1
Figure 2. IOH Pulse test circuit
Figure 22. IOL Pulse test circuit
Figure 23. VOH Pulse test circuit
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_10mA
+_
0.1µF
0.1µF
15V Pulsed
IOUT
30V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
VS
CATHODE
ANODE
ANODE
CATHODE
+_10mA
+_
0.1µF0.1µF
0.1µF0.1µF
15V Pulsed
IOUT
30V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_+_
0.1µF
0.1µF
15V Pulsed
IOUT
30V+_
0.1µF
0.1µF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_
0.1µF
0.1µF
VOUT
30V
10mA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
VS
CATHODE
ANODE
ANODE
CATHODE
+_
0.1µF
0.1µF
10mA10mA 650µA
15
Figure 24. VOL Pulse test circuit
Figure 25. ICC2H test circuit
Figure 26. ICC2L test circuit
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_
0.1µF
0.1µF
ICC2
30V
10mA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_
0.1µF0.1µF
0.1µF0.1µF
ICC2
30V
10mA10mA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_
0.1µF
0.1µF30V
I CC2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
VS
CATHODE
ANODE
ANODE
CATHODE
+_
0.1µF0.1µF
0.1µF0.1µF30V
I CC2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_
0.1µF
0.1µF
VOUT
30V
0.1µFF
0.1µF
100mA
1
Figure 27. ICHG Pulse test circuit
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_
0.1µF
0.1µF
ICHG
30V
10mA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_
0.1µF
0.1µF
ICHG
30V
10mA10mA
Figure 28. IDSCHG test circuit
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_
0.1µF
0.1µF
7V
30V
+_
IDSCHG
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_
0.1µF
0.1µF
7V
30V
+_
IDSCHG
Figure 29. tPLH, tPHL, tf, tr, test circuit
10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_
0.1µF
0.1µF
VOUT
30V10Ω
10mA, 10kHz, 50% Duty Cycle
10nF10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_0.1µF0.1µF
VOUT
30V
10mA, 10kHz, 50% Duty Cycle
1
VCM
10
10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
0.1µF
SCOPE
30V
430Ω
2.1kΩ
0.1µF
15pF
5V
VCM
10Ω
10nF10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
0.1µF0.1µF
SCOPE
30V
0.1µF0.1µF
15pF15pF
5V5V
VCM
10Ω
10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
0.1µF
SCOPE
30V
430Ω
2.1kΩ
0.1µF
15pF
5V
VCM
10nF10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
0.1µF0.1µF
SCOPE
30V
0.1µF0.1µF
15pF15pF
5V5V
Figure 30. tDESAT fault test circuit
10nF
+_
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_
5V
0.1µF
0.1µF
VOUT
30V10Ω
VIN
2.1kΩVFAULT
10mA 10nF
+_
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
VS
CATHODE
ANODE
ANODE
CATHODE
+_
5V
0.1µF0.1µF
0.1µF0.1µF
VOUT
30V
VIN
VFAULT
10mA10mA
Figure 3. CMR Test circuit LED2 off
Figure 32. CMR Test Circuit LED2 on
1
Figure 33. CMR Test circuit LED off
10
10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
0.1µF
SCOPE
30V
VCM
430Ω
2.1kΩ
0.1µF
15pF
5V
1010Ω
10nF10nF
0.1µF0.1µF
SCOPE
30V
Figure 34. CMR Test Circuit LED on
VCM
10
10nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
0.1µF
SCOPE
30V
430
2.1k
0.1µF
15pF
5V
SCOPE
2.1kΩ
0.1µF
15pF
5V
Ω
Ω
1
Application Information
Product Overview Description
The ACPL-333J are highly integrated power controldevices that incorporate all the necessary componentsforacomplete,isolatedIGBT/MOSFETgatedrivecircuitwith fault protection and feedback into one SO-16package.ActiveMillerclampfunctioneliminatestheneedofnegativegatedriveinmostapplicationandallowstheuse of simple bootstrap supply for high side driver. Anoptically isolated power output stage drives IGBTs withpower ratings of up to 150 A and 1200V. A high speedinternal optical link minimizes the propagation delaysbetweenthemicrocontrollerandtheIGBTwhileallowingthetwosystemstooperateatverylargecommonmodevoltagedifferencesthatarecommonin industrialmotordrivesandotherpowerswitchingapplications.AnoutputIC provides local protection for the IGBT to preventdamage during over current, and a second optical linkprovides a fully isolated fault status feedback signal forthe microcontroller. A built in“watchdog” circuit, UVLOmonitorsthepowerstagesupplyvoltagetopreventIGBTcausedbyinsufficientgatedrivevoltages.ThisintegratedIGBTgatedriverisdesignedtoincreasetheperformanceandreliabilityofamotordrivewithoutthecost,size,andcomplexityofadiscretedesign.
Two light emitting diodes and two integrated circuitshoused in the same SO-16 package provide the inputcontrolcircuitry,theoutputpowerstage,andtwoopticalchannels. The output Detector IC is designed manufac-tured on a high voltage BiCMOS/Power DMOS process.The forward optical signal path, as indicated by LED1,transmitsthegatecontrolsignal.Thereturnopticalsignalpath, as indicated by LED2, transmits the fault statusfeedbacksignal.
Figure 35. Block Diagram of ACPL-333J
SHIELD
SHIELD
DRIVER
VE
DESAT
VCC2
VOUT
VCLAMP
VEE
VCC1
VS
FAULT
ANODE
CATHODE
VCLAMP
VLED
6, 7
5, 8
2
3
1, 4
13
11
14
9, 12
10
16
15
DESAT
UVLO
LED1
LED2
SHIELD
SHIELD
DRIVER
VE
DESAT
VCC2
VOUT
VCLAMP
VEE
VCC1
VS
FAULT
ANODE
CATHODE
VCLAMP
VLED
6, 7
5, 8
2
3
1, 4
13
11
14
9, 12
10
16
15
DESAT
UVLO
LED1
LED2
Under normal operation, the LED1 directly controls theIGBT gate through the isolated output detector IC, andLED2 remains off. When an IGBT fault is detected, theoutputdetectorICimmediatelybeginsa“soft”shutdownsequence, reducing the IGBT current to zero in a con-trolled manner to avoid potential IGBT damage frominductiveover voltages.Simultaneously, this fault statusistransmittedbacktotheinputviaLED2,wherethefaultlatch disables the gate control input and the active lowfaultoutputalertsthemicrocontroller.
During power-up, the Under Voltage Lockout (UVLO)feature prevents the application of insufficient gatevoltage to the IGBT, by forcing the ACPL-333J ’s outputlow.Oncetheoutputisinthehighstate,theDESAT(VCE)detection feature of the ACPL-333J provides IGBT pro-tection. Thus, UVLO and DESAT work in conjunction toprovideconstantIGBTprotection.
Recommended Application Circuit
The ACPL-333J have an LED input gate control, and anopen collector fault output suitable for wired‘OR’ appli-cations. The recommended application circuit shown inFigure36(page21)illustratesatypicalgatedriveimple-mentationusingtheACPL-333J.The followingdescribesabout driving IGBT. However, it is also applicable toMOSFET. Depending upon the MOSFET or IGBT gatethreshold requirements, designers may want to adjusttheVCC supply voltage (RecommendedVCC = 17.5V forIGBTand12.5VforMOSFET).
The two supply bypass capacitors (0.1 µF) provide thelarge transient currents necessary during a switchingtransition.Becauseofthetransientnatureofthechargingcurrents,a lowcurrent (5mA)powersupplysuffices.ThedesaturationdiodeDDESAT600V/1200Vfastrecoverytype,trr below 75ns (e.g. ERA34-10) and capacitor CBLANK arenecessary external components for the fault detectioncircuitry.ThegateresistorRGservesto limitgatechargecurrent and controls the IGBT collector voltage riseand fall times. The open collector fault output has apassivepull-upresistorRF(2.1kW)anda330pFfilteringcapacitor, CF. A 47 kW pull down resistor RPULL-DOWN onVOUT provides a predictable high level output voltage(VOH). In this application, the IGBT gate driver will shutdown when a fault is detected and fault reset by nextcycleofIGBTturnon.Applicationnotesarementionedattheendofthisdatasheet.
20
Description of Operation
Normal Operation
During normal operation,VOUT of the ACPL-333J is con-trolled by input LED current IF (pins 5, 6, 7 and 8), withthe IGBT collector-to-emitter voltage being monitoredthroughDDESAT.TheFAULToutputishigh.SeeFigure37.
Fault Condition
TheDESATpinmonitors the IGBTVcevoltage.WhenthevoltageontheDESATpinexceeds6.5VwhiletheIGBTison,VOUTisslowlybroughtlowinorderto“softly”turn-offthe IGBT and prevent large di/dt induced voltages. Alsoactivated is an internal feedback channel which bringsthe FAULT output low for the purpose of notifying themicro-controllerofthefaultcondition.
Figure 36. Recommene application circuit (Single Supply) with esaturation etection an active Miller Clamp
+_
+_
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_RG
100 Ω
CBLANK
DDESAT
Q1
Q2
+VCE-
RF
RRPULL-DOWN
+ HVDC
- HVDC
3-PHASEAC
+VCE-
0.1µF 0.1µF
0.1µF
CF
7
+_
-
Fault Reset
Oncefaultisdetected,theoutputwillbesoft-shutdownto low. All input LED signals will be ignored during thefault period to allow the driver to completely soft shut-down the IGBT. For ACPL-333J, the driver will automati-callyresettheFAULTpinafterafixedmutetimeof25ms(typical).SeeFigure37.
Figure 37. Fault Timing iagram (ACPL-333J)
IF
V DESAT
V OUT
FAULT
6.5V
tDESAT(LOW)
10%
tDESAT(10%)
90%
tDESAT(90%)
50%tDESAT(FAULT)
tDESAT(MUTE)
Automatic Reset aftermute time
50%
tBLANK
21
Output Control
Theoutputs(VOUTandFAULT)oftheACPL-333Jarecon-trolled by the combination of IF, UVLO and a detectedIGBTDesatcondition.OnceUVLOisnotactive(VCC2-VE>VUVLO),VOUTisallowedtogohigh,andtheDESAT(pin14)detectionfeatureoftheACPL-333Jwillbetheprimarysource of IGBT protection. UVLO is needed to ensureDESAT is functional. Once VUVLO+ > 10.5 V, DESAT willremain functional untilVUVLO- < 11.1V.Thus, the DESATdetection and UVLO features of the ACPL-333J work inconjunctiontoensureconstantIGBTprotection.
Desaturation Detection and High Current Protection
TheACPL-333Jsatisfiesthesecriteriabycombiningahighspeed, high output current driver, high voltage opticalisolation between the input and output, local IGBT de-saturation detection and shut down, and an opticallyisolated fault status feedback signal into a single 16-pinsurfacemountpackage.
The fault detection method, which is adopted in theACPL-333J, is to monitor the saturation (collector)voltageoftheIGBTandtotriggeralocalfaultshutdownsequence if the collector voltage exceeds a predeter-mined threshold. A small gate discharge device slowlyreduces the high short circuit IGBT current to preventdamaging voltage spikes. Before the dissipated energycan reach destructive levels, the IGBT is shut off. DuringtheoffstateoftheIGBT,thefaultdetectcircuitryissimplydisabledtopreventfalse‘fault’signals.
The alternative protection scheme of measuring IGBTcurrent to prevent desaturation is effective if the shortcircuit capability of the power device is known, butthis method will fail if the gate drive voltage decreasesenough to only partially turn on the IGBT. By directlymeasuringthecollectorvoltage,theACPL-333JlimitsthepowerdissipationintheIGBTevenwithinsufficientgatedrivevoltage.Anothermoresubtleadvantageofthede-saturationdetectionmethodisthatpowerdissipationinthe IGBT is monitored, while the current sense methodrelies on a preset current threshold to predict the safelimitofoperation.Therefore,anoverlyconservativeovercurrentthresholdisnotneededtoprotecttheIGBT.
IF UVLO (VCC2 – VE) Desat Conition Detecte on Pin 4 Pin 3 (FAULT) Output VOUT
X Active X X Low
X X Yes Low Low
OFF X X X Low
ON NotActive No High High
Slow IGBT Gate Discharge during Fault Condition
Whenadesaturationfaultisdetected,aweakpull-downdevice in the ACPL-333J output drive stage will turn onto‘softly’turnofftheIGBT.Thisdeviceslowlydischargesthe IGBT gate to prevent fast changes in drain currentthat could cause damaging voltage spikes due to leadandwire inductance.Duringtheslowturnoff, the largeoutput pull-down device remains off until the outputvoltagefallsbelowVEE+2Volts,atwhichtimethelargepulldowndeviceclampstheIGBTgatetoVEE.
DESAT Fault Detection Blanking Time
TheDESATfaultdetectioncircuitrymustremaindisabledforashorttimeperiodfollowingtheturn-onoftheIGBTto allow the collector voltage to fall below the DESATthreshold. This time period, called the DESAT blankingtime is controlled by the internal DESAT charge current,the DESAT voltage threshold, and the external DESATcapacitor.
The nominal blanking time is calculated in terms ofexternal capacitance (CBLANK), FAULT threshold voltage(VDESAT), and DESAT charge current (ICHG) as tBLANK =CBLANK xVDESAT / ICHG.The nominal blanking time withtherecommended100pFcapacitoris100pF*6.5V/240µA=2.7µsec.
Thecapacitancevaluecanbescaledslightlytoadjusttheblankingtime,thoughavaluesmallerthan100pFisnotrecommended. This nominal blanking time representsthelongesttimeitwilltakefortheACPL-333JtorespondtoaDESATfaultcondition.IftheIGBTisturnedonwhilethe collector and emitter are shorted to the supply rails(switching into a short), the soft shut-down sequencewillbeginafterapproximately3µsec.IftheIGBTcollectorandemitterareshortedtothesupplyrailsaftertheIGBTisalreadyon,theresponsetimewillbemuchquickerdueto theparasiticparallelcapacitanceof theDESATdiode.The recommended 100pF capacitor should provideadequate blanking as well as fault response times formostapplications.
22
Under Voltage Lockout
The ACPL-333J UnderVoltage Lockout (UVLO) feature isdesigned to prevent the application of insufficient gatevoltage to the IGBT by forcing the ACPL-333J outputlow during power-up. IGBTs typically require gatevoltages of 15 V to achieve their rated VCE(ON) voltage.Atgatevoltagesbelow13Vtypically,theVCE(ON)voltageincreases dramatically, especially at higher currents. Atverylowgatevoltages(below10V),theIGBTmayoperatein the linear region and quickly overheat. The UVLOfunctioncausestheoutputtobeclampedwhenever in-sufficient operating supply (VCC2) is applied. Once VCC2exceedsVUVLO+(thepositive-goingUVLOthreshold),theUVLOclampisreleasedtoallowthedeviceoutputtoturnoninresponsetoinputsignals.AsVCC2isincreasedfrom0V(atsomelevelbelowVUVLO+),firsttheDESATprotec-tioncircuitrybecomesactive.AsVCC2isfurtherincreased(above VUVLO+), the UVLO clamp is released. Before thetime the UVLO clamp is released, the DESAT protectionis already active. Therefore, the UVLO and DESAT Faultdetectionfeatureworktogethertoprovideseamlesspro-tectionregardlessofsupplyvoltage(VCC2).
Active Miller Clamp
A Miller clamp allows the control of the Miller currentduringahighdV/dtsituationandcaneliminate theuseofanegativesupplyvoltageinmostoftheapplications.During turn-off, the gate voltage is monitored and theclampoutputisactivatedwhengatevoltagegoesbelow2V (relative to VEE). The clamp voltage is VOL+2.5V typforaMillercurrentupto1100mA.TheclampisdisabledwhentheLEDinputistriggeredagain.
Other Recommended Components
The application circuit in Figure 36 includes an outputpull-down resistor, a DESAT pin protection resistor, aFAULTpincapacitor,andaFAULTpinpullupresistorandActiveMillerClampconnection.
Output Pull-Down Resistor
During the output high transition, the output voltagerapidlyrisestowithin3diodedropsofVCC2.Iftheoutputcurrent then drops to zero due to a capacitive load, theoutput voltage will slowly rise from roughlyVCC2-3(VBE)toVCC2withinaperiodofseveralmicroseconds.To limitthe output voltage to VCC2-3(VBE), a pull-down resistor,RPULL-DOWNbetweentheoutputandVEEisrecommendedtosinkastaticcurrentofseveral650µAwhiletheoutputis high. Pull-down resistor values are dependent on theamountofpositivesupplyandcanbeadjustedaccordingtotheformula,Rpull-down=[VCC2-3*(VBE)]/650µA.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
RG
RPULL-DOWN
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
RG
RPULL-DOWN
VCC
DESAT Pin Protection Resistor
The freewheeling of flyback diodes connected acrossthe IGBTs can have large instantaneous forward voltagetransients which greatly exceed the nominal forwardvoltageof thediode.Thismayresult ina largenegativevoltagespikeontheDESATpinwhichwilldrawsubstan-tialcurrentoutofthedriver ifprotection isnotused.TolimitthiscurrenttolevelsthatwillnotdamagethedriverIC, a 100 ohm resistor should be inserted in series withtheDESATdiode.TheaddedresistancewillnotaltertheDESATthresholdortheDESATblankingtime.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
RG
VCC
100 Ω
100pFDDESAT
Figure 39. DESAT pin protection.
Figure 38. Output pull-own resistor.
2
Figure 4. Large IGBT rive with negative gate rive, external booster. VCLAMP control seconary ischarge path for higher power application.
Figure 40. IGBT rive with negative gate rive, external booster an esaturation etection (VCLAMP shoul be connecte to VEE when it is not use) VCLAMP is use as seconary gate ischarge path. * inicates component require for negative gate rive topology
Pull-up Resistor on FAULT Pin
TheFAULTpinisanopencollectoroutputandthereforerequires a pull-up resistor to provide a high-level signal.Also the FAULT output can be wire‘OR’ed together withother types of protection (e.g. over-temperature, over-voltage,over-current)toalertthemicrocontroller.
Other Possible Application Circuit (Output Stage)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_
+_
RG
Q1
Q2
+VCE
-
RPULL-DOWN
+ HVDC
- HVDC
3-PHASEAC
+VCE
-
0.1µF 0.1µF
0.1µF
Optional R1
Optional R2
RGOptional R1
Optional R2
*
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+_
+_
RG
Q1
Q2
+VCE
-
RPULL-DOWN
+ HVDC
- HVDC
3-PHASEAC
+VCE
-
0.1µF 0.1µF
0.1µF
Optional R1
Optional R2
R3
9
RGOptional R1
Optional R2
R3
*
Capacitor on FAULT Pin for High CMR
Rapid common mode transients can affect the fault pinvoltagewhilethefaultoutputis inthehighstate.A330pFcapacitorshouldbeconnectedbetweenthefaultpinandgroundtoachieveadequateCMOSnoisemarginsatthe specified CMR value of 15 kV/µs.The added capaci-tance does not increase the fault output delay when adesaturationconditionisdetected.