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Complex rectilinear Floor Plan and Implementation

for Multi-voltage domain, Low Power ASICs

Zameer Ahmed([email protected])

Shankar .N.G

Seshagiri .T. N

Ramakrishna Alluri

Venkateswara Rao Arumilli

Govindrajan Natarajan

Neel Das

ABSTRACT

Mobile and other power-sensitive applications require specialized techniques to meet dynamic

and static power consumption targets, and do this while ensuring performance targets are not

violated.

In this paper, the Tallika team presents key learnings and recommendations that can be used by

engineers to implement such power-sensitive designs, with the added challenges posed byrectilinear floorplan.

Our flow uses Primepower-PX, Jupiter, and then a DC/DFTC/PwC/PC/Astro implementation

flow with RTL clock gating. We use PT-SI, StarRCXT and Hercules for timing, extraction and

physical verification.

We shall present scripts and techniques used to define the complex power plan, and how we

defined voltage regions and voltage islands for level shifters. A two-stage filler cell insertion

technique is described. We shall share some of the key challenges faced, and how they were

overcome with a mix of tool capabilities and floorplan design techniques. For some key

components in the multi-domain design flow, we designed timing models for custom levelshifters as well: we shall share some examples of how this was done.

We will also describe some of the special tweaks and changes in our standard, single-core-

voltage Hercules flow. LVS in particular needs to be thought through from the beginning on

such SOCs, and we shall share some of our learnings on that front.

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SNUG Boston 2007 Complex rectilinear Floor Plan and

Implementation for Multi-voltage domain, Low Power ASICs

2D

Table of Contents

1.0 Introduction..................................................................................................................... 3

2.0 Tallika Low power implementation Flow....................................................................... 42.1.1 Low power Architecture and RTL development.....................................................................................5

2.1.2 Logic Synthesis.......................................................................................................................................52.1.3 Design for Test (DFT).............................................................................................................................82.1.4 Rectilinear Floor plan and Power plan....................................................................................................8

3.0 Conclusions and Recommendations ............................................................................. 13

4.0 References..................................................................................................................... 13

Table of Figures

Figure 1Tallika Low power Implementation flow...4

Figure 2block A in Astro, With rectilinear floor

plan..9

Figure 3 Full chip, With rectilinear floor plan......9

Figure 4block B rectilinear 3.3V, Astro Place and Routed Block.10

Figure 5 level Shifter 3.3V to

1.2V.11

Figure 6 block C 3.3V J Shape block .12

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1.0IntroductionTallika offers concept-to-production Professional Services serving OEMs in networking,

consumer, storage and computing markets as well as digital and mixed-signal semiconductorCompanies. This chip has a complex, rectilinear floor plan with Multi-voltage domains and

Multi-voltage islands with more than 18 clocks and ultra Low power chip and it is targeted on

the TSMC 130nm.

This chip is targeted for mobile applications which requires an innovative ultra low power

techniques for power savings without degradation the performance of the chip.

This paper presents various techniques which Tallika incorporates to meet the ultra low power

requirements and performance for Mobile and security applications.

Tallika uses an integrated design methodology which uses Primepower-PX, Jupiter followedby DC/DFTC/PwC/PC/Astro implementation flow with RTL clock gating. For timing,

extraction and physical verification, Tallika uses PT-SI, StarRCXT and Hercules tools.

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2.0Tallika Low power implementation Flow

Low Power RTL

Logic synthesis

DC-Ultra

Design for Test

DFT-Compiler

Formal Verification

Formality

PreLayout STA

PrimeTime, Power estimation(PrimePower-

PX

Rectilinear FloorPlan and Prototyping

JupitorXT-Astro

Multi-Voltage Power Plan

Astro

Placement(PC) , CTS and Route

Astro

Post Layout STA

Timing Sign-off Prime Time

Formal Verification Rtl to Netlist

Formality

RC Extraction

StarRC-XT

Physical Verification

Hercules

GDS11

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Figure 1Tallika Low power Implementation flow

2.1.1 Low power Architecture and RTL developmentWe know that the biometric chip is targeted for low power applications, we decided howreally our floorplan should be look like and we decided that which Power domains and

signal isolation can be defined in the RTL code as power management tasks. We used Level

shifters at appropriate places for the signal traversing from one domain to the other domain.

This gives clear and sufficient information to functionally simulate the design. Also, we

functionally simulate the different operating mode for the given design. We used the

Modelsim tool for the simulation of the RTL for the functional analysis.

2.1.2 Logic SynthesisWe synthesized the design with Synopsys Design Compiler Ultra, We used power aware

optimizations techniques to achieve the concurrently. We utilized the clock gating

capabilities for different power domains and optimize the clock-gating cells accordingly. We

are experiencing the Topographical Technology to estimate the power consumption of a

multi-voltage design.

A reference block A synthesis script is attached below. This covers clock gating constructs.

The block A is operating at 1.2V low voltage libraries.

current_design $TOP_DESIGN;

linkredirect $outdir1/check_design.rpt {check_design};

#######################set all dont touches#######################set_dont_touch clock genereatorset_dont_touch spare_gates#returnset_dont_touch /microctroller

#return####################################source block A sdc constraints#

###################################redirect $outdir2/block_A_sdc.log {source -e -v ${DIR_BLOCKA}/constraints/block_A_top.sdc}

current_design $TOP_DESIGN;uniquifyset_fix_multiple_port_nets -feedthroughs -outputs -buffer_constants [get_designs *];set_max_area 0

#set ultra optimization turned on

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#set constraints for sub block #################################

set SO_CLK_PERIOD 33

set SO_DECODE_MAX [expr ${SO_CLK_PERIOD} / 2 - 3.0];

set_max_delay 10.0 -from [all_inputs] -to [all_outputs];

set_load 0.139 [get_ports so_o_33s];

set_max_area 0

set_ultra_optimization true

remove_attribute ${LIB_NAME}/vddcon dont_useremove_attribute ${LIB_NAME}/vsscon dont_use

compile -scan -map_effort medium

set_dont_touch $blk

report_area -hredirect $outdir1/final_tim_${blk}.rpt {report_timing -nworst 2 -max 1000 -nosplit -input -net};

}

A reference customized Multi-voltage level shifter .lib is given below

/* Multivoltage cell */

cell("ls_33_12") {is_level_shifter : true;

/* Define all rail voltages used in cell */

rail_connection(VDD_12_OUT, VDD_1.2V); /*

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}cell_fall(ls_33_12_tin_load_1x1) {values ("0.801");

}fall_transition(ls_33_12_trans_tin_load_1x1) {

values("0.0252");

2.1.3 Design for Test (DFT)Our DFT flow reported 98.9% coverage for the synthesized parts of the chip. The standard

Tallika DFT flow is used to stitch the scan chains during synthesis and simultaneously re-

order them during physical implementation(Physical Compiler flow). An alternative flow is

used in some of the blocks to do scan reordering in Astro, in cases where some amount of

manually guided placement was done for specific design requirements. In such blocks, all

the scan synthesis is performed by using DFT Compiler. After completing scan synthesis,

physically-aware scan chain reordering is performed in Astro during placement

optimization.

2.1.4 Rectilinear Floor plan and Power planThe design goal is simple: achieve the lowest possible power and area that should support

the specified performance and functionality of given chip. Using the rectilinear Floor plan

implementation and Multi-voltage domain, the power reduction at block level and top level

are critical. Multi-voltage domain and level shifter instantiation was very critical.

The Chip operating from a single uniform power supply, the Multi-voltage device uses a

range of 1.2v and 3.3v supply voltages assigned to different blocks . Each block of a chipcan be assigned reassigned to different voltage level shifters 1.2V to 3.3V and 3.3V to

1.2Vfor different functions.

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Figure 2block A in Astro, With rectilinear floor plan.

CORE 1.2V

AnalogPLL

WOE

3.3V

so_control 3.3V

so_control 3.3V

Figure 3 Full chip, With rectilinear floor plan

With multi-voltage design approach we are able to save power, different blocks operating at

different clock speeds. The synthesis is done using Synopsys Design Compiler Ultra, which

allows the power supply voltage to be reduced to match the needs of the lower performance

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tasks. We used Power Compiler- to implement RTL clock gating to reduce the dynamic

power consumption of the synthesized blocks.

This chips Multi-voltage design is partitioned into distinct power domains, some of the

blocks are completely shut down and some of the blocks are running at fixed operating

voltage. The mode of operation depend on the control logic block of chip and special librarycells.

Figure 4block B rectilinear 3.3V, Astro Place and Routed Block

This Chip has isolated Voltage Island and enabled level shifters that are used to set a non-

floating output signal on the output side of power domain interface when part of the logic is

shutdown.

The Chip has Buffer-type Level shifter cells (1.2v to 3.3V) that are used to transmit the

signals across logic at the voltage interface. This design has multiple operating conditions

defined in its logic hierarchy, which we have taken care in the timing to calculate the timing

paths that across different operating conditions.

The Chip floor plan is the first stage Physical design implementation, where power domains

voltage area (1.2v, Level Shifters and 3.3v). We did multiple iterations to get the rightvoltage domain area. We used Jupiter-XT to create eleven different options before

narrowing down to the final rectilinear floor plan.

ThePrime Time SItiming engine recognizes the multi-voltage signal integrity aware and it

is detected signals that connect the driver and load across (1.2v to 3.3V) power domains.

The signal-level consistency has to be maintained on the entire design. Slew scaling is

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applied when a signal transits across multi-voltage (1.2v to 3.3v vice versa).We usedPrime

Time SIto do this.

Power straps and rings for different power domain care fully created, performed the power

budget and electron migration constraints, power hookup is done for different power

domains(1.2v, LS, 3.3V), We had LS cells that connect a lower voltage domain to highervoltage domain have two power supply pins. These pins must be connected to power nets.

We placed in the dedicated LS blocks.

We designed several rectilinear level shifter blocks. This helped save a lot of die area. The

height of the level shifter Cell is more than Standard Cell height. The placement of level

shifter Cells in the level shifter block is done with a perl script. Designing the two different

voltage straps (1.2V VDD, 3.3V VDD and VSS) and connecting the correct power strap to

the appropriate level shifter has to be done with care stage. Routing the different signals to

the level shifter blocks was also another crucial requirement.

Figure 5 level Shifter 3.3V to 1.2V

In summary, the design and placement of rectilinear level shifter block saves lot of die area.

We had 18 different (slow and fast)clocks. The Astro Clock tree synthesis recognizes

voltage areas and creates the clock tree bottom-up, by clustering sink points from the same

voltage areas. We care fully performed the clock tree building for the different clock tree in

the design. Once clock sub trees are built for each voltage area, The CTS joins the sub-treesat the root of the clock tree. We usedAstro-Express for the manual auto CTS option.

One key 3.3V block has a J shape. An innovative methodology was used to meet very

tight skew requirements for the block. First we performed the Astro CTS to meet the given

skew requirement. However, Astro was not able to meet the required skew. We designed

manual CTS structures utilizing basic repeated plan group blocks and allowed Astro to do

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CTS from that point to leaf level. With this we were able to meet the skew for the J shape

block.

Figure 6 block C 3.3V J Shape block

The routing of the design with different voltage islands was one of key requirement of the

chip. The isolation of two different voltage islands was another key requirement while

routing. The routing for one voltage islands and power hookup manually to specific power

pins in the physical domain was very essential. We used Astro to route according this

requirement.

2.1.5 Physical Verification

We sign-off for the full Chip performing the Physical Verification using the Hercules,design rule checking of the layout polygons (DRC), layout versus schematic (LVS) using

theHercules.

The hierarchical Physical verification is one of the key requirement for the given chip. The

analog block needs to be verified by Hercules. Basically Hercules will not accept the

detailed hierarchical cdl netlist and special Varactor devices. We manually worked on the

detailed hierarchical cdl netlist and Varactor Device mapping to converge withHercules, So

that we can use the modified cdl netlist to perform the Physical verification with Hercules

itself. With theHercules antenna report files, finding out an Antenna violation in the layout

was very painful. Hercules will report an Antenna violation closest proximity to the given

cell, Instead the exact gate. We used3rd party toolreports to fix the antenna violations inthe layout for two specific cases where Hercules was unable to pinpoint coordinates/metal

layers that violated antenna requirements..

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3.0Conclusions and RecommendationsThe complex rectilinear floorplan design and development was the key challenge in terms of

SOC implementation. The major time spent on the development of the rectilinear floor plan,power plan and placement of the Hard macro for the meeting the timing and power

requirement. One more critical area for the voltage islands level shifter placement. The level

shifter blocks are also rectilinear in the shape. The placement of the different voltage

domain blocks was another challenge. The J shaped block, with its tight skew

requirement, was a very big challenge for the given chip. The entire Synopsys flow for

implementing the complex rectilinear floorplan for multi-voltage domain was very helpful.

We found that Astro was not geared to handle tight skew requirements in the J block, and

we achieved significantly better skew and timing results with a lot of manual intervention.

We are in the process of evaluating ICC for this block.

4.0References Solvnet from Synopsys Design Planning Strategies for Floor planning and Power Planning Synopsys white

paper

Implementing an End-to-End Low-Power Mutil-Voltage Methodology SynopsysWhite paper.

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