Da0tw7mb8g0_rev g ___tw7 - Rev 3a

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PCB STACK UPLAYER 1 : TOP LAYER 2 : SGND1A

TW7- DESIGN31TW7MB00XXMerom 35W(478 Micro-FCPGA) PG 37 PG 3,4 RUN POWER SW PG 43 AC/BATT CONNECTOR BATT CHARGER PG 40

1DC/DC 3VSUS 5VSUS PG43 DC/DC 3VPCU 5VPCU PG38 DC/DC +1.05V +1.5V PG37

CLOCKSICS9LPRS365BGLFTA

LAYER 3 : IN1 LAYER 4 : IN2 LAYER 5 : VCC LAYER 6 : IN3 LAYER 7 : SGND2 LAYER 8 : BOT FSB 667/800

PG 2

CPU VR

PG 40

PCI-Express X16

nVIDIANB8M-GS 533 BGA 23X23 10~13W DDRII 16M*16(128MB) 32M*16(256MB) (Bank*4) 64 Bit Bandwidth PG 18~22

DC/DC VGA CORE 1.15V PG42

DDRII VRB

DDRII-SODIMM1PG 16,17

DDRII 533/667

Crestline (G)MCH 965GM/PMDDRII 533/667

LVDS(2 Channel) TVOUT VGA USB2.0 (P5)

Panel ConnectorPG 23

S-VideoPG 24

PG 39

DDRII-SODIMM2PG 16,17

B

1299 FCBGA 35X35 PG 5,6,7,8,9,10,11 DMI X4 USB2.0 (P0~P7)

VGA,DVIPG 24

BluetoothPG 35

SATA - HDD PG 31

SATA0

USB2.0 (P0~P1,P4)

ICH8-M652 BGA 31X31 PATA 100

USB2.0 I/O Ports PG 26 Camera LANPG 23Function Board

USB2.0 (P3)

Internal ODD CD-ROMPG 31C

PCI-E, 1X

Marvell 8055,8038 PG 26

Magnetics

PG 27

RJ45

PG 27

Conn

Azalia PG 12,13,14,15 MDC DAA PG 34 Realtek ALC268 PG 32

PCI-E, 1X PCI-E, 1X

Mini PCI-E Card *2PCI Express Mini Card

PG 28Power On Power Input

C

PG 35 Express Card x1 NEW CARD

RQ6Replicator Daughter Board

PCI Bus 33MHz LPC

LPT PORT

PG 35

COM PORT LAN VGA Headphone 1394

USB

Audio Amplifier TPA0312 PG 33 Daughter Board RJ11+USB PG 33

HP Amplifier MAX4411 PG 33

KBCENE KB3926 A01 PG 38 X-Bus

TI PC7402PG 29,30

USB X 2

SVID 152D SPI ROM PG 38 IEEE1394 CONN PG 29 Card reader PG 30Size Date: Document Number

PG 37D

D

Internal Speaker

Audio Jacks PG 30Green

Line in PG 33Blue

Mic Jacks PG 32Pink

TPM1.2 PG 40

Key Matrix PG 36

Touch Pad PG 36

SSID 0763

PROJECT : TW7 Quanta Computer Inc.Rev

Block DiagramFriday, April 13, 2007 Sheet8

3A1 of 54

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+3V

120 ohms@100MhzL44 1 1 2 C534 C816 0.1U/10V_4 2 4.7U/6.3V_6 +CK_VDD_MAIN 1 1 1 1 C814 4.7U/6.3V_6 2 1 BLM18PG121SN1D

02C527 0.1U/10V_4 2 C815 0.1U/10V_4 2 C827 0.1U/10V_4 2 C552 0.1U/10V_4 2

C850 0.1U/10V_4

5 * 3.2Y5 CLK_XTAL_IN 1 1 2 14.318MHZ C812 BG614318F33 22P/50V_4 2 2 1 CLK_XTAL_OUT

A

L46 1 2 VDDCPU BLM18PG121SN1D 1 C541 C808 0.1U/10V_4 2 4.7U/6.3V_6 C542 4.7U/6.3V_6 2 1 C537 0.1U/10V_4

+3VCLK_3GPLLREQ# NEW-CARD_CLK_REQ# R602 R610 2 2 1 10K_4 1 10K_4

A

14.318MHzC813 22P/50V_4

30PPM,CL=20PF

120 ohms@100MhzL45 1 1 2 1 1 C547 C806 0.1U/10V_4 2 4.7U/6.3V_6 C550 4.7U/6.3V_6 2 +CK_VDD_MAIN2 1 1 1 1 +CK_VDD_MAIN R570 C847 0.1U/10V_4 VDDCPU +CK_VDD_MAIN2 R568 16 0_4 9 2 0_4 61 39 55 12 20 26 45 36 49 48 RP60 4P2R-S-2.2K Q28 2N7002E [14,36] PDAT_SMB R266 *4.7K_4 [14] CK_PWG CK_PWG CPU_MCH_BSEL1 R571 C821 4.7P/50V_4 1 CGCLK_SMB [16,35] CGCLK_SMB [16,35] CGDAT_SMB CGCLK_SMB CGDAT_SMB 64 63 15 19 11 52 8 58 23 29 42 SCLK SDATA GND GND GND48 GNDCPU GNDPCI GNDREF GNDSRC GNDSRC GNDSRC 4.7K_4 FSB 56 57 3 2 1 3 CLK_XTAL_IN CLK_XTAL_OUT 60 59 BLM18PG121SN1D U35 VDDPLL3 VDD48 VDDPCI VDDREF VDDSRC VDDCPU VDD96I/O VDDPLL3I/O VDDSRCI/O VDDSRCI/O VDDSRCI/O VDDCPU_IO NC X1 X2 CPUCLKT0 CPUCLKC0 CPUCLKT1 CPUCLKC1 CPUT2_ITP/SRCT8 CPUT2_ITP/SRCC8 DOTT_96/SRCT0 DOTC_96/SRCC0 27MHz_Nonss/SRCCLK1/SE1 27Mhz_ss/SRCCLC1/SE2 SRCCLKT2/SATACL SRCCLKC2/SATACL SRCCLKT3/CR#_C SRCCLKC3/CR#_D SRCCLKT4 SRCCLKC4 CK_PWRGD/PD# FSLB/TEST_MODE PCI_STOP# CPU_STOP# SRCCLKT6 SRCCLKC6 SRCCLKT7/CR#_F SRCCLKC7/CR#_E SRCCLKT9 SRCCLKC9 SRCCLKT10 SRCCLKC10 SRCCLKT11/CR#_H SRCCLKC11/CR#_G PCICLK0/CR#_A PCICLK1/CR#_B PCICLK2/TME PCICLK3 PCICLK4/27_SELECT 54 53 51 50 47 46 13 14 17 18 21 22 24 25 27 28 38 37 41 40 44 43 30 31 34 35 33 32 1 3 4 5 6 CLK_PCIE_ICH [13] CLK_PCIE_ICH# [13] CLK_PCIE_MINI1 [35] CLK_PCIE_MINI1# [35] CLK_MCH_3GPLL [6] CLK_MCH_3GPLL# [6] CLK_PCIE_EXPCARD [36] CLK_PCIE_EXPCARD# [36] NEW-CARD_CLK_REQ#_R R605 CLK_3GPLLREQ#_R R601 R_PCLK_KB3926 PCI_PCCARD PCI_MINIPCI PCICLK3 FCTSEL1 R563 R566 R567 R285 R301 R282 R277 FSA FSC R278 0_4 R273 R279 R271 475/F 475/F NEW-CARD_CLK_REQ# CLK_3GPLLREQ# 33 33 33 33 33 22_4 22_4 4.7K_4 4.7K_4 33 FSLA_BSEL0 CPU_MCH_BSEL2 CLK_ICH_14M [14] NEW-CARD_CLK_REQ# [36] CLK_3GPLLREQ# [6] CLK_PCI_KB3926 [39] CLK_PCI_PCCARD [29] PCLK_TPM [41] PCLK_LPC_DEBUG [35] CLK_PCI_ICH [13] CLK_7402_48M [30] CLK_ICH_48M [14] PCIE_VGA PCIE_VGA# DOT96 DOT96# DOT96_SSC DOT96_SSC# CPU_BCLK CPU_BCLK# MCH_BCLK MCH_BCLK# RP61 4 2 RP63 4 2 3 4P2R-S-0 1 3 4P2R-S-0 1 CLK_CPU_BCLK [3] CLK_CPU_BCLK# [3] CLK_MCH_BCLK [5] CLK_MCH_BCLK# [5]

C824 0.1U/10V_4 2

C856 0.1U/10V_4 2

C830 0.1U/10V_4 2

C834 0.1U/10V_4 2

C835 0.1U/10V_4 2

CK505

CLK_PCIE_MINI2 [35] CLK_PCIE_MINI2# [35] RP62 RP64 2 4 2 4 1 4P2R-S-0 3 1 4P2R-S-0 3 MCH_DREFCLK [6] MCH_DREFCLK# [6] DREF_SSCLK [6] DREF_SSCLK# [6]

+3V +3V2 2 4

B

B

R265 10K_4 1 PCI_MINIPCI

CLK_PCIE_SATA [12] CLK_PCIE_SATA# [12] RP68 2 4 1 *4P2R-S-0 3 CLK_PCIE_VGA [18] CLK_PCIE_VGA# [18]

1

CGDAT_SMB

CLK_PCIE_LAN [26] CLK_PCIE_LAN# [26] PM_STPPCI# [14] PM_STPCPU# [14]

+3VQ27 2N7002E [14,36] PCLK_SMB 3 2 CLK_7402_48M CLK_ICH_48M PCLK_TPM CLK_PCI_KB3926 CLK_PCI_PCCARD CLK_PCI_ICH PCLK_LPC_DEBUG CLK_ICH_14M

0=overclocking of CPU and SRC AllowedC522 10P/50V_4 10P/50V_4 10P/50V_4 10P/50V_4 10P/50V_4 10P/50V_4 10P/50V_4 10P/50V_4

1 = overclocking of CPU and SRC not AllowedC

C518 C818 C810 C817 C533 C526

C

FCTSEL1 2 C513 R289 10K_4 1

PCI_F5/ITP_EN

7 10 62

ITP_EN

for EMI

RTM875T-606-LFT(AL000875K06)ICS9LPRS365BGLFT

USB_48MHZ/FSLA FSLC/TST_SL/REF

CRB-->2.2K BSEL0,BSEL2 FSB 0 0 1 1 0 0 1 1 FSA 1 1 1 0 0 0 0 1 CPU 100 133 166 200 266 333 400 RSVD SRC 100 100 100 100 100 100 100 100 PCI 33 33 33 33 33 33 33 33

CPU Clock select0=UMA 1 = External VGA[3] CPU_MCH_BSEL0

L89 BLM18AG601SN1D FSLA_BSEL0 1 2 CPU_MCH_BSEL0 R267 R270 *10K_4 1K/F R287 R290 *0_4 1K/F R272 R269 *0_4 1K/F 0_4 MCH_BSEL2 [6] 0_4 MCH_BSEL1 [6] R268 0_4 MCH_BSEL0 [6]

B2A-->Add L89,R278

FSC 1 0 0 0 0 1 1 1

GCLK_SEL = FCTSEL1FCTSEL1 (PIN13) PIN20 PIN21 PIN24 PIN25

+1.05V

0=UMA 1 = External VGA

DOT96T DOT96C SRCT0 SRCC0

SRCT1/LCDT_100 SRCT1/LCDT_100 27Mout-NSS 27Mout-SSD

[3] CPU_MCH_BSEL1 ITP_EN 1D

R300 10K_4

+1.05V[3] CPU_MCH_BSEL2

R284

Disable ITP

+1.05V

R275

1K to NB only when XDP is implement.No XDP can use 0 ohm

2

PROJECT : TW7 Quanta Computer Inc.Size Date: Document Number Rev

CLOCK GENERATORFriday, April 13, 20077

2ASheet 28

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54

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[5] H_A#[3..16]

H_A#[3..16] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#[0..4] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#[17..35] H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6

U19A A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# A20M# FERR# IGNNE# ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 H_IERR# H_INIT# H_LOCK# H_RS#0 H_RS#1 H_RS#2 H_TRDY# H_HIT# H_HITM# ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# SYS_RST# H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_BR0# R28 H_ADS# [5] H_BNR# [5] H_BPRI# [5] H_DEFER# [5] H_DRDY# [5] H_DBSY# [5] H_BR0# [5] 56.2_4

Merom CPU Socket PN: FOX: DGT^000021 TYC: DGT^000012 MLX: DGT^000004 MLX: DGT^000000

[5] H_D#[0..63]

H_D#[0..63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24

U19B D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 BSEL[0] BSEL[1] BSEL[2] D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[1] COMP[2] COMP[3] Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#[0..63]

H_D#[0..63] [5]

03A

CONTROL

IERR# INIT# LOCK# RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#

+1.05VH_INIT# [12] H_LOCK# [5] H_RST# H_RS#0 [5] H_RS#1 [5] H_RS#2 [5] H_TRDY# [5] H_HIT# [5] H_HITM# [5]

Near to CPUAdd for ESDR2 2 0_4 H_RESET# [5] [5] H_DSTBN#0 [5] H_DSTBP#0 [5] H_DINV#0 [5] H_D#[0..63] H_D#[0..63]

[5] H_ADSTB#0 [5] H_REQ#[0..4]

DATA GRP 2

A

[5] H_A#[17..35]

1

XDP/ITP SIGNALS

DATA GRP 3

1 C651 0.1U/10V_4

SYS_RST# [14] RV3 1 2

+1.05V2

+1.5V

B

THERMALPROCHOT# THERMDA THERMDC THERMTRIP# D21 A24 B25 C7 CPU_PROCHOT# H_THERMDA H_THERMDC PM_THRMTRIP#

R32 1K/F

2

[5] H_ADSTB#1 [12] H_A20M# [12] H_FERR# [12] H_IGNNE# [12] [12] [12] [12] H_STPCLK# H_INTR H_NMI H_SMI#

H_THERMDA [4] H_THERMDC [4] PM_THRMTRIP# [6,12]

1

2

STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10]

1

BCLK[0] BCLK[1]

A22 A21

CLK_CPU_BCLK CLK_CPU_BCLK#

CLK_CPU_BCLK [2] CLK_CPU_BCLK# [2]

[2] CPU_MCH_BSEL0 [2] CPU_MCH_BSEL1 [2] CPU_MCH_BSEL2 +1.05V

CPU_MCH_BSEL0 CPU_MCH_BSEL1 CPU_MCH_BSEL2

B22 B23 C21

H_CPUSLP# [5] PM_PSI# [42]

RV2 *VZ0603M260APT 2

+1.05VR26 R396 68_4 R394 *330_6 R27 C93 1 1

Merom Ball-out Rev 1a

RESERVED

1

FSB 533 667 800

BCLK 133 166 200

BSEL2 0 0 0

BSEL1 0 1 1+1.05V

BSEL0 1 1

*1K/F 2 *1K/F 2 2

CPU_TEST1 CPU_TEST2

T15 T39

CPU_TEST3 CPU_TEST5

Populate ITP700Flex for bringupC


CPU_PROCHOT#

2

0

*0.1U/10V_4 CPU_TEST4 1 *0_4 2 CPU_TEST6

1

3 Q24 *MMBT3904

VR_TT# [42]

R23 1

For the purpose of testability, route these signals through a ground referenced Z0 = 55ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection.C

+1.05V

Layout Note: Place R4,R361,R346 & R7 close to CPU.

3VPCUR21 *1K/F R19 *10K_4

2

R3 *51/F

R9 *51_4

R7 39/F

R4 150_4

ITP_TDI ITP_TMS ITP_TCK ITP_TDO ITP_TRST# H_RST#

3

R8 1 R1 1

2 *0_4 *22.6/F_6 2

T5 T8 T6 T2 T7 T1

T12 T11 T10 T13 T3 T4

ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5

PM_THRMTRIP#

2

ITP debug signals1

Place C close to the CPU_TEST4 pin. Make sure CPU_TEST4 routing is reference to GND and away from other noisy signal.+5VCPU_PROCHOT# R395 100K_4

COMP0 COMP1 COMP2 COMP3 2 2 2 2

1

1

1

1

3 Q2 *MMBT3904

THERM_CPUDIE_L#

R20

*0_4

THERM_CPUDIE# [39] THERM_CPUDIE_L# [19]

2

2

2

2

R5 54.9/F

R6 27.4/F

1

1

1

1

Q25 2N7002E 2 3 Q3 DTC144EUA 1

Layout Note: Place R8 close ITP.27.4/F 1 ITP_TCK 1 ITP_TRST#

ITP disable guidelinesR11D

[39] FANLESS#

2

Comp0,2 connect with Zo=27.4ohm,Comp1,3 connect with Zo=55ohm, make those traces length shorter than 0.5".Trace should be at least 25 mils away from any other toggling signal.VGA_LESS# [19]

2 2

Signal TDI TMS TRST# TCK TDO

Resistor Value Connect To Resistor Placement 150 ohm +/- 5% 39 ohm +/- 1% VTT VTT Within 2.0" of the ITP1D

R10

500-680ohm +/- 5% GND 27 ohm +/- 1% 150 ohm +/- 5% GND VTT

Within 2.0" of the ITP Within 2.0" of the ITP Within 2.0" of the ITP

For Throttle Function2

3

649/F

Within 2.0" of the ITP

Q4 *2N7002E

PROJECT : TW7 Quanta Computer Inc.Size Date: Document Number Rev 1

Note: Populate R5, R8, C372 & R430 when ITP connector is populated.1 2 3 4 5 6 7

Merom (HOST BUS)Friday, April 13, 2007 Sheet 38

1

ADDR GROUP 0 ICH

DATA GRP 0

RV1 *VZ0603M260APT

H_DSTBN#2 [5] H_DSTBP#2 [5] H_DINV#2 [5] H_D#[0..63] H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_D#[0..63] [5]

Layout Note: Place voltage divider within 0.5" of GTLREF pin

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

Reserved for EMI.+1.05V

ADDR GROUP 1

DATA GRP 1

*VZ0603M260APT

[5] H_DSTBN#1 [5] H_DSTBP#1 [5] H_DINV#1

H_DSTBN#3 [5] H_DSTBP#3 [5] H_DINV#3 [5] COMP0 COMP1 COMP2 COMP3

B

R33 2K/F

H CLK

V_CPU_GTLREF AD26 CPU_TEST1 C23 CPU_TEST2 D25 CPU_TEST3 C24 CPU_TEST4 AF26 CPU_TEST5 AF1 CPU_TEST6 A26

MISC

Note: H_DPRTSTP need to daisy chain from ICH8 to IMVP6 to CPU.H_DPRSTP# [6,12,42] H_DPSLP# [12] H_DPWR# [5]

DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#

H_PWRGD [12]

R31 54.9/F

R30 27.4/F

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VCC_CORE1 1

10U/4V_8 *321 1 1

VCC_CORE U19C A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA[01] VCCA[02] VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE . AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26 AD6 AF5 AE5 AF4 AE3 AF3 AE2

VCC_CORE

ICCODE: for Merom processors recommended design target is 44A

U19D A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] . P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

04A

C20 10U/6.3V_8 2 2

C41 10U/6.3V_8 2

C46 10U/6.3V_8 2

C39 10U/6.3V_8 2 C58 10U/6.3V_8 2 2 1

C16 10U/6.3V_8

A

VCC_CORE1 1 1 1 C43 10U/6.3V_8 2

C21 10U/6.3V_8 2 2

C22 10U/6.3V_8

C47 10U/6.3V_8

8 inside cavity, north side, secondary layer.VCC_CORE1 1 1 1 1

C40 10U/6.3V_8 2 2

C52 10U/6.3V_8 2

C53 10U/6.3V_8 2

C23 10U/6.3V_8 2

C33 10U/6.3V_8

ICCP: 1before vccore stable peak current is 4.5A 2.after vccore stable continue current is 2.5A+1.05V

VCC_CORE1 1 1 1 1

C5 + 330U/2V/ESR9

B

C37 10U/6.3V_8 2 2

C49 10U/6.3V_8 2

C42 10U/6.3V_8 2

C38 10U/6.3V_8 2

C24 10U/6.3V_8

+1.5V

B

8 inside cavity, south side, secondary layer.

ICCA 130mA1 1

Layout Note: Place C105 near PIN B26.

VCC_CORE1 1 1 1 1 1

C655 0.01U/16V_4

C656 10U/6.3V_8

2

C56 10U/6.3V_8 2 2

C28 10U/6.3V_8 2

C17 10U/6.3V_8 2

C51 10U/6.3V_8 2

C34 10U/6.3V_8 2

C27 10U/6.3V_8

6 inside cavity, north side, primary layer.VCC_CORE1 1 1 1 1 1

CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6

[42] [42] [42] [42] [42] [42] [42]

VCC_CORE

2

R22 100/F TP_VCCSENSE [42] TP_VSSSENSE [42]

AF7 TP_VCCSENSE AE7 TP_VSSSENSE

C57 10U/6.3V_8 2 2C

C30 10U/6.3V_8 2

C44 10U/6.3V_8 2

C48 10U/6.3V_8 2

C54 10U/6.3V_8 2

C31 10U/6.3V_8


C

6 inside cavity, south side, primary layer.+3V +1.05V1 1 1 1 1 1

R18 100/F

+3V

5V_AL

C60 0.1U/10V_4 2 2

C18 0.1U/10V_4 2

C59 0.1U/10V_4 2

C19 0.1U/10V_4 2

C6 0.1U/10V_4 2

C7 0.1U/10V_4

R34 *100

R653 100

25milsLayout out: Place these inside socket cavity on North side secondary.+3V2 Q5 2N7002E 3 R52 10K_4 R38 10K_4 LM86_SMC LM86_SMD 1 LM86_SMD LM86_SMD [19,20] R37 10K_4 U1 8 7 6 4 SCLK SDA ALERT# OVERT# GMT-781 VCC DXP DXN GND 1 2 3 5 LM86VCC

G3D


C89 0.1U/10V_4

R47

*0_4

THERM_OVER# [39,43]

+3VH_THERMDA C88 *2200pF/50V H_THERMDC H_THERMDA [3]

[39,45] MBDATAD

E3B

10/10milsH_THERMDC [3] 3

R59 1M_4 2 1

3

D

+3V2 Q6 2N7002E 3

[14] THERM_ALERT#

THERM_ALERT#

Q7 2N7002E

2 Q9 2N7002E 2

1

ADDRESS: 98H1 LM86_SMC LM86_SMC [19,20]

SYS_SHDN-1#

C155 0.1U/10V_4

[39,45] MBCLK

add hardware protect

[19] SYS_SHDN-1#

1

D3A

PROJECT : TW7 Quanta Computer Inc.Size Date: Document Number

SYS_SHDN-1#

Merom Processor (POWER)Friday, April 13, 20077

Rev 3D 48

Sheet

of

54

1

2

3

4

5

6

1

2

3

4

5

6

7

8

05U24A [3] H_D#[0..63]A

H_A#[3..35] H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# [3] H_ADSTB#0 [3] H_ADSTB#1 [3] H_BNR# [3] H_BPRI# [3] H_BR0# [3] H_DEFER# [3] H_DBSY# [3] CLK_MCH_BCLK [2] CLK_MCH_BCLK# [2] H_DPWR# [3] H_DRDY# [3] H_HIT# [3] H_HITM# [3] H_LOCK# [3] H_TRDY# [3]

H_D#[0..63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_SWING H_RCOMP E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 B3 C2 W1 W2 B6 E5 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_SWING H_RCOMP H_SCOMP H_SCOMP# H_CPURST# H_CPUSLP#

H_A#[3..35] [3]

A

+1.05V

1 R57 221/F H_SWING R56 100/F 2 2 C138 0.1U/10V_4 1B

1

2

B

+1.05V

impedance 55 ohm1 1

R411 54.9/F

R410 54.9/F H_SCOMP H_SCOMP#

HOST

Short Stub < 100mils extract from same point

2

H_RCOMP 1 R58 24.9_6 2

2

C

Layout Note: H_RCOMP trace should be 10-mil wide with 20-mil spacing.

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2

K5 L2 AD13 AE13 M7 K3 AD2 AH11 L7 K2 AC2 AJ10 M14 E13 A11 H13 B12 E12 D7 D8

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

[3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3]

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

C

R413 0_4 [3] H_RESET# [3] H_CPUSLP# +1.05V 2 1 RV7 *VZ0603M260APT Near NB

H_SCOMP H_SCOMP# H_CPUSLP#

[3] [3] [3] [3] [3]

H_REF R69 1K/F

Add for ESD

B9 A9

H_RS#0 [3] H_RS#1 [3] H_RS#2 [3]

H_AVREF H_DVREF CRESTLINE_1p0

2

1

1

R73 2K/FD

1 2

C185 0.1U/10V_4D

2

Layout Note: Place the 0.1 uF decoupling capacitor within 100 mils from GMCH pins.1 2 3 4 5 6

PROJECT : TW7 Quanta Computer Inc.Size Date: Document Number

Crestline (HOST)Friday, April 13, 20077

Rev 1A Sheet 58

of

54

1

2

3

4

5

6

7

8

U24B P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20A

MUXING

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14

U24C SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4 SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4 SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF_0 SM_VREF_1 AV29 BB23 BA25 AV23 AW30 BA23 AW25 AW23 BE29 AY32 BD39 BG37 BG20 BK16 BG16 BE13 BH18 BJ15 BJ14 BE16 BL15 BK14 BK31 BL31 AR49 AW4 SMRCOMPP SMRCOMPN SM_RCOMP_VOH SM_RCOMP_VOL SMDDR_VREF_MCH M_A_CLK0 M_A_CLK1 M_B_CLK0 M_B_CLK1 M_A_CLK0# M_A_CLK1# M_B_CLK0# M_B_CLK1# M_A_CKE0 M_A_CKE1 M_B_CKE0 M_B_CKE1 M_A_CS#0 M_A_CS#1 M_B_CS#0 M_B_CS#1 M_A_ODT0 M_A_ODT1 M_B_ODT0 M_B_ODT1 [16] [16] [16] [16] [16] [16] [16] [16] [16,17] [16,17] [16,17] [16,17] [16,17] [16,17] [16,17] [16,17] [16,17] [16,17] [16,17] [16,17] C110 1 C124 C115 R44 2 470P/50V/X7R/04 0.1U/10V_4 0.1U/10V_4 0_4 SMDDR_VREF [16,41,44] [22] NB_TXUOUT0+ [22] NB_TXUOUT1+ [22] NB_TXUOUT2+ MCH_DREFCLK [2] MCH_DREFCLK# [2] DREF_SSCLK [2] DREF_SSCLK# [2] CLK_MCH_3GPLL [2] CLK_MCH_3GPLL# [2] DMI_TXN[3:0] [13] DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 AN47 DMI_TXN0 AJ38 DMI_TXN1 AN42 DMI_TXN2 AN46 DMI_TXN3 AM47 DMI_TXP0 AJ39 DMI_TXP1 AN41 DMI_TXP2 AN45 DMI_TXP3 AJ46 DMI_RXN0 AJ41 DMI_RXN1 AM40DMI_RXN2 AM44DMI_RXN3 AJ47 DMI_RXP0 AJ42 DMI_RXP1 AM39DMI_RXP2 AM43DMI_RXP3 [25] NB_DDCCLK [25] NB_DDCDAT [22] NB_HSYNC_COM E44 A47 A45 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 [22] NB_TXUOUT0[22] NB_TXUOUT1[22] NB_TXUOUT2G44 B47 B45 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 [19,23] LCD_BKLTCTL [19,23] LCD_BLON_AND R139 R140 R136 R484 R480 R478 R148 R144 0_6 0_6 10K_4 10K_4 0_6 0_6 0_6 2.4K L_BKLT_EN J40 H39 E39 E40 C37 D35 K40 L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2

+VCC_PEG R155 24.9_6 N43 VCC3G_PCIE_R 1 2 M43 J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41 J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4

+3V[19,23] EDIDCLK [19,23] EDIDDATA [19,23] ENVDD

PEG_COMPI PEG_COMPO PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

06A

DDR

[16,17] SA_MA14 [16,17] SB_MA14

SA_MA14 SB_MA14

CLK

100 Mhz[22] NB_TV_COMP [22] NB_TV_Y/G [22] NB_TV_C/R

PCI-EXPRESS

CRESTLINE new pin define

T29 T28

PAD PAD

DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK#

B42 C42 H48 H47 K44 K45

96 MhzNB_TV_COMP NB_TV_Y/G NB_TV_C/R E27 G27 K27 F27 J27 L27 TVA_DAC TVB_DAC TVC_DAC

GRAPHICS

WW22 update --- MA14 needs to be routed if customers are planning on using 2Gb technology and width=8 (by 8) DIMMs

[22] [22] [22] [22]

NB_TXLCLKOUTNB_TXLCLKOUT+ NB_TXUCLKOUTNB_TXUCLKOUT+

LVDS_IBG L41 L43 N41 N40 D46 C45 D44 E42 G51 E51 F49 G50 E50 F48

H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BJ29 BE24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34

B

Layout Note: Location of all MCH_CFG strap resistors needs to be close to minmize stub.MCH_BSEL0 MCH_BSEL1 MCH_BSEL2 CFG5 P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35

RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 SA-MA14 SB_MA14 RSVD34 RSVD35 RSVD36 LVDSA_DATA#_3 LVDSA_DATA_3 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

[22] NB_TXLOUT0[22] NB_TXLOUT1[22] NB_TXLOUT2[22] NB_TXLOUT0+ [22] NB_TXLOUT1+ [22] NB_TXLOUT2+

PEG_RXN0 [18] PEG_RXN1 [18] PEG_RXN2 [18] PEG_RXN3 [18] PEG_RXN4 [18] PEG_RXN5 [18] PEG_RXN6 [18] PEG_RXN7 [18] PEG_RXN8 [18] PEG_RXN9 [18] PEG_RXN10 [18] PEG_RXN11 [18] PEG_RXN12 [18] PEG_RXN13 [18] PEG_RXN14 [18] PEG_RXN15 [18] PEG_RXP0 [18] PEG_RXP1 [18] PEG_RXP2 [18] PEG_RXP3 [18] PEG_RXP4 [18] PEG_RXP5 [18] PEG_RXP6 [18] PEG_RXP7 [18] PEG_RXP8 [18] PEG_RXP9 [18] PEG_RXP10 [18] PEG_RXP11 [18] PEG_RXP12 [18] PEG_RXP13 [18] PEG_RXP14 [18] PEG_RXP15 [18] PEG_TXN0 [18] PEG_TXN1 [18] PEG_TXN2 [18] PEG_TXN3 [18] PEG_TXN4 [18] PEG_TXN5 [18] PEG_TXN6 [18] PEG_TXN7 [18] PEG_TXN8 [18] PEG_TXN9 [18] PEG_TXN10 [18] PEG_TXN11 [18] PEG_TXN12 [18] PEG_TXN13 [18] PEG_TXN14 [18] PEG_TXN15 [18] PEG_TXP0 [18] PEG_TXP1 [18] PEG_TXP2 [18] PEG_TXP3 [18] PEG_TXP4 [18] PEG_TXP5 [18] PEG_TXP6 [18] PEG_TXP7 [18] PEG_TXP8 [18] PEG_TXP9 [18] PEG_TXP10 [18] PEG_TXP11 [18] PEG_TXP12 [18] PEG_TXP13 [18] PEG_TXP14 [18] PEG_TXP15 [18]

LVDS

RSVD

TVA_RTN TVB_RTN TVC_RTN TV_DCONSEL_0 TV_DCONSEL_1

+3VDMI_TXP[3:0] [13]

R131 R133

2.2K 2.2K

TV_DCONSEL_0 M35 TV_DCONSEL_1 P33

[2] MCH_BSEL0 [2] MCH_BSEL1 [2] MCH_BSEL2 [11] MCH_CFG_5

[11] MCH_CFG_9 [11] MCH_CFG_12 [11] MCH_CFG_13 [11] MCH_CFG_16 [11] MCH_CFG_19 [11] MCH_CFG_20

CFG9 CFG12 CFG13 CFG16 CFG19 CFG20

GRAPHICS VID

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_RXN[3:0] [13] [22] NB_CRT_B_COM DMI_RXP[3:0] [13] [22] NB_CRT_G_COM [22] NB_CRT_R_COM H32 G32 K29 J29 F29 E29 NB_DDCCLK NB_DDCDAT HSYNC11 CRTIREF VSYNC11 K33 G35 F33 C32 E33 CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

N45 C_PEG_TXN0 C724 U39 C_PEG_TXN1 C744 U47 C_PEG_TXN2 C757 N51 C_PEG_TXN3 C748 R50 C_PEG_TXN4 C750 T42 C_PEG_TXN5 C428 Y43 C_PEG_TXN6 C426 W46 C_PEG_TXN7 C756 W38 C_PEG_TXN8 C436 AD39C_PEG_TXN9 C776 C782 AC46C_PEG_TXN10 C786 AC49C_PEG_TXN11 C443 AC42C_PEG_TXN12 C763 AH39C_PEG_TXN13 C452 AE49 C_PEG_TXN14 C778 AH44C_PEG_TXN15 M45 C_PEG_TXP0 C722 T38 C_PEG_TXP1 C730 T46 C_PEG_TXP2 C745 N50 C_PEG_TXP3 C747 R51 C_PEG_TXP4 C749 U43 C_PEG_TXP5 C427 W42 C_PEG_TXP6 C424 Y47 C_PEG_TXP7 C755 Y39 C_PEG_TXP8 C435 AC38C_PEG_TXP9 C775 C781 AD47C_PEG_TXP10 C785 AC50C_PEG_TXP11 C439 AD43C_PEG_TXP12 C762 AG39C_PEG_TXP13 C456 AE50 C_PEG_TXP14 C784 AH43C_PEG_TXP15

TV

B

DMI

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

CFG

VGA

[22] NB_VSYNC_COM

R128 R112 R124

39 1.3K_6 39

[14] PM_BMBUSY# [3,12,42] H_DPRSTP# [16] PM_EXTTS#0 [14,42] DELAY_VR_PWRGOOD [13] PLT_RST-R# [3,12] PM_THRMTRIP# [14,42] PM_DPRSLPVR

R146 R142

C

R88 R91 R137

0_4 PM_BMBUSY#_R G41 0_4 ICH_DPRSTP#_R L39 PM_EXTTS#0 L36 PM_EXTTS#1 J36 DELAY_VR_PWRGOOD AW49 PLTRST_MCH# 100_4 AV20 PM_THRMTRIP#_GMCH N20 0_4 0_4 PM_DPRSLPVR_GMCH G36

PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN

E35 A39 C38 B39 E36

HSYNC/VSYNC serial R place close to NB

CRESTLINE_1p0

IV&EV Dis/Enable setting[18] PEG_RXP[15:0] [18] PEG_RXN[15:0] [18] PEG_TXP[15:0] [18] PEG_TXN[15:0]

For GM -->39 ohm PM-->NC

PM

SDVO/PCIE/LVDS not implement 16 lanes NC

C

ME

GMCH pwrok is 3.3v tolerant

MISC

DELAY_VR_PWRGOOD

Near to NB*VZ0603M260APT

RV4 2

BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16

CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF

AM49 AK50 AT43 AN49 AM50

CL_CLK0 [14] CL_DATA0 [14] ECPWROK [14,39] CL_RST#0 [14] MCH_CLVREF

SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# TEST_1 TEST_2

H35 K36 G39 G40 A37 R32 2 2 R122 20K

For EV@ Connect to GND CRT R/G/B TV A/B/C HSYNC/VSYNC

For IV@ Connect to 150ohm CRT R/G/B TV A/B/C Connect to 39ohm HSYNC/VSYNC

NC

CLK_3GPLLREQ# [2] MCH_ICH_SYNC# [14]

1

R129 R485 0_4 R121

*39_4 *39_4

HSYNC11 DREF_SSCLK VSYNC11 DREF_SSCLK# R153 *80.6_4 R151 *80.6_4

CRESTLINE_1p0

+1.25V

1.8VSUS 1

R107 R106 R125 1K/F +1.25V 1 1.8VSUS 1 R104

150_4 150_4 150_4

NB_TV_C/R NB_TV_Y/G NB_TV_COMP

If no use DREFCLK PU and DREFCLK# PDMCH_DREFCLK MCH_DREFCLK# R150 R149 *80.6_4 *80.6_4D

1

1

+1.25V

D

SM_RCOMP_VOH 1 1

+3VR141 1 R130 1 2 10K_4 PM_EXTTS#0 2 10K_4 PM_EXTTS#1 2

C309 0.01U/16V_4

C302 2.2U/6.3V_6

R512 1K/F R123 3.01K/F MCH_CLVREF 1 SMRCOMPP SMRCOMPN R511 392/F 2

R110 R78 20/F 2 R111 R119

150_4 150_4 150_4

NB_CRT_B_COM NB_CRT_G_COM NB_CRT_R_COM

If no use DREFCLK PU and DREFCLK# PD

2

2

1

2

2

C283 0.01U/16V_4

C300 2.2U/6.3V_6

C746 0.1U/10V_4 2

1

SM_RCOMP_VOL 1 1 1

For GM -->150 ohm For PM --> 0 ohmSize Date: Document Number

R113 1K/F 2

R77 20/F 2

2

2


1

Crestline (VGA,DMI)Friday, April 13, 20077

2ASheet 68

of

54

1

2

3

4

5

6

1

2

3

4

5

6

7

8

07A

[16] M_A_DQ[63:0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11

U24D SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 CRESTLINE_1p0 SA_BS_0 SA_BS_1 SA_BS_2 SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_RAS# SA_RCVEN# SA_WE# BB19 BK19 BF29 BL17 AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6 AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2 BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 BE18 AY20 BA19 M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CAS# M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_RAS# TP_SA_RCVEN# T18 M_A_WE# M_A_WE# [16,17] M_A_BS#0 [16,17] M_A_BS#1 [16,17] M_A_BS#2 [16,17] M_A_CAS# [16,17] M_A_DM[0..7] [16]

[16] M_B_DQ[63:0] U24E M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 CRESTLINE_1p0 SB_BS_0 SB_BS_1 SB_BS_2 SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_RAS# SB_RCVEN# SB_WE# AY17 BG18 BG36 BE17 AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2 AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3 BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 AV16 AY18 BC17 M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_CAS# M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_RAS# TP_SB_RCVEN# M_B_WE# M_B_BS#0 [16,17] M_B_BS#1 [16,17] M_B_BS#2 [16,17] M_B_CAS# [16,17] M_B_DM[0..7] [16]

A

M_A_DQS[7:0] [16]

A

M_B_DQS[7:0] [16]

MEMORY

M_A_DQS#[7:0] [16]

MEMORY

B

M_B_DQS#[7:0] [16]

B

B

M_A_A[13:0] [16,17]

SYSTEM

M_B_A[13:0] [16,17]

DDR

M_A_RAS# [16,17]

DDR

SYSTEM

M_B_RAS# [16,17] T17 PAD M_B_WE# [16,17]

C

C

D

D

PROJECT : TW7 Quanta Computer Inc.Size Date:1 2 3 4 5 6

Document Number

Crestline (DDR)Friday, April 13, 20077

Rev 1A Sheet 78

of

54

5

4

3

2

1

+1.05VU24G AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32 VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

+3V R446 1 VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83 T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31 10 2 +VCC_GMCH_L D9 1

30mA2 AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37

U24F VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50

CH501H-40PT L-F

08VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28D

VCC CORE

Ivcc (External GFX 1.310 A, integrate 1.572 A)+1.05V

D

+ C660

C131

C312 10U/6.3V_8

C322 0.22U/16V_6

C275 0.22U/16V_6

C251 0.1U/10V_4

R30

2

2

POWERAU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36

Ivcc_AXG Graphics core supply current 7.7A

+ C109 330U/2V/ESR9

+ C95 *330U/2V/ESR9

C109 change to NC(PM)

C

VSS SCB

Layout Note: 370 mils from edge.

POWERVSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6 A3 B2 C1 BL1 BL51 A51C

Layout Note: Inside GMCH cavity for VCC_AXG.

A test check when use external VGA can remove or not.. andrew

VCC GFX NCTF

VCC SM

1

1

1

1

C276

C222

C210

C318 1U/10V_4

1

C316 10U/6.3V_8

C328 10U/6.3V_8

C162 10U/6.3V_8

0.1U/10V_4 0.1U/10V_4 0.47U/10V_6 2 2 2 2

for IAMT power if not support need to connection to S0 power

VCC NCTF

IVCCSM supply current 1 channel 1.615A 2 channel 1.8VSUS 3.318A

Layout Note: Inside GMCH cavity.+1.05V

2

VCC_13

Layout Note: 370 mils from edge.

330U/2V/ESR9 10U/6.3V_8

VSS NCTF

1

1

1

+1.05V VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7 AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

2

+1.05V

GMCH 1.05V current(A) VCC Core VCC_AXG VCC_AXD VTT VCC_PEG VCC_AXM 1.573 7.7 0.2 0.85 1.2 0.54

Remark ( 1.3A for external GFX for ) integrated Gfx

C246 0.1U/10V_4 2 2

C187 0.1U/10V_4 2

C229 0.1U/10V_4

+1.05VR20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14 VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34

B

VCC AXM NCTF

Ivcc_AXM Controller supply current 540mA

FSB VCCP1 C201 C291

for PCIEG10U/6.3V_8 10U/6.3V_8 2

C247 0.22U/16V_6 2

C274 0.22U/16V_6

AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33

for IAMT function DMI

VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19

1

1

1

VCC AXM

B

VCC GFX

VCCR_RX_DMI SUM

0.25 12.313

Layout Note: Place close to GMCH edge.

1

CRESTLINE_1p0

1.8VSUS

VCC SM LF

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

AW45 BC39 BE39 BD17 BD4 AW8 AT6

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7 1 1 1 1 1 1 1 C173 0.1U/10V_4 2 2 C169 2 C139 2 C213 2 C329 2 C334 1U/10V_4 2 C357 1U/10V_4

1

+ C188 C311 0.1U/10V_4 330U/2V/ESR9

C183 10U/6.3V_8

C174 10U/6.3V_8

C123 10U/6.3V_8

C147 10U/6.3V_8

2

A

0.1U/10V_4 0.47U/10V_6 0.47U/10V_6 0.47U/10V_6

Layout Note: Place C901 where LVDS and DDR2 taps.

Layout Note: Place on the edge.A

CRESTLINE_1p0 Size Date:5 4 3 2

PROJECT : TW7 Quanta Computer Inc.Document Number

Crestline (VCC, NCTF)Friday, April 13, 2007 Sheet1

Rev 1A 8 of 54

5

4

3

2

1

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC IV&EV Dis/Enable setting

LVDS Disable/Enable guidelineExternal VGA with EV@part,Internal VGA with IV@ part

CRT/TV Disable/Enable guideline+3V_VCCSYNC +3VL24 1 2 BLM18PG181SN1D C301 0.1U/10V_4 +3V_VCCSYNC

Signal VCCD_LVDS VCCA_LVDS Disable

PM-->Low

External VGA with EV@part,Internal VGA with IV@ partBall VCCA_CRT_DAC VCCD_CRT Enable 3.3V 1.5V 1.5V 3.3V Disable GND GND GND GND GND Ball VCCA_TVC_DAC VCCD_TVDAC VCCA_DAC_BG VSS_DAC_BG VCCSYNC Enable 3.3V 1.5V 3.3V GND 3.3V

If SDVO Disable If LVDS LVDS Disable enable 1.8V GND GND GND 1.8V 1.8V

09D

PM-->Low+1.25V L29 2 10UH_8D

GND 1.5V GND GND GND

VCC_TX_LVDS

80mA1 +1.25V_VCCA_DPLLA

CNF10R223S

22000pf,0.5A

DCR:0.15 ohm

VCCD_QDAC1 + C380 330U/2V/ESR9 2 C364 0.1U/10V_4 +3V L25 1 2 BLM18PG181SN1D 1 +VCCA_CRTDAC

10uH+-20%_100mA

PM-->Low

VCCA_TVA_DAC

VCCA_TVB_DAC 3.3VL32 2 10UH_8 1 2 1

80mA+1.25V_VCCA_DPLLB + C417 330U/2V/ESR9 2 C391 0.1U/10V_4 L68 1 2 BLM18PG181SN1D

+1.05V C319 0.1U/10V_4

+3V_VCC_HV PM-->Low+VCC_TVBG U24H J32 A33 B33 VCCSYNC VCCA_CRT_DAC_1 VCCA_CRT_DAC_2 VCCA_DAC_BG VSSA_DAC_BG VCCA_DPLLA VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1 AT23 AU28 AU24 AT29 AT25 AT30 AR29 B23 B21 A21 AJ50 BK24 BK23 BJ24 BJ23 +1.25V_VCC_AXF +1.25V_VCC_DMI +1.25V_VCC_DMI +1.8VSUS_VCC_SM_CK 2 1 C780 0.1U/10V_4 +1.8VSUS_VCC_TX_LVDS 1.8VSUS L26 2 + C358 1UH_8 1 D1 CH501H-40PT L-F 1 +3V_VCC_HV +1.05V R114 10 R494 R408 1 1 BLM21PG221SN1D 0_4 2 2

0.1Caps should be placed 200 mils with in its pins.

+3V_TV_DAC

CRT

C700 0.1U/10V_4 2

C198 2.2U/6.3V_6 2 2

A30 B32

Ivcc_VTT FSB supply C157 current 4.7uF/6.3V_6 0.85A

40 mil wide

1

1

1

2

1

+1.25V_VCCA_HPLL C658 10U/6.3V_8 2 1

+1.8VSUS_VCC_TX_LVDS

+1.25V_VCCA_HPLL AL2 +1.25V_VCCA_MPLL AM2

VCCA_HPLL VCCA_MPLL

PLL

L62 BLM18PG121SN1D C659 10U/6.3V_8

50mA

+1.25V_VCCA_DPLLB H49

VCCA_DPLLB

VTT

+1.25V

FB_120ohm+-25%_100mHz _2A_0.2ohm DC

Place on the edge.

+1.25V_VCCA_DPLLA B49

Close to NBC158 4.7uF/6.3V_6 + C102 330U/2V/ESR9 +1.25V +1.25V +3V

C156 0.47U/10V_6 2 2

L64 150mA BLM18PG121SN1D +1.25V_VCCA_MPLL 2 1C

1

L33 1 2 BLM21PG221SN1D

100mA

A41 B41

+1.25V_VCCD_PEG_PLL

+3V C347 1000pF/50V

VCCA_LVDS VSSA_LVDS

A LVDS

C663 0.1U/10V_4

+1.25V

PM-->Low

Place on the edge.+1.25V_AXD 1 C262 C260 1U/10V_6 2 10U/6.3V_8 L9 1 C263 10U/6.3V_8 R45 2 +VCC_AXD_R 1 0_4 BLM21PG221SN1D C920 0.1U/10V_4 1 R94 0_8C

FB_220ohm+-25%_100MHz _2A_0.1ohm DC12

1

R157 1_6

L31 1 1 2 BLM18PG181SN1D C377 0.1U/10V_4 K50 K49 +1.25V_VCCD_PEG_PLL U51 AW18 AV19 AU19 AU18 AU17 VCCA_PEG_BG VSSA_PEG_BG VCCA_PEG_PLL VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2 VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2 VCCD_CRT VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL VCCD_LVDS_1 VCCD_LVDS_2 C368 0.1U/10V_4

A PEG

AXD

C664 0.1U/10V_4 2 2

C389 10U/6.3V_8

Ivcca_PEG_BG supply current 100mA

2

2

VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6 VCC_AXD_NCTF VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 VCC_DMI

1

Reserved R45 for Inductor

+1.25V_VCC_AXF 1 C267 1U/10V_6 2 2 C219 10U/6.3V_8

2

100mA

Place caps close to VCC_AXD.

+1.25V

POWERA SM

AXF

Ivcc_DMI supply current 100mAR517 BLM21PG221SN1D

+1.25V

R50 + C106

BLM21PG221SN1D 2 C234 C190 C228 C207 10U/6.3V_8

+1.25V_VCCA_SM C191 10U/6.3V_8 2 1 C211 1U/10V_4

220U/2.5V_ESR35 1

4.7uF/6.3V_6 10U/6.3V_8 10U/6.3V_8

AT22 AT21 AT19 AT18 AT17 AR17 AR16 BC29 BB29

Place caps close to VCC_AXF

SM CK

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

200mA

PM-->LowVCC_TX_LVDS VCC_HV_1 VCC_HV_2 VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5 A43 C40 B40 1 AD51 W50 W51 V49 V50 AH50 AH51 A7 F2 AH1 C718 0.1U/10V_4 2 +VCC_PEG +VCC_RXR_DMI + C772 +1.8VSUS_VCC_TX_LVDS +3V_VCC_HV

100mA

+1.25V

1

R95 1 C919 0.1U/10V_4

BLM18PG181SN1D 1 C217 10U/6.3V_8 C259 10U/6.3V_8

+1.25V_VCCA_SM_CK 1 C252 1U/10V_4 C282 1U/10V_4 1 +3V_TV_DAC C280 0.1U/10V_4 C752 1 +3V_TV_DAC +3V_TV_DAC 0.1U/10V_4 2 +1.5V_VCCD_CRT +1.5V_VCCD_TVDAC +1.5V_VCCD_QDAC R48 0_6 250 mA VCCD_HPLL +1.25V_VCCD_PEG_PLL 1 1

A CK

1uH+-20%_300mA

+1.5V R98 BLM18PG181SN1D 1

60 mA 60 mA

R109

0_6

1

M32 L29 N28 AN2 U48 J41 H42

D TV/CRT

+1.5V_VCCD_TVDAC +1.5V_VCCD_TVDAC

PEG

C25 B25 C27 B27 B28 A28

HV

C354 1000P/50V 2

220U/2.5V_ESR35

TV

2

2

2

2

+VCC_PEG L73 BLM21PG221SN1D C779 10U/6.3V_8

+1.05V

Ivcc_PEG supply current 1.2ASeparate DMI and PEG power -->B2A+VTTLF1 +VTTLF2 +VTTLF3 1 1 1B

DMI

C266 0.1U/10V_4 2 2 L22 1 2 +VCCQ_TVDAC R276 BLM18PG181SN1D 1 C914

VCC_RXR_DMI_1 VCC_RXR_DMI_2

+1.25V

220U/2.5V_ESR35 H=1.9 +VTTLF1 +VTTLF2 +VTTLF3

+1.05V L72 BLM21PG221SN1D C901 10U/6.3V_8

VTTLF

B

100_6 1

VCCD_LVDS C375 0.1U/10V_4

4.7uF/6.3V_6 2

FB_180ohm+-25%_ 100mHz_1500mA_ 0.09ohm DC

C203 0.1U/10V_4 2

PM-->Low1.8VSUSR637 0_6

+ C902 CRESTLINE_1p0 220U/2.5V_ESR35

2

1

C148 0.1U/10V_4

LVDS

C2B

250mA

VTTLF1 VTTLF2 VTTLF3

2

150mA

Ivcc_RX_DMI supply current 250mA

C662 0.47U/10V_6 2 2

C150 0.47U/10V_6 2

1

C677 0.47U/10V_6

PM-->LowC299 C161 10U/6.3V_8

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DCRESISTOR CHIP 100 1/10W +-5%(0603)EPCS11003J947-->C227

1U/10V_4

60 mils or 80 mils+VCC_RXR_DMI VCC_PEGC230 +1.8VSUS_VCC_SM_CK 1

2

L14 1UH_8 2

1.8VSUS 1

1uH+-20%_300mA

+3V_TV_DAC+3V L67 1 2 1 1

2

For GM C301 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_5

For PM0 ohm,0402 0 ohm,0402 0 ohm,0402 0 ohm,0402 0 ohm,0402 0 ohm,0402 0 ohm,0402 0 ohm,0402 0 ohm,0402 0 ohm,0402 0 ohm,0403 L67 L24 L25 L26 L68 R109 R637 L22

For GM BLM18PG181SN1D BLM18PG181SN1D BLM18PG181SN1D 1UH_8 BLM18PG181SN1D 0_6 0_6 BLM18PG181SN1D

For PMNo stuff No stuff No stuff No stuff No stuff No stuff No stuff No stuff

12 2

PM-->Low

C231 10U/6.3V_8

10U/6.3V_8

R80 1_6 C258 0.1U/10V_4 +VCC_SM_CK_L C204 10U/6.3V_8

BLM18PG181SN1D C693 10U/6.3V_8

C699 0.1U/10V_4 2 2

C319 C700 C752 C347 C299 C699 C697 C695

22nF & 0.1uF for VCC_TVDACA:C_R should be placed with in 250 mils from Crestline.

PM-->Low1

CVA9115MN10 , IND 91NH+-20% 1.5A NLFC322522T-091M

C697 0.1U/10V_4 2

A

1

A

PM-->Low1

C354 C203

C695 0.1U/10V_4 2

PROJECT : TW7 Quanta Computer Inc.Size Date:5 4 3 2

Document Number

Rev

Crestline (POWER)Friday, April 13, 20071

3ASheet 9 of 54

5

4

3

2

1

U24I A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41 C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39 K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3

U24J VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 CRESTLINE_1p0 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28

10D

D

VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

VSS

C

C

VSS

B

B

A

A

CRESTLINE_1p0


Document Number

Crestline (VSS)Friday, April 13, 2007 Sheet1

Rev 1A 10 of 54

5

4

3

2

1

Strap tableAll strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal CFG[17:3] Have internal Pull-up CFG[18:19] Have internal Pull-down Any CFG signal strapping option not list below should be left NC Pin Pin Name CFG[2:0]D

11D

Strap description FSB Frequency Select

Configuration 010 = FSB 800MHz 011 = FSB 667MHz

CFG[4:3] CFG5

Reserved DMI X2 Select 0 = DMI X2 1 = DMI X4(Default)

CFG6 CFG7

Reserved CPU Strap 0 = Reserved 1 = Mobile CPU(Default) 0 = Normal mode 1 = Low Power mode 0 = Reverse Lanes 1 = Normal operation(Default)

CFG8

Low power PCI Express

CFG9

PCI Express Graphics Lane Reversal

CFG[11:10]C

Reserved XOR/ALLZ 00 01 10 11 = = = = Reserved XOR Mode Enable All-Z Mode Enabled Normal operation(Default)C

CFG[13:12]

CFG[15:14] CFG16

Reserved FSB Dynamic ODT 0 = Dynamic ODT disable 1 = Dynamic ODT Enable(Default)

CFG[18:17] SDVO_CTRLDATA

Reserved SDVO Present 0 = No SDVO Card present(Default) 1 = SDVO Card Present 0 = Normal operation(Default) 1 = Reverse Lanes 0 = Only SDVO or PCIE x1 is operation(Default) 1 = SDVO and PCIE x1 are operating simultaneously via the PEG portB

CFG19

DMI Lane Reversal

CFG20B

SDVO/PCIe concurrent

DMI X2 SelectMCH_CFG_5 Low = DMIX2 High = IDMIX4(Default)

DMI Lane ReversalMCH_CFG_19 Low = Normal operation(Default) High = Reverse Lane

XOR /ALLz /Clock Un-gatingMCH_CFG_12MCH_CFG_13 0 0 1 0 1 Configuration Clock gating disable XOR Mode Enable ALL-z Mode Enable

PCI Express GraphicsMCH_CFG_9 Low = Reverse Lane High = Normal operation(Default)

SDVO Present Strap define at External DVI control page

[6] MCH_CFG_5

+3V0 1 R96 R132 *4.02K_4 *4.02K_4 1 Normal operation(Default)

[6] MCH_CFG_9

R92 *4.02K_4

[6] MCH_CFG_19

FSB Dynamic ODTMCH_CFG_16 Low = ODT Disable High = ODT Enable(Default)

SDVO/PCIE Concurrent operationMCH_CFG_20 Low = Only SDVO or PCIE X1 is operational(Default) High = SDVO andPCIE X1 are operating simultaneously via the PEG port [6] MCH_CFG_12 [6] MCH_CFG_13

A

[6] MCH_CFG_16

A

+3V

R102 *4.02K_4

R101 *4.02K_4

R90 *4.02K_4 R134 *4.02K_4 Size [6] MCH_CFG_20 Date:5 4 3 2

PROJECT : TW7 Quanta Computer Inc.Document Number

10 -- GMCH STRAP-3(6 of 6)Friday, April 13, 20071

Rev 1A 11 of 54

Sheet

5

4

3

2

1

RTC3VPCU

VCCRTCC737 1U/10V_4 VCCRTC D10 CH501H-40PT L-F R199 20K/F VCCRTC_2 D11 R582 CH501H-40PT L-F 1K/F C738 1U/10V_4 R190 1M_4 2 1 C393

CKL:C1/C2: 18pF -> CL:12.5pF C1/C: 10pF -> CL Value = 8.5pF 10ppm,12.5pfCLK_32KX1 2 1 12PF/50V_4 Y1 *SHORT_ PAD1 G1 32.768KHZ 3 4 C392 12PF/50V_4 CH01206JB05 , CAP CHIP 12P 50V(+-5%,C0G,0402) RV8

H_PWRGD

Near to SB+3V *VZ0603M260APT +3V

12R235 10K_4 R228 10K_4D

R160 10M_6 U31A CLK_32KX2 RTCRST# SM_INTRUDER# ICH_INTVRMEN LAN100_SLP AG25 AF24 AF23 AD22 AF25 AD21 B24 D22 C21 B21 C22 RTCX1 RTCX2 RTCRST# INTRUDER# FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 FWH4/LFRAME# E5 F5 G8 F6 C4 G9 E6 AF13 AG26 AF26 AE26 AD24 AG29 AF27 AE24 AC20 AH14 AD23 AG28 AA24 AE27 AA23 V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6 AA4 AA1 AB3 Y6 Y5 W4 W3 Y2 Y3 Y1 W5 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PDA0 PDA1 PDA2 H_THERMTRIP_R T31 R508 0_4 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ#0 GATEA20 H_DPRSTP#_R H_DPSLP#_R LAD0 LAD1 LAD2 LAD3 [35,39,41] [35,39,41] [35,39,41] [35,39,41]

D

4 3 2 1

2

1

+1.05V

RCIN# GATEA20 +1.05V

CN6 DFHD02MS784

LFRAME# [35,39,41] LDRQ#0 GATEA20 [39] H_A20M# [3] R185 R174 0_4 0_4 R176 *56_4 R180 *56_4

GLAN_CLK LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2

RTC LPC

INTVRMEN LAN100_SLP

LDRQ0# LDRQ1#/GPIO23 A20GATE A20M# DPRSTP# DPSLP# FERR#

R195 56_4 H_DPRSTP# [3,6,42] H_DPSLP# [3] H_FERR# [3] H_PWRGD [3] H_IGNNE# [3] H_INIT# [3] H_INTR [3] RCIN# [39]

R580 1.2K_6 R581 4.7K_4

VCCRTC_1

R585 1K/F

VCCRTC_3

Q30 3

1 MMBT3904

D21 E20 C20 AH21 R178 24.9_6 GLAN_COMP_SB ACZ_BCLK ACZ_SYNC D25 C25 AJ16 AJ15 AE14 AJ17 AH17 AH15 AD13 AE13 AE10 AG14 AF10 AF6 AF5 AH5 AH6 AG3 AG4 AJ4 AJ3 AF2 AF1 AE4 AE3

LAN_TXD0 LAN_TXD1 LAN_TXD2

LAN / GLAN CPU

5VPCU

20MIL

20MIL

CPUPWRGD/GPIO49 IGNNE# INIT# INTR RCIN# NMI SMI# STPCLK#

+1.05V

ENERGY_DETECT/GPIO13 GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC HDA_RST#

+1.5V_PCIE

RCIN# H_SMI#_R R507 0_4

2

H_NMI [3] H_SMI# [3] H_STPCLK# [3] R506 PDD[15:0] [31]

Within 2"

R509 56_4C

R586C

ACZ_RST# [32] ACZ_SDIN0 [34] ACZ_SDIN1 ACZ_SDIN0 ACZ_SDIN1

15K

THRMTRIP# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDOUT TP8 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15

24.9_6

PM_THRMTRIP# [3,6]

IHDA

ACZ_SDOUT +3V R250 [26] LAN_DISABLE# 10K_4 LAN_DISABLE# SATA_LED# SATA_RXN0_C SATA_RXP0_C 3900P/25V SATA0TXN 3900P/25V SATA0TXP

Should be 2" close ICH7

C729 *SFI0603-050E101NP

HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 SATALED# SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP

[28] SATA_LED# [31] SATA_RXN0_C [31] SATA_RXP0_C [31] SATA_TXN0 [31] SATA_TXP0

C501 C499

ACZ_SDOUT

R230

33

ACZ_SDOUT_AUDIO [32] C483 *10P/50V_4

CKL:1n ~ 20nF

IDE

PDA[2:0] [31] ACZ_SYNC R525 33 ACZ_SYNC_AUDIO C798 *10P/50V_4 BK1608LL241-T ACZ_BCLK R531 BIT_CLK_AUDIO [32]B

SATA

SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS ICH8M REV 2.0

DA0 DA1 DA2 DCS1# DCS3# DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ

[32]

PDCS1# [31] PDCS3# [31] PDIOR# [31] PDIOW# [31] PDDACK# [31] IRQ14 [31] PDIORDY [31] PDDREQ [31]

[2] CLK_PCIE_SATA# [2] CLK_PCIE_SATAB

CLK_PCIE_SATA# CLK_PCIE_SATA R561 24.9_6 SATA_BIAS

AB7 AC6 AG1 AG2

IRQ14 PDIORDY

Place within 500 mils of ICH7

25mils/15mils

C799 22PF/50V_4 ACZ_RST# R232 33

ACZ_RST#_AUDIO [32]

SB StrapICH8-M Internal VR Enable strap (Internal VR for Vccsus1_05,VccSus1_5 and VccCL1_5)INTVRMEN Low = Internal VR disable High = Internal VR enable(Default)

XOR Chain Entrance StrapICH_RSV0 HDA_SDOUT 0 1 0 1 +3V Description RSVD

intel check list define to stuff 33ohmACZ_SDOUT R243 33 C493 *10P/50V_4 ACZ_SDOUT_AUDIO_MDC [34]

ICH8-M LAN100_SLP Strap (Internal VR for VccLAN1_05 and VccCL1.05)LAN100_SLP Low = Internal VR disable High = Internal VR enable(Default)

0 0 1 1

ACZ_SYNC Enter XOR Chain Normal opration(Default) Set PCIE port config bit 1 ACZ_BCLK

R238

33 C489 *10P/50V_4

ACZ_SYNC_AUDIO_MDC

[34]

R236

BK1608LL241-T C487 22PF/50V_4

BIT_CLK_AUDIO_MDC [34]

VCCRTC

VCCRTC

A

A

R186 332K/F ICH_INTVRMEN

R188 332K/F LAN100_SLP

R528 *1K ACZ_SDOUT ICH_TP3 [14]

ACZ_RST#

R231

33

ACZ_RST#_AUDIO_MDC [34]

R181 *0_4

R197 *0_4 R521 *1K Size Date:5 4 3 2

PROJECT : TW7 Quanta Computer Inc.Document Number Rev

ICH8-M HOST,SATA,LPCFriday, April 13, 2007 Sheet1

2A12 of 54

5

4

3

2

1

U31D

+3VDMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP DMI_CLKN DMI_CLKP V27 V26 U29 U28 Y27 Y26 W29 W28 AB26 AB25 AA29 AA28 AD27 AD26 AC29 AC28 T26 T25 Y23 Y24 G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2 F2 F3 USB_RBIAS_PN RP40 DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 [6] [6] [6] [6] [6] [6] [6] [6] [6] [6] [6] [6] [6] [6] [6] [6] REQ2# REQ1# FRAME# STOP# 6 7 8 9 10 8.2KX8 5 4 3 2 1 TRDY# IRDY# DEVSEL# INTG#

PCIE-LAN(Marvell Lan)D

[26] [26] [26] [26] [35] [35] [35] [35]

PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3

C733 C734

0.1U/10V_4 0.1U/10V_4

PCIE_TXN2_C PCIE_TXP2_C

M27 M26 L29 L28 K27 K26 J29 J28 H27 H26 G29 G28 F27 F26 E29 E28

PCI-Express Direct Media Interface

For Wireless MINI CARD1 PCI-E

[35] [35] [35] [35]

PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1

C739 C740

0.1U/10V_4 0.1U/10V_4


P27 P26 N29 N28

PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5

14D

+3V

+3VRP42 REQ0# PERR# SERR# 6 7 8 9 10 8.2KX8 5 4 3 2 1 LOCK# INTD# INTF# REQ3#

MINI CARD2 PCI-E For Robson

C735 C736

0.1U/10V_4 0.1U/10V_4


+1.5V_PCIE

+3V

+3VRP43 R166 24.9_6 INTH# 6 7 8 9 10 8.2KX8 5 4 3 2 1

CLK_PCIE_ICH# [2] CLK_PCIE_ICH [2] DRI_IRCOMP_R USBP0USBP0+ USBP1USBP1+ USBP2USBP2+ USBP3USBP3+ USBP4USBP4+ USBP5USBP5+ USBP6USBP6+ USBP7USBP7+ USBP8USBP8+ USBP9USBP9+ [28] [28] [28] [28] [27] [27] [23] [23] [38] [38] [36] [36] [35] [35] [36] [36] [28] [28] [35] [35]

EXPRESS CARD (NEW CARD)

[36] [36] [36] [36]

PCIE_RXN6 PCIE_RXP6 PCIE_TXN6 PCIE_TXP6

C731 C732

0.1U/10V_4 0.1U/10V_4


D27 D26 C29 C28 C23 B23 E22 D23 F21

DMI_ZCOMP DMI_IRCOMP USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBRBIAS# USBRBIAS

15/15milsExt Left Side Ext Left Side Top

PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP SPI_CLK SPI_CS0# SPI_CS1# SPI_MOSI SPI_MISO OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9#

Place within 500 mils of ICH7 +3V

INTB# INTC# INTE# INTA#

SPI_CS1#

Ext Right Side Top CAMERA Docking Bluetooth Mini Card WLAN Express Card 1 Ext Right Side Express Card 2USBOC#8 USBOC#9 USBOC#2 USBOC#4 USBOC#6 USBOC#3 6 7 8 9 10

RP41 5 4 3 2 1 8.2KX8C

SPI

C

USBOC#0 USBOC#1 USBOC#2 USBOC#3 USBOC#4 USBOC#5 USBOC#6 USBOC#7 USBOC#8 USBOC#9

AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18

3V_S5

USBOC#1 USBOC#7 USBOC#0 USBOC#5

USB

R223 R218

10K_4 10K_4

3V_S5 3V_S5 pull up 10k

CHECK LIST suggest

ICH8M REV 2.0

25mils/15milsPlace within 500 mils of ICH7R564 22.6/F

A16 SWAP Override strapPCI_GNT#3 Low = A16 swap override enabled High = Default R239 *10K_4

GNT3# [29] AD[0..31] U31B AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 INTA# INTB# INTC# INTD#A

B

D20 E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15 B6 C11 A9 D11 B12 C12 D10 C7 F13 E11 E13 E12 D8 A6 E8 D6 A3 F9 B5 C5 A10

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PIRQA# PIRQB# PIRQC# PIRQD#

PCI

REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME#

A4 D7 E18 C18 B19 F18 A11 C10 C17 E15 F16 E17 C8 D9 G6 D16 A7 B7 F10 C16 C9 A17 AG24 B10 G7

REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3#

REQ0# [29] GNT0# [29] T34 T33

ICH8 Boot BIOS selectPCI_GNT#0 0 SPI_CS#1 1 0 1 R191 R257 *10K_4 *10K_4 Boot BIOS Location SPI(Default) PCI LPCB

C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# LOCK# SERR# STOP# TRDY# FRAME# PLT_RST-R# CLK_PCI_ICH PCI_PME#

[29] [29] [29] [29]

1 1 SPI_CS1# GNT0#

IRDY# [29] PAR [29] PCIRST# [29] DEVSEL# [29] PERR# [29] SERR# [29,39] STOP# [29] TRDY# [29] FRAME# [29] PLT_RST-R# [6] CLK_PCI_ICH [2] PCI_PME# [29]

PCI ROUTING IDSEL TABLE REQ0# / GNT0# AD25

INTERUPT INTE#,INTF#

DEVICE TI7402

+3V

C450 PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 F8 G11 F12 B3 INTE# INTF# INTG# INTH# INTE# [29] INTF# [29] PLT_RST-R# 0.1U/10V_4 5 U30 2 4 1 TC7SH08FU 3 R523 100K_4 PLTRST# [14,18,26,31,35,36,39,41]A

Interrupt I/F

Don't connect to PCI device / Express card

ICH8M REV 2.0

CLK_PCI_ICH

R259

*0_4

C503 *33P/50V_4 Size Date: Document Number


for EMI request5 4 3 2

ICH8-M M PCI E(2/4)Friday, April 13, 2007 Sheet1

2A13 of 54

5

4

3

2

1

4P2R-S-2.2K CL_RST#1 SMB_ALERT# 2 4 RP59 C451 5 4 VR_PWRGD_CK410 NL17SZ14DFT2GD

3V_S5 1 3 PCIE_WAKE# R212 1K/F

3V_S5ICH_RI# DNBSWON# PM_BATLOW#_R R208 8.2K SYS_RST# R225 8.2K 10K_4 10K_4 SWI#_R R229 R171 10K_4 10K_4 100K_4 *0.1U/10V_4 PM_RSMRST#_R SMLINK0 SMLINK1 R206 R202 R219 8.2K

3V_S5

+3VCLKRUN# R534 R233 R541 R540 8.2K 8.2K 10K_4 10K_4

+3VU29 [42] VR_PWRGD_CK410# 1 2 3 0.1U/10V_4

D3A R261

10K_4 SERIRQ SCI#_R KBSMI#_R

14EMI solutionD

3V_S5 RP39 PDAT_SMB PCLK_SMB 4 2 4P2R-S-2.2K U31C 3 1

PLTRST_LAN# C797

Place these close to ICH8MCLK_ICH_48M CLK_ICH_14M R258 *10 1 R252 *10_NC 12 C506 *4.7P_50V 2 2 C496 *4.7P_50V_NC

VR_PWRGD_CK410 R522

E3BSATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37 CLK14 CLK48 SUSCLK SLP_S3# SLP_S4# SLP_S5# S4_STATE#/GPIO26 AJ12 AJ10 AF11 AG11 AG9 G5 D3 AG23 AF21 AD18 AH27 AE23 AJ14 AE21 C2 AH20 AG27 E1 E3 AJ25 F23 AE18 F22 AF19 D24 AH23 AJ23 AJ27 AJ24 AF22 AG19 ICH_PWROK DPRSLPVR-ICH PM_BATLOW#_R DNBSWON# PLTRST_LAN# PM_RSMRST#_R R557 R260 SUSM# T64 CL_CLK0 ICH_CL_CLK1 CL_DATA0 ICH_CL_DATA1 CL_VREF0_SB CL_VREF1_SB CL_RST#0 R519 10K_4 CL_RST#0 [6] T66 C474 R209 453/F T68 0.1U/10V_4 CL_CLK0 [6] ICH_CL_CLK1 [35] CL_DATA0 [6] ICH_CL_DATA1 [35] R203 3.24K/F_6 0_4 0_4 R524 R170 100_4 100_4 CK_PWG [2] ECPWROK [6,39] RSMRST# R526 R213 475_4 PM_DPRSLPVR 0_4 PM_DPRSLPVR [6,42] BATLOW# [39] DNBSWON# [39] PLTRST# [13,18,26,31,35,36,39,41] RSMRST# [39] R194 R205 R645 100_4 100_4 *100_4 R527 *100K_4 SUSB# [39] SUSC# [39] BOARD_ID1 BOARD_ID0 BOARD_ID3 BOARD_ID4 CLK_ICH_14M CLK_ICH_48M CLK_ICH_14M [2] CLK_ICH_48M [2]

SMB

+3V

SATA GPIO

[2,36] PCLK_SMB [2,36] PDAT_SMB [35] CL_RST#1

R221 *10K/F

R220 *10K/F

[29,41] SUS_STAT# [3] SYS_RST# [6] PM_BMBUSY#

SUS_STAT# SYS_RST# R532 0_4

F4 AD15 AG12 AG22 AE20 AG18

SUS_STAT#/LPCPD# SYS_RESET# BMBUSY#/GPIO0 SMBALERT#/GPIO11

SMB_ALERT# [2] PM_STPPCI# [2] PM_STPCPU# R214 R215 [29,39,41] CLKRUN# 0_4 0_4 CLKRUN# PCIE_WAKE# SERIRQ VR_PWRGD_CK410

Clocks

ICH_RI#

AF17

RI#

D3A

SYS GPIO Power MGT

STP_PCI#/GPIO15 STP_CPU#/GPIO25 CLKRUN#/GPIO32 WAKE# SERIRQ THRM# VRMPWRGD TP7 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 GLAN_DOCK#/GPIO12 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 SPKR MCH_SYNC# TP3 ICH8M REV 2.0

PWROK DPRSLPVR/GPIO16 BATLOW# PWRBTN# LAN_RST# RSMRST# CK_PWRGD CLPWROK SLP_M# CL_CLK0 CL_CLK1

AH11 AE17 AF12 AC13 AJ20 AJ22

close to ICH[4] THERM_ALERT#C

[26,35,36] PCIE_WAKE# [29,39,41] SERIRQ R224 *0_4 8.2K T65

+3V

R227

LAN_RST pin : 1.if used pci LAN please tie to PLTRST# 2.if used PHY LAN please tie to RSMRST#

12

PCLK_SMB PDAT_SMB CL_RST#1 SMLINK0 SMLINK1

AJ26 AD19 AG21 AC17 AE19

SMBCLK SMBDATA LINKALERT#/CL_RST1# SMLINK0 SMLINK1

1

C

[39] KBSMI# [39] SCI# [39] SWI#

KBSMI# SCI# SWI#

R537 R538 R217

0_4 0_4 0_4

KBSMI#_R SCI#_R SWI#_R

T35 BOARD_ID2

MISC GPIO Controller Link

+3V[33] ACZ_SPKR [6] MCH_ICH_SYNC# R529 R530 0_4

R536 R248

0830

BOARD_ID5 10K_4 10K_4

AJ8 AJ9 AH9 AE16 AC19 AG8 AH12 AE11 AG10 AH25 AD16 AG13 AF9 AJ11 AD10 AD9

3V_S5

+3V

CL_DATA0 CL_DATA1 CL_VREF0 CL_VREF1 CL_RST0# MEM_LED/GPIO24 ME_EC_ALERT/GPIO10 EC_ME_ALERT/GPIO14 WOL_EN/GPIO9

R193 3.24K/F_6

C457 R187 453/F 0.1U/10V_4

MCH_ICH_SYNC#_R [12] ICH_TP3

AJ13 AJ21

3VSUS

+3VB

*10K_4

No Reboot strapHDA_SPKR Low = Default High = No Reboot RV5 ICH_PWROK

Controller Link 1 VREF for IAMT support only

Controller Link 0 VREF for IAMT support only

B

CK_PWG

Near to SBRV9 *VZ0603M260APT

Near to SB*VZ0603M260APT

1

1

3VSUS CRB STUFF 2K%1 +3V[6,42] DELAY_VR_PWRGOOD [6,39] ECPWROK R182 2K/F 5 U9 4 1 TC7SH08FU R183 100K_4 3 R196 10K_4 ICH_PWROK C468 0.047uF/10V

+3V2 ACZ_SPKR R251 *1K_4

2

2

BOARD ID Selection+3V1

Near to SB

+3V1

+3V1

+3V

+3V

+3V

Board ID1

Function 00: TW7 01: DW7 10: SW7 1:Without Modem 0:Modem 1:Without Internal Mic

ID [1:0]R256 10K_4

R539 *10K_4 2 2A

R535 *10K_4 BOARD_ID1 1 1 2

R245 *10K_4 BOARD_ID2 1

R242 *10K_4 BOARD_ID3 1

R237 10K_4 BOARD_ID4

ID2BOARD_ID0 1 BOARD_ID5 R255 *10K_4 2 1 2

A

ID3 ID4 ID5

0:Internal MIC 0: No docking. 1: w/ docking 1: CRT 0: DVISize Date: Document Number

R542 10K_4 2 2

R533 10K_4 2

R246 10K_4 2

R241 10K_4 2

R240 *10K_4


ICH8-M GPIO(3/4)Friday, April 13, 2007 Sheet1

2A14 of 54

5

4

3

2

5

4

3

2

1

3V_S52 D3 D2 CH501H-40PT L-F U31E A23 A5 AA2 AA7 A25 AB1 AB24 AC11 AC14 AC25 AC26 AC27 AD17 AD20 AD28 AD29 AD3 AD4 AD6 AE1 AE12 AE2 AE22 AD1 AE25 AE5 AE6 AE9 AF14 AF16 AF18 AF3 AF4 AG5 AG6 AH10 AH13 AH16 AH19 AH2 AF28 AH22 AH24 AH26 AH3 AH4 AH8 AJ5 B11 B14 B17 B2 B20 B22 B8 C24 C26 C27 C6 D12 D15 D18 D2 D4 E21 E24 E4 E9 F15 E23 F28 F29 F7 G1 E2 G10 G13 G19 G23 G25 G26 G27 H25 H28 H29 H3 H6 J1 J25 J26 J27 J4 J5 K23 K28 K29 K3 K6 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] ICH8M REV 2.0 C454 10U/6.3V_8 VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12] K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24 A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29 CH501H-40PT L-F

+3V VCCRTC2 C471 1U/10V_4 C461 0.1U/10V_4 C466 0.1U/10V_4 AD25 +5VREF_SB C494 0.1U/10V_4 +5VREF_SUS_SB A16 T7 G4 AA25 AA26 AA27 AB27 AB28 AB29 D28 D29 E25 E26 E27 F24 F25 G24 H23 H24 J23 J24 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25 W25 Y25 AJ6 C490 1U/10V_6 AE7 AF7 AG7 AH7 AJ7 AC1 AC2 AC3 AC4 AC5 AC10 AC9 AA5 AA6 C804 0.1U/10V_4 G12 G17 H7 AC7 AD7 D1 F1 L6 L7 M6 M7 +1.5V_SATA TP_VCCLAN1_05_ICH_1 TP_VCCLAN1_05_ICH_2 W23 F17 G18 F19 G20 A24 A26 A27 B26 B27 B28 C453 10U/6.3V_8 B25 1 U31F VCCRTC V5REF[1] V5REF[2] V5REF_SUS VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] VCCSATAPLL VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05] VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] VCC1_5_A[09] VCC1_5_A[10] VCC1_5_A[11] VCC1_5_A[12] VCC1_5_A[13] VCC1_5_A[14] VCC1_5_A[15] VCC1_5_A[16] VCC1_5_A[17] VCC1_5_A[18] VCC1_5_A[19] VCCPSUS VCCUSBPLL VCC1_5_A[20] VCC1_5_A[21] VCC1_5_A[22] VCC1_5_A[23] VCC1_5_A[24] VCC1_5_A[25] VCCPUSB VCCLAN1_05[1] VCCLAN1_05[2] VCCLAN3_3[1] VCCLAN3_3[2] VCCGLANPLL GLAN POWER VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] VCCGLAN1_5[5] VCCGLAN3_3 ICH8M REV 2.0 R200 R179 0_6 +3V_GLAN TP_VCCLAN1_05_ICH_1 TP_VCCLAN1_05_ICH_2 C478 C480 C497 C477 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0_6 VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] VCC1_05[27] VCC1_05[28] VCCDMIPLL VCC_DMI[1] VCC_DMI[2] V_CPU_IO[1] V_CPU_IO[2] VCC3_3[01] VCC3_3[02] VCCP_CORE VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06] VCC3_3[07] VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] VCC3_3[14] VCC3_3[15] VCC3_3[16] VCC3_3[17] VCC3_3[18] VCC3_3[19] VCC3_3[20] VCC3_3[21] VCC3_3[22] VCC3_3[23] VCC3_3[24] VCCHDA VCCSUSHDA VCCSUS1_05[1] VCCSUS1_05[2] VCCSUS1_5[1] VCCSUS1_5[2] VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04] VCCSUS3_3[05] VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCCL1_05 VCCCL1_5 VCCCL3_3[1] VCCCL3_3[2] A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 R29 AE28 AE29 AC23 AC24 AF29 AD2 AC8 AD8 AE8 AF8 AA3 U7 V7 W1 W6 W7 Y7 A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11 AC12 AD11 J6 AF20 AC16 J7 C3 AC18 AC21 AC22 AG20 AH28 P6 P7 C1 N7 P1 P2 P3 P4 P5 R1 R3 R5 R6 G22 A22 F20 G21 VCCCL1_5_INT_ICH +V3.3M_ICH C465 1U/10V_4 C470 0.1U/10V_4 +V3.3A_ICH C434 0.1U/10V_4 C460 0.1U/10V_4 R201 +V3.3_DMI_ICH +V3.3_SATA_ICH +V3.3S_VCCPCORE_ICH C805 0.1U/10V_4 +V3.3S_IDE_ICH C807 0.1U/10V_4 R254 R559 +V3.3S_PCI_ICH R207 0_6 0_6 0_6 C741 0.1U/10V_4 R505 R560 0_6 0_6

+1.05V

15+1.5VL35 1UH_1210D

5V_S5

R262

10_6

+5V R247C507 0.1U/10V_4

100_6

C486 0.1U/10V_4

C484 0.1U/10V_4

1

+1.5V_PCIE

D

VCCDMIPLL_ICH C419 0.01U/16V_4 C420 10U/6.3V_8

R161

1

BLM18PG121SN,CX8PG121009,120 ohm,2000mAL34

+1.5VBLM21PG221SN1D + C463 220U/2.5V_ESR35 C462 10U/6.3V_8 C425 10U/6.3V_8 C440 10U/6.3V_8 C445 10U/6.3V_8 C433 2.2U/6.3V_6

CORE

+1.25V+1.25V_DMI C743 10U/6.3V_8 C455 0.1U/10V_4 C467 0.1U/10V_4 C472 4.7uF/6.3V_6 R503 C742 10U/6.3V_8 0_8 R192 0_6

+1.5V

+1.05V

100mAR264 +1.5V_SATA R263 0_8 1 +1.5V_APLL_RR L40 +1.5V_APLL 10UH_8 C508 10U/6.3V_8 C509 1U/10V_4

VCCA3GP

+1.05V_V_CPU_IO

+3V

C

C

C495 1U/10V_6

IDE ARX PCI ATX

C485

C479

C481 0.1U/10V_4

0.1U/10V_4 0.1U/10V_4

+3V_1.5V_HDA_IO_ICH +VCCSUSHDA TP_VCCSUS1_05_ICH_1 TP_VCCSUS1_05_ICH_2 C492 R234 0_6

R244

0_6

+3V

3V_S5

C488

Can be connect to +3V_S5 or

Can be connect to 0.1U/10V_4 +3V or +1.5V

R558

0_6

+1.5V_USB

0.1U/10V_4 +1.5V_S5

3V_S50_6B

B

USB CORE

C803 0.1U/10V_4

+V3.3A_USB_ICH C535 0.1U/10V_4 C532 0.1U/10V_4 C528 0.1U/10V_4 C521

R562 C811 10U/6.3V_8

0_8

0.1U/10V_4

+3V

R211

0_6 C476

+3V_VCCLAN +1.5V_VCCGLANPLL 0.1U/10V_4 L36 1UH_1210

+1.5V

R163

1

+1.5V_PCIE +3VA

+3VA

Close to SB(U31)C905 0.1U/10V_4 C904 0.1U/10V_4 C903 0.1U/10V_4 C544

C438 10U/6.3V_8

+3V

TP_VCCSUS1_05_ICH_1 0.1U/10V_4 TP_VCCSUS1_05_ICH_2


Document Number

ICH8-M POWER(4/4)Friday, April 13, 20071

Rev 2A Sheet 15 of 54

1

2

3

4

5

6

7

8

+3V 1.8VSUS

H=5.2Near CN16 Pin1

+3V [2,4,6,8,9,11,12,13,14,15,18,19,20,23,24,25,29,30,31,32,33,35,36,37,39,41,48] 1.8VSUS [6,8,9,41,44] M_A_DM[0..7] [7] M_A_DQ[0..63] [7] M_A_DQS[0..7] [7] M_A_DQS#[0..7] [7] M_A_A[0..13] [7,17]

H=9.21.8VSUSSMDDR_VREF_DIMM 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 CN15 VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50 VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD) VSS46 DQ4 DQ5 VSS15 DM0 VSS5 DQ6 DQ7 VSS16 DQ12 DQ13 VSS17 DM1 VSS53 CK0 CK0# VSS41 DQ14 DQ15 VSS54 VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

M_B_DM[0..7] [7] M_B_DQ[0..63] [7] M_B_DQS[0..7] [7] M_B_DQS#[0..7] [7] M_B_A[0..13] [7,17]

1.8VSUS

1.8VSUSSMDDR_VREF_DIMM 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199

CN14 VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50 VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 V

Da0tw7mb8g0_rev g ___tw7 - Rev 3a

Documents

tw7 quanta

pc4800 ddr2

5a peak current

ev disenable

internal ss

inside gmch

document number

d3a delete