D Algorithm

Combinational ATPG

OverviewMajor ATPG algorithms

• DefinitionsDefinitions• D-Algorithm (Roth) -- 1966

– D-cubes– Bridging faults– Logic gate function change faults

• PODEM (Goel) -- 1981– X-Path-Check

Backtracing– Backtracing• Summary

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Forward ImplicationForward Implication• Results in logic gate inputs that are

significantly labeled so that outputsignificantly labeled so that output is uniquely determined

• AND gate forward implication table:

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Backward ImplicationBackward Implication

• Unique determination of all gate inputs when the gate• Unique determination of all gate inputs when the gate output and some of the inputs are given

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Implication Stack Decision Tree and BacktrackImplication Stack Decision Tree and BacktrackImplication Stack, Decision Tree, and BacktrackImplication Stack, Decision Tree, and Backtrack

10 EUnexploredPresent AssignmentS h d d I f ibl

00 1BB 1Searched and Infeasible

0 00 11 1FF F

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Objectives and Backtracing in ATPGObjectives and Backtracing in ATPG

• Objective – desired signal value goal for ATPG– Guides it away from infeasible/hard solutions– Uses heuristics

• Backtrace – Determines which primary input and value to set to achieve objective

U h i ti h t PI– Use heuristics such as nearest PI

• Forward trace – Determines gate through which the fault effect should be sensitizedfault effect should be sensitized– Use heuristics such as output that is closest to the present

fault effect

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Branch-and-Bound SearchBranch and Bound Search• Efficiently searches binary search tree• Branching At each tree level selects which input• Branching – At each tree level, selects which input

variable to set to what value• Bounding – Avoids exploring large tree portions by

ifi i ll i i h d i i h iartificially restricting search decision choices– Complete exploration is impractical– Uses heuristics

• Backtracking – Search fails, therefore undo some of the work completed and start searching from a location where search options still existp

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D-Algorithm – Roth (1966)D-Algorithm – Roth (1966)D Algorithm Roth (1966)D Algorithm Roth (1966)

• Fundamental concepts invented:– First complete ATPG algorithm

D C b– D-Cube– D-Calculus– Implications – forward and backward– Implications – forward and backward– Implication stack– Backtrack– Test Search Space

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Singular Cover ExampleSingular Cover Exampleg pg p• Minimal set of logic signal assignments to represent a function

– show prime implicants and prime implicates of Karnaugh p p p p gmap (with explicitly showing the outputs too)

Gate Inputs Output Gate Inputs OutputAND

12

A0X

BX0

d00

NOR12

d1X

eX1

F00

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23

X1

01

01

23

X0

10

01

Primitive D Cube of FailurePrimitive D-Cube of Failure• Models circuit faults:

– Stuck-at-0– Stuck-at-1

Oth f lt h B id i f lt ( h t i it)– Other faults, such as Bridging fault (short circuit)– Arbitrary change in logic function

• AND Output sa0: “1 1 D”AND Output sa0: 1 1 D• AND Output sa1: “0 X D”

“X 0 D”• Wire sa0: “D”• Propagation D-cube – models conditions under

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p gwhich fault effect propagates through gate

Construction of PrimitiveD-Cubes of Failure

1 Make cube set α1 when good machine output1. Make cube set α1 when good machine output is 1 and set α0 when good machine output is 0

2. Make cube set β1 when failing machine output2. Make cube set β1 when failing machine output is 1 and β0 when it is 0

3. Change α1 outputs to 0 and D-intersect each cube with every β0. If intersection works, change output of cube to D

4 Change α0 outputs to 1 and D intersect each4. Change α0 outputs to 1 and D-intersect each cube with every β1. If intersection works, change output of cube to D

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g p

Gate Function Change D-Cube of Fail re

Gate Function Change D-Cube of Fail reFailureFailure

Cube-set

0

a

0

b

X

c

0

Cube-set a b c

α0

α1

0X1

X01

001

PDFs forAND changing

0 1 D

β0β1

01X

0X1

011

g gto OR 1 0 D

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X 1 1

Propagation D-CubePropagation D Cube• Collapsed truth table entry to characterize logic• Use Roth’s 5-valued algebra• AND gate: use the rules given earlier using α and β

b t i thi k ith d i it lbut in this case work with good circuit only

AD

B1

dDWrite all primitive

Cubes of AND gateand then create

D1D

1DD

DDDand then create

propagation cubes D1D

DD1

DDD

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D 1 D

D C b O i f D I iD C b O i f D I iD-Cube Operation of D-IntersectionD-Cube Operation of D-Intersectionψ – undefined (same as φ)µ or λ – requires inversion of D and D

• D-intersection: 0 0 = 0 X = X 0 = 0∩ ∩∩1 1 = 1 X = X 1 = 1X X = X

∩∩ ∩∩X X X

• D-containment –Cube a contains 0

00

1φ

X0

Dψ

Dψ

∩Cube a containsCube b if b is a subset of a

01XD

0φ0

φ11

01XD

ψψD

ψψDλ

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subset of a DD

ψψ

ψψ

DD

µλ

λµ

Implication ProcedureImplication Procedure

1 Model fault with appropriate primitive D1. Model fault with appropriate primitive D-cube of failure (PDF)

2 Select propagation D-cubes to propagate fault2. Select propagation D-cubes to propagate fault effect to a circuit output (D-drive procedure)

3. Select singular cover cubes to justify internal3. Select singular cover cubes to justify internal circuit signals (Consistency procedure)

• Put signal assignments in test cubeg g• Regrettably, cubes are selected very

arbitrarily by D-ALG

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y y

D-Algorithm – Top LevelD Algorithm Top Level

1. Number all circuit lines in increasing level order from PIs to POs;

2. Select a primitive D-cube of the fault to be the test cube;– Put logic outputs with inputs labeled as D (D) ontoPut logic outputs with inputs labeled as D (D) onto

the D-frontier;3. D-drive ();4. Consistency ();5. return ();

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D-Algorithm – D-drivewhile (untried fault effects on D-frontier)

select next untried D-frontier gate for propagation;while (untried fault effect fanouts exist)

select next untried fault effect fanout;generate next untried propagation D-cube;generate next untried propagation D-cube;D-intersect selected cube with test cube;if (intersection fails or is undefined) continue;if ( ll ti D b t i d & f il d) b kif (all propagation D-cubes tried & failed) break;if (intersection succeeded)

add propagation D-cube to test cube -- recreate D-frontier;Find all forward & backward implications of assignment;save D-frontier, algorithm state, test cube, fanouts, fault;break;

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else if (intersection fails & D and D in test cube) Backtrack ();else if (intersection fails) break;

if (all fault effects unpropagatable) Backtrack ();

D-Algorithm -- Consistencydi t f t t b ith 1’ & 0’g = coordinates of test cube with 1’s & 0’s;

if (g is only PIs) fault testable & stop;for (each unjustified signal in g)for (each unjustified signal in g)

Select highest # unjustified signal z in g, not a PI;if (inputs to gate z are both D and D) break;while (untried singular covers of gate z)while (untried singular covers of gate z)

select next untried singular cover;if (no more singular covers)

If (no more stack choices) fault untestable & stop;( ) p;else if (untried alternatives in Consistency)

pop implication stack -- try alternate assignment;else

Backtrack ();D-drive ();

If (singular cover D-intersects with z) delete z from g, add inputs to i l t fi d ll f d d b k d i li ti f

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singular cover to g, find all forward and backward implications of new assignment, and break;

If (intersection fails) mark singular cover as failed;

BacktrackBacktrack

if (PO exists with fault effect) Consistency ();else pop prior implication stack setting to try

alternate assignment;if (no untried choices in implication stack)

f &fault untestable & stop;else return;

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Circuit Example 7.1 and Truth Table

Circuit Example 7.1 and Truth TableTableTable

Inputsa0

b0

c0

OutputF00

000

0011

0101

00010

11

100

101

100

11

11

01

00

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Singular Cover & Propagation D-CubesSingular Cover & Propagation D-Cubes• Singular cover –

Used for justifying linesA10

B1

0

C d100

e F

010

1

0

0011

• Propagation D-cubesD 1

10D

1

0

001

• Propagation D-cubes– Conditions under which difference b t d/f ili

D1D

1DDD1

1D

DDD

DD between good/failing

machines propagates1D

DD

D0

DD0D

DD

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0D

DD

DD

Steps for Fa lt d sa0Steps for Fa lt d sa0Steps for Fault d sa0Steps for Fault d sa0

Step A B C d e F Cube type1

2

1 1 D

D 0 D

PDF of AND gate

Prop. D-cube for NOR23 1 1

D 00

D Prop. D cube for NORSing. Cover of NAND

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Example 7.3 – Fault u sa1• Primitive D-cube of Failure

1

0

Dsa1

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Example 7.3 – Step 2 u sa1• Propagation D-cube for v

1

0 0

Dsa1

D D

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Example 7.3 – Step 2 u sa1• Forward and backward implications

11

00 0

01

00

Dsa1

D

0

D

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Inconsistent

• d = 0 and m = 1 cannot justify r = 1 (equivalence)– Backtrack– Remove B = 0 assignment

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Example 7.3 – Backtrack• Need alternate propagation D-cube for v

1

0

sa1 D

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Example 7.3 – Step 3 u sa1• Propagation D-cube for v

1

01

sa1 D

D

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Example 7.3 – Step 4 u sa1• Propagation D-cube for Z

1

01 1

sa1D

DD1

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Example 7.3 – Step 4 u sa1• Propagation D-cube for Z and implications

01

1 1

01 1 00

1

sa1D

0

DD1

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PODEM G lPODEM G lPODEM -- Goel (1981)

PODEM -- Goel (1981)(1981)(1981)

• New concepts introduced:New concepts introduced:– Expand binary decision tree only around

primary inputsA C C– Use X-PATH-CHECK to test whether D-

frontier still there– Objectives -- bring ATPG closer to propagatingObjectives bring ATPG closer to propagating

D (D) to PO– Backtracing

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MotivationMotivation

IBM i t d d i d t DRAM• IBM introduced semiconductor DRAM memory into its mainframes – late 1970’s

• Memory had error correction and translation• Memory had error correction and translation circuits – improved reliability– D-ALG unable to test these circuitsD ALG unable to test these circuits

• Search too undirected• Large XOR-gate treesg g• Must set all external inputs to define output

– Needed a better ATPG tool

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PODEM High-Level FlowPODEM High Level Flow

1. Assign binary value to unassigned PI2. Determine implications of all PIs3. Test Generated? If so, done.4. Test possible with more assigned PIs? If

b t St 1maybe, go to Step 15. Is there untried combination of values on

assigned PIs? If not exit: untestable faultassigned PIs? If not, exit: untestable fault6. Set untried combination of values on assigned

PIs using objectives and backtrace. Then, go

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g j , gto Step 2

Example 7.3 AgainExample 7.3 Again• Select path s – Y for fault propagation

sa1

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Example 7.3 -- Step 2 s sa1Example 7.3 -- Step 2 s sa1• Initial objective: Set r to 1 to excite fault

1

sa1

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Example 7.3 -- Step 3 s sa1• Backtrace from r

11

sa1

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Example 7.3 -- Step 4 s sa1• Set A = 0 in implication stack

110

sa1

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Example 7.3 -- Step 5 s sa1• Forward implications: d = 0, X = 1

11

00

sa10

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Example 7.3 -- Step 6 s sa1• Initial objective: set r to 1

11

10

0sa1

0

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Example 7.3 -- Step 7 s sa1• Backtrace from r again

11

10

0sa1

0

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Example 7.3 -- Step 8 s sa1• Set B to 1. Implications in stack: A = 0, B = 1

11

10

0sa1

01

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Example 7.3 -- Step 9 s sa1• Forward implications: k = 1 m = 0 r = 1 q = 1 Y =Forward implications: k 1, m 0, r 1, q 1, Y

1, s = D, u = D, v = D, Z = 11

10

0Dsa1

1

0

111

0

1 1

DDD

1

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Backtrack -- Step 10 s sa1• X PATH CHECK shows paths s Y and s• X-PATH-CHECK shows paths s – Y and s –

u – v – Z blocked (D-frontier disappeared)

11

10

0sa1

0

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Step 11 -- s sa1• Set B = 0 (alternate assignment)

110

sa10

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Backtrack -- s sa1• Forward implications: d = 0 X = 1 m = 1 r = 0

1

• Forward implications: d = 0, X = 1, m = 1, r = 0,s = 1, q = 0, Y = 1, v = 0, Z = 1. Fault not sensitized.

00

0

1sa1

00 1

01

1

0

00 1

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Step 13 -- s sa1• Set A = 1 (alternate assignment)

111

sa1

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Step 14 -- s sa1• Backtrace from r again

111

sa1

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Step 15 -- s sa1• Set B = 0. Implications in stack: A = 1, B = 0

111

sa10

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Backtrack -- s sa1F d i li ti d 0 X 1 1 0• Forward implications: d = 0, X = 1, m = 1, r = 0. Conflict: fault not sensitized. Backtrack

01

1

0

0

sa10 11

10

1

0

001

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Step 17 -- s sa1• Set B = 1 (alternate assignment)

111

sa11

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Fault Tested -- Step 18 s sa1• Forward implications: d = 1 m = 1 r = 1 q = 0 s =• Forward implications: d = 1, m = 1, r = 1, q = 0, s =

D, v = D, X = 0, Y = D0

11

1

sa111

1

0

D D0

DD

XD

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Backtrace (s, vs)Pseudo-Code

v v ;v = vs;while (s is a gate output)

if (s is NAND or INVERTER or NOR) v = v;if (s is NAND or INVERTER or NOR) v v;if (objective requires setting all inputs)

select unassigned input a of s with hardest controllability to value v;

elseselect unassigned input a of s with easiestselect unassigned input a of s with easiest

controllability to value v;s = a;

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return (s, v) /* Gate and value to be assigned */;

Objective Selection CodeObjective Selection Code

if (gate g is unassigned) return (g, v);select a gate P from the D-frontier;select an unassigned input l of P;if (gate g has controlling value)

c = controlling input value of g;else if (0 value easier to get at input of

XOR/EQUIV gate)XOR/EQUIV gate)c = 1;

else c = 0;

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;return (l, c );

PODEM Algorithmwhile (no fault effect at POs)

if (xpathcheck (D-frontier)(l, vl) = Objective (fault, vf lt);(l, vl) Objective (fault, vfault);(pi, vpi) = Backtrace (l, vl);Imply (pi, vpi);if (PODEM (fault v ) == SUCCESS) return (SUCCESS);if (PODEM (fault, vfault) == SUCCESS) return (SUCCESS);(pi, vpi) = Backtrack ();Imply (pi, vpi);pif (PODEM (fault, vfault) == SUCCESS) return (SUCCESS);Imply (pi, “X”);return (FAILURE);

else if (implication stack exhausted)return (FAILURE);

else Backtrack ();

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Summaryy• D-ALG – First complete ATPG algorithm

– D-CubeD Cube– D-Calculus– Implications – forward and backward– Implication stack– Backup

• PODEM• PODEM– Expand decision tree only around PIs– Use X-PATH-CHECK to see if D-frontier existsf– Objectives -- bring ATPG closer to getting

D (D) to PO

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– Backtracing

A diAppendices

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Implication StackImplication Stack• Push-down stack. Records:

– Each signal set in circuit by ATPG – Whether alternate signal value already tried – Portion of binary search tree already searched

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Objectives and Backtracing in ATPGObjectives and Backtracing in ATPG• Objective – desired signal value goal for ATPG

– Guides it away from infeasible/hard solutionsy– Uses heuristics

• Backtrace – Determines which primary input and l t t t hi bj tivalue to set to achieve objective

– Use testability measures

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B id i F lt Ci itB id i F lt Ci itBridging Fault CircuitBridging Fault Circuit

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Bridging Fault D-Cubes of Bridging Fault D-Cubes of FailureFailure

Cube-setα0

a0

bX

a*0

b*X

Cube-set b a* b*a

α1X1X

0X1

X1X

0X1

PDFs forBridging fault

01

1D

D1

10

β0β1

X0X1

101X

X011

1011

Bridging fault 1 D 10

1 X 1 1

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E ample 7 2 Fa lt A sa0E ample 7 2 Fa lt A sa0Example 7.2 Fault A sa0Example 7.2 Fault A sa0

• Step 1 – D-Drive – Set A = 1

D1 D1 D

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Step 2 E ample 7 2Step 2 E ample 7 2Step 2 -- Example 7.2Step 2 -- Example 7.2

• Step 2 – D-Drive – Set f = 0

D1

0

DD

1 D

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Step 3 E ample 7 2Step 3 E ample 7 2Step 3 -- Example 7.2Step 3 -- Example 7.2

• Step 3 – D-Drive – Set k = 1

1D

D1

0

DD

1 D

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Step 4 E ample 7 2Step 4 E ample 7 2Step 4 -- Example 7.2Step 4 -- Example 7.2

• Step 4 – Consistency – Set g = 1

1D

1

D1

0

DD

1 D

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Step 5 E ample 7 2Step 5 E ample 7 2Step 5 -- Example 7.2Step 5 -- Example 7.2

• Step 5 – Consistency – f = 0 Already set

1D

1

D1

0

DD

1 D

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Step 6 E ample 7 2Step 6 E ample 7 2Step 6 -- Example 7.2Step 6 -- Example 7.2St 6 C i t S t 0 S t 0• Step 6 – Consistency – Set c = 0, Set e = 0

1D

10

D1

0

DD0

1 D

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D Chain Dies E ample 7 2D Chain Dies E ample 7 2D-Chain Dies -- Example 7.2D-Chain Dies -- Example 7.2• Step 7 – Consistency – Set B = 0

X

p y• D-Chain dies

1D

10

D1

0

DD0

0

1 D

Test cube: A B C D e f g h k L2/10/2012 67

Test cube: A, B, C, D, e, f, g, h, k, L

Example 7.3 – Fault s sa1• Primitive D-cube of Failure

1

Dsa1

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Example 7.3 – Step 2 s sa1• Propagation D-cube for v

1

0sa1 D1 D

D

0

D

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Example 7.3 – Step 2 s sa1• Forward & Backward Implications

01

11D

sa10

D1 111

0

DD

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Example 7.3 – Step 3 s sa1• Propagation D-cube for Z – test found!

01

11D

sa10

D1 111

0

DD

1D

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