Cyclone 10 GX Dynamic Reconfiguration with ATX PLL Switching … · 2020-04-27 · FMC loopback card. The design comes with frequency counters which are used to monitor the tx_clkout
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Table of Contents Introduction.................................................................................................................................................... 3
Theory of Operation ...................................................................................................................................... 4
How to Setup the Hardware for Link Test ..................................................................................................... 5
How to Reconstruct and Running the Reference Design ............................................................................. 5
Revision History .......................................................................................................................................... 13
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Introduction
The objective of this design example is to demonstrate the implementation of Cyclone 10 GX Native PHY ATX PLL switching, channel reconfiguration with embedded streamer as well as recalibration. The two ATX PLLs are used to support two different data rates which could not be achieved with TX local divider. The purpose of this design example is to assist users to have quick start with the Cyclone 10 GX transceiver dynamic reconfiguration. The design starts with transceiver channel running at 2Gbps data rate and then reconfigure to 1.5Gbps using ATX PLL switching and channel reconfiguration. After reconfiguration is completed, a channel recalibration followed by reset is performed. Incremental data is sent from the TX and loopback to the RX for monitoring. In-System Sources and Probes (ISSP) is used to provide real time control to the transceiver while SignalTap II Logic Analyzer is used for status and data monitoring. The dynamic reconfiguration and recalibration commands are performed through System Console.
Requirements The reference design requires the following hardware and software to run the test:
• Quartus® Prime Software Version: 17.1 Pro Edition
• Cyclone 10 GX Development Kit https://www.altera.com/products/boards_and_kits/dev-kits/altera/cyclone-10-gx-development-kit.html
18. After the dynamic reconfiguration is completed, you should see messages as shown in Figure 11
19. Go to Spf1.spf and set source[0] to 0 to release the transceiver channel from reset mode
20. Go back to stp1.stp and click on Run Analysis button again. You should see the tx_clkout and
rx_clkout frequencies = 150MHz as shown in Figure 12. This shows that the dynamic
reconfiguration of the transceiver data rate to 1.5Gbps using ATX PLL switching is successful
Figure 3. Commands to Reduce the JTAG Frequency to 16M
Figure 4. Default Clock Controller GUI for Si5332
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Figure 5. Clock Controller GUI for Si5332 after Successful Configuration
Figure 6. In-System Sources and Probes Editor
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Figure 7. tx_clkout and rx_clkout Frequencies for 2Gbps Data Rate
Figure 8. Launching the System Console
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Figure 9. Sourcing the TCL for Dynamic Reconfiguration
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Figure 10. Command to Reconfigure the Transceiver Channel to 1.5Gbps
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Figure 11. Dynamic Reconfiguration is Completed
Figure 12. tx_clkout and rx_clkout Frequencies for 1.5Gbps Data Rate
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Conclusion The design example provides a reference on how to perform dynamic transceiver rate change with ATX PLL switching, channel reconfiguration with embedded streamer as well as recalibration.
References • Intel Cyclone 10 GX Transceiver PHY User Guide